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Computer Architecture

by: Ashleigh Dare

Computer Architecture ECS 154B

Ashleigh Dare
GPA 3.75


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This 22 page Class Notes was uploaded by Ashleigh Dare on Tuesday September 8, 2015. The Class Notes belongs to ECS 154B at University of California - Davis taught by Staff in Fall. Since its upload, it has received 50 views. For similar materials see /class/191708/ecs-154b-university-of-california-davis in Engineering Computer Science at University of California - Davis.

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Date Created: 09/08/15
Digital Logic the Bare Minimum Norman MatloiT University of California at Davis updated October 31 1999 Contents 1 Overview 2 Com binational Logic 21 AFeW Basic Gates 211 AND Gates 212 OR Gates 213 NOT Gates 214 NAND Gates 215 NOR Gates 216 XOR Gates 22 Some MSI Combinational Components 221 Multiplexors 222 Decoders 23 Examples 231 HalfAdder 232 Full Adder 233 2Bit Adder 24 Timing 3 Sequential Logic 2 CONIBINAHONAL LOGIC 31 Latches and FlipFlops 9 32 EdgeTriggering 11 33 Example A 2Bit Ripple Counter 11 34 Example Tracking Counts Mod and Div 5 12 4 Bus Based Circuits 14 5 Example Memory Chips and Systems 17 51 An SRAM Memory Chip 17 52 A Memory System 20 53 Memory Interleaving 21 54 DRAMs 21 6 Example A Simple CPU 21 1 Overview As you know all information inside a computer is processed and stored as 01 bits Here we will look at the basic building blocks used to manipulate this 01 information 2 Combinational Logic The term combinational logic refers to circuitry that transforms bits as opposed to storing bits For exam ple the ALU portion of a CPU transforms data eg transforming two input wordsized bit strings into an output which is the sum of the two inputs 21 A Few Basic Gates 211 AND Gates A basic AND gate has two inputs and one output 2 Let s call the two inputs X and Y and the output Z Then Z 1 if and only ifX 1 Y 1 hence the name AND The AND operation is representedin boolean equation settings by multiplication ie we write 1Our course has no digital design prerequisite and thus some of this material must be presented here For those of you who do have this background I ask for your patience we will quickly move to other things ZVersions with fanin of more than two ie having more than two inputs exist too Digital Logic 2 2 CONIBINATIONAL LOGIC 21 A Few Basic Gates Z X Y 1 As you can see this equation does succinctly summarize the AND operation For example if X and Y are both 1 then since 1 gtlt 1 1 then Z will be 1 too If on the other hand for instance X 1 but Y 0 Z will be 0 The standard symbol for an AND gate is D Note that for any X 0 or 1 0X0 D and 1 X X 3 212 OR Gates Again a basic OR gate will have two inputs but in this case Z 1 if and only ifX 1 EY 1 which includes the case in which both X and Y are 1 The boolean equation is ZXY W where the is standard addition except that 1 1 is taken to be 1 The standard symbol for an OR gate is D Note that for any X 0 or 1 0 XX 5 and Digital Logic 3 2 CONIBINATIONAL LOGIC 21 A Few Basic Gates 1X1 6 213 NOT Gates A NOT gate has one input X and one output Z with the output being the logical negation of the input In other words an input of 1 produces an output of 0 and Vice versa In boolean equations a NOT operation is indicated by an overbar Z X 7 The standard symbol for a NOT gate is gtw 214 NAND Gates Here there are two inputs X and Y and one output Z The term NAND stands for notand meaning that Z l ifthe statement X l emY l is r true The boolean equation is z x y 8 The standard symbol for a NAND gate is D Note that the little circle here means not Obviously if on the day on which we shopped at the Gates R Us store they were out of NAND gates we could synthesize a NAND by using an AND together with a NOT W But of course this would not be so desirable as using a real NAND The synthesized version would probably have more transistors than the real one and thus would be slower and take up more space on a chip thus reducing the total number of gates we could put on the chip Digital Logic 4 2 CONIBINATIONAL LOGIC 22 Some MSI Combinational Components 215 NOR Gates Again inputs X and Y output Z with Z being equal to 1 if the statement X l or Y l is IQ true The boolean equation is z x y 9 The symbol for a NOR gate is D Again the same effect could be synthesized by leading the output of an OR into a NOT 216 XOR Gates Here we have inputs X and Y output Z with Z being equal to 1 if the statement X l or Y l but not both is true The term used for this is exclusiveor abbreviated to XOR The boolean equation is Z XY X 10 The symbol for an XOR gate is Again the same effect could be synthesized by using two NOT gates two AND gates and an OR gate 22 Some MSI Combinational Components MSI stands for mediumscale integration We are integrating a moderate number of gates to form some frequently used building blocks Digital Logic 5 2 CONIBINATTONAL LOGIC 23 Examples 221 Multiplexors A multiplexer or MUX selects one of its data inputs and copies that input to the output with the selection being made according to its address input As a simple example consider a MUX having two 1bit data inputs D1 and D0 To indicate which one we want we need another input A A 1 will mean we want D1 and A 0 will mean we want D0 Let s call the output Z Then the equation for Z is ZA11K10 11 Make SURE this makes sense to you While it won t be drawn here you should be able to see above that we could construct this MUX by using two AND gates one NOT and one OR A MUX with four data inputs D3 D2 D1 and D0 would need two selector bits A1 and A0 and the output would be 2 A AO 03 A ow Aom m no 12 Again make SURE this makes sense to you 222 Decoders This is best explained by example say for a 3to8 decoder Let s call the 3bit input lines X2 X1 and X0 and the output lines Z7 Z6 Z1 and Z0 The 3bit input can be considered the binary coding for one of the numbers 07 The output lines then tell us which one of the numbers 07 is represented by the input For example suppose X2 0 X1 1 and X0 1 representing the number 3 then Z3 will be 1 to indicate that fact and all the other Zi will be 0 Building a decoder from gates is quite straightforward from the equations which themselves are also straightforward For example from the example above you can see that the equation for Z3 is 23 x1x0 13 23 Examples 231 HalfAdder Here we will design logic to add two 1bit numbers together Let s call the sum bit Sum But note also that there may be a carry generated this will happen if both addends are equal to 1 we will call this Cout for carry output Digital Logic 6 2 CONIBINATIONAL LOGIC 23 Examples The logic will look like this AB Cout I l Sum The dark circles represent wire connections If two lines cross in the picture but there is no dark circle at their intersection then they do IQ touch each other 232 Full Adder A full adder has one more input than does a half adder We will call this input Cin for carry in The reason we need this eXtra input is that we will be using a full adder as a building block to do multibit addition For example consider the following addition of two 3bit numbers 011 and 001 l l 0 l l 0 0 l l 0 0 Let s refer to the bit positions as 2 1 and 0 from left to right The point then is that the addition at position 0 resulted in a carry into position 1 shown in the picture and that carry must be incorporated into the sum performed at position 1 That carry would be the Cin for position 1 and the Cout for position 0 We will not draw the logic but here are the equations remember we are now back to a single bit even though the logic will be used below as a building block for a multibit adder Sum AF Cm A I A F A 137in 14 Com A 13 CM A F Cm A I A 133in 15 Let s use the following not standard symbol for a full adder Digital Logic 7 2 CONTBINATTONAL LOGIC 24 Timing Cin FA iA Cout S 233 Z Bit Adder We can put two full adders together to form a 2bit adder ie logic which will add together two 2bit inputs producing a 2bit sum and a possible carry A1 B1 A0 B0 FA FA 4 C S1 S0 Here AlA0 forms the rst 2bit addend and B1B0 forms the second The sum is S1S0 and the carry into bit position 3 is C Note that a constant 0 is hardwired into the Cin input of the full adder on the right 24 Timing The delay of a typical gate is on the order of 10 nanoseconds ns ie 10 billionths of a second This sounds extremely fast almost beyond human imagination but in View of the fact that computers perform tens of millions of operations per second gate delays do add up into tangible amounts of time and thus directly affect the overall speed of the machine To get the fastest machine digital logic must be optimized In other Digital Logic 8 3 SEQUENTIAL LOGIC words even though several sets of gates may be equivalent in effecting a certain function say addition their timings may differ considerably and it is desire to nd an optimal set We don t cover optimization in this course but still this principle should be kept in mind Note that in the 2bit adder example above the overall delay is approximately double the delay of a single full adder since the left full adder must wait for the outputs of the right one to be valid before that time the outputs of the left one are garbage There are other adder designs such as carry lookahead adders which aim to circumvent this problem 3 Sequential Logic Sequential logic stores data Registers in a CPU RAM and so on store data 31 Latches and Flip Flops We rst look at the S R latch It has two inputs R and S and two outputs Q and Its function is that of a 1bit memory with Q being the bit currently stored 3 Whenever we want to store a new bit in the latch replacing the old one we simply pulse a l on R or S momentarily depending on whether we want to store a 0 or a l in the latch R and S stand for reset and set As long as R and S stay at 0 the storedvalue will remain as is An SR latch can be constructed as follows R 39 Q L 39 s Q Suppose for instance that currently Q l and we wish to change Q to 0 That would mean momentarily pulsing the R line to 1 Let s see that this does indeed work Since Q 1 Q will be 0 Thus the two inputs to the upper NOR gate will be 1 from R and 0 from 6 making the output 0 In other words Q does change to 0 as desired What about Q It will stay at 0 for a short time but as soon as Q changes to 0 and feeds that value back into the lower NOR the output of that lower NOR will now be 1 since S 0 In other words 7 does indeed 3 is then the negation of the bit being stored Since this is generated anyway due to the nature of the logic usedin construction we get it for free and thus might as well formally make it one of the outputs That way if 5 happens to be needed elsewhere in our machine we would be able to save a NOT gate there Digital Logic 9 3 SEQUENTIAL LOGIC 31 Latches and FlipFlops change to 1 But that is not the end of the story for we must make sure that those new values of Q and Q are maintained Well the feedback nature of the circuit has exactly that result For example after Q changes to 1 that ensures that the output of the upper NOR gate is 0 regardless of what R is so Q will indeed continue to stay at 0 Similarly you should check that the design ensures that 7 will stay at 1 until such time as S is pulsed Flip ops are like latches except that they are clocked so that they accept new input only at certain times A clock is a crystal device that pulses at regular intervals sending l0l0l For example a 300 megahertz mhz PC has a clock which pulses 300 million times per second Flip ops by virtue of having clocked input acceptance allow the designer much more convenient control After all in a complex machine the inputs will sometimes be garbage still 0 or 1 maybe but not meaning ful and the clocked nature allows us to make sure that the stored values will change only when we want them to ie when nongarbage values are at the inputs Note that this also means that in many cases the clock pulse itself is not connected to the clock input of a ip op but rather that pulse is ANDed with some other wires that represent conditions under which the input data is valid You will see an example of this later in this tutorial where we build a RAM circuit A D ip op can be constructed as follows The D input data is the new value to be stored at the time of the clock pulse You should walk through an instance of the operation of this circuit again say where the value 1 had been stored originally Q l but in which we want the new value to be 0 D 0 Trace through the sequence of events which will occur when the clock pulse comes you will nd that Q is the rst to change becoming l with its feedback into the upperright NAND making Q change to 0 as desired 4Of course the faster the clock the faster the machine However in choosing the clock speed we have to account for all gate delays signal propagation times along wires and so on so that all signals reach their destinations within one clock cycle In other words we must choose the clock cycle to accommodate the longest delay in the overall circuit Digital Logic 10 3 SEQUENTIALLOGIC 32 EdgeTriggering 32 Edge Triggering Many ip ops are edge triggered What this means is that they are designed in such a way that an input value labeled D in the picture above will have effect on the ip op only during a narrow window of time speci cally the time during which the clock pulse is rising or falling 5 This is done to avoid feedback problems in compleX circuits The output of a ip op may be routed through a series of gates and ultimately fed back in to the same ip op as an input For instance consider the Intel assemblylanguage instruction ADD AX BX If you have not worked with Intel machines before this instruction adds the values in the AX and BX registers and stores the sum back into AX Suppose AX and BX originally contain the values 5 and 2 respectively The new value in AX should be 7 But if the circuitry were poorly designed the addition might continue with the 7 being added to 2 thus putting 9 into AX and so on By limiting the sensitivity of ip ops 6 to very narrow windows of time this feedback problem cannot occur 33 Example A 2 Bit Ripple Counter Recall that an nbit string can represent unsigned integers in the range 0 l 2 27quot 1 An nbit ripple counter is simply a counter which will continually cycle through these values For example a 2bit ripple counter will cycle through 0 l 23 0 l 2 3 0 or in bit form 00 01 10 110001 10 ll 00 We can construct such a counter from two D ip ops two half adders and a clock 5These are called the leading edge and falling edge of the clock pulse 6Again remember that registers are made up of ip ops Digital Logic ll 3 SEQUENTIAL LOGIC 34 Example Tracking Counts Mod and Div 5 b1k DFF DFF I I i 1 HA HA 4 4 R1 R0 In the DFF boxes the two left inputs are D and Clk while the two right outputs are Q and Note the following o the constant 1 is hardwired as one of the inputs to the righthand half adder 0 we are ignoring the Q outputs of the ip ops 0 the outputs are R1 and R0 eg when the count is 2 we will have R1 1 and R0 0 since 10 is the binary representation of 2 O the input labeled Clk does not actually have to be connected to a clock and in most applications will not be instead the input will simply be a line which we have arranged elsewhere in the circuit to pulse to a 1 every time some particular event of interest occurs 34 Example Tracking Counts Mod and Div 5 The circuit to be designed here will have an input line like a ripple counter does but instead of tracking the raw count 0 of the number of times the input line is pulsed we will track 0 mod 5 and c div 5 Here is the circuit Digital Logic 12 3 SEQUENTIAL LOGIC 34 Example Tracking Counts Mod and Div 5 The input line is visible at the left of the picture Its quiescent state is 0 but sometimes pulses ie ls come in on that line The pulses might come at regular intervals such as from a clock or at irregular times depending on what application we needed this circuit for The output pins are M0 M1 and M2 which contain 0 mod 5 and D0 D1 D2 and D3 which contain 0 div 5 though only up to 15 for the latter There are twoboxes labeled CTR these are 4bit ripple counters The pins labeled C in them are for clearing ie resetting if this pin is pulsed all bits of the ripple counter will be reset to 0 Similarly there is an init input at the top of the picture to clear both the mod and div counters The box labeled DCD is a 3to8 decoder Its output pins are active low meaning that 0 means yes and 1 means no For example let s label these pins Z7Z6Z0 from left to right Then Z7 will be equal to 0 if and only if the three input pins contain 111 the binary representation of 7 Whenever the mod counter reaches 4 Z4 will be 0 which means that the output of the NOT gate we ve connected to Z4 will be 1 This 1 is then ANDed with the Circuit s input line So the next time the input line is pulsediwhich will be a count which is a multiple of 57a pulse will be felt at the c div 5 counter That counter will then increment exactly what we want Note that the gate delay in DCD is helping us here When the count is 4 the next pulse will change the count momentarily to 5 and the rest of the circuit will change that to 0 However even when the count rst Digital Logic l3 4 B USBASED CIRCUITS becomes 5 Z4 will still be equal to 0 indicating a count of 4 not 5 for a short period of time equal to the gate delay in DCD This delay is good because when the pulse comes at count 4 we want Z4 to stay at 0 long enough so that it makes CTR increment This illustrates the delicate timing issues which can arise in digital circuits 4 BusBased Circuits A bus is a set of parallel wires used for transfer of data among various components You are probably familiar with the idea of a system bus for a computer which connects components such as the CPU memory and IO devices7 Since several components are attached to the same bus how do we make sure that only one of them actually is connected to the bus at a time The answer is that we use tri state buffers which can connect a component to a bus or electrically isolate the component away from the bus To illustrate this consider the design of a very simple CPU which for simplicity of eXposition will have only two registers R0 and R1 each only one bit wide implemented as a DFF D AS AD Clk In each register the upper left input is for data the lower left for the clock and output is out the right side Again keep in mind that the bus shown here is inside the CPU different from the system bus the purpose of the bus here is for data transfer from one register the source to another the destination There also would be an ALU etc but we do not show other items here We see data D and address AS AD lines here just as we would for a system bus However due to the simple nature of our example in which our word size is only one bit we only need one data line if we had say 32bit words we would need 32 data lines D31D30D0 Similarly since we have only two registers we only need one address line for the source register and one for the destination register if we had say 16 registers we would need four address lines each for source and destination What is new here though is the presence of triangles which look like NOT gates but are instead tristate buffers the latter are distinguished from the former by the presence of an eXtra input line coming in at the 7In this context the term bus o en connotes not just the wires themselves but also standards for the roles played by the wires electrical characteristics and so on Digital Logic l4 4 B USBASED CIRCUITS of the triangle ie entering at a sloped leg of the triangle C The operation is very simple If C 1 then the input A is copied to B If C 0 then B is entirely unaffected by A I have chosen the name AS for address of source and AD for address of destination thinking of R0 and R1 having addresses 0 and 1 respectively Suppose we wish to copy the contents of R1 to R0 Then we will put 1 on the AS line and 0 on the AD line What will happen when the clock pulse comes Look at the tristate buffer just below and to the right of R1 Its input A is R1 s Q value ie the valued stored in register R1 Since AS 1 the tristate buffer will allow its input to ow through ie R1 will be copied to the D line Meanwhile R0 will I be copied to the D line because the input to R0 s tristate buffer is 0 The little circle to the left of that buffer represents an inverter ie a NOT gate Since AS 1 the inverter converts the signal inputted to R0 s tristate buffer to a 0 Of course that is what we want we would have chaos if both R0 and R1 were copied to D at the same time You should now verify on your own that because we put 0 on the AD line when the clock pulses the value on the D line which was from R1 as we saw above will ow into R0 So we will indeed have copied R1 to R0 as desired You might be wondering what will control which values go onto AS and AD This is done by the control logic a combinational circuit which has as its input the op code from the current instruction and which has AS and AD among other things as its output You will not work with the control logic and construct an entire CPU until ECS 154B but let us at least eXplore some options First let us add an ALU to the tworegister onebus system depicted above Digital Logic 15 4 B USBASED CIRCUITS We do not have room to show the connecting lines gates and tristate buffers suf ce it to say that they are similar to those shown earlier You should try drawing some for yourself though as a check of your understanding For simplicity we are continuing to assume a onebit word size The ALU has two inputs on its left and one output on its right Again remember that the ALU is a combinational circuit for example performing addition using properlychosen gates as we have seen before Note that we have added two new registers R2 and R3 They are known as private registers private in the sense that they will not be visible to the programmer The instruction format for the machine would still have each register eld source and destination within an instruction consist of only one bit which would control whether R0 or R1 is involved the programmer has no way to specify R2 or R3 here Instead R2 and R3 will serve as temporary storage cells which save up data destined for the ALU As you can see their Q outputs feed into the ALU rather than being connected back to the D bus line as with R0 and R1 Now consider a machine instruction ADD R0Rl meaning that the old value of R0Rl will now become the new value of R0 This instruction would require three clock cycles rst clock copy R0 to R2 second clock copy Rl to R3 third clock enable the tristate buffer connecting the output of the ALU to D and let D ow into R0 There are also inputs again not shown to the ALU determining which operation we want to perform eg add subtract logicaland logicalor etc Thus in the third clock cycle the control logic would also be putting the code for add on the control inputs to the ALU 8 During the third cycle we would also enable the connection from the output of the ALU to the bus 8Though we have not set it up this way here in most designs even a move operation is done through the ALU39 in the case here then during the rst and second clock cycles the control logic would put the code for move onto the ALU s control input lines Digital Logic l6 5 EXANLPLE lVlEMORY CHIPS AND SYSTEMS By the way you can now begin to see how the digital logic design affects the choice of clock speed The clock cycle length must be chosen to cover the worst case that would occur Here that means for instance that the cycle must be at least as long as the time needed to do an addition and to copy two values between a register and a bus How could we make this faster Suppose we had two buses rather than one with all components the registers and the ALU connected to both buses Then we could load both R2 and R3 at the same time ie during the same clock cycle R0 would be copied to R2 via the rst bus while at the same time Rl would be copied to R2 via the second bus During the second cycle we would enable the output from the ALU to a bus say the rst one and enable the input to in this example R0 The instruction ADD R0Rl would then take only two clock cycles rather than threeia 33 speedup And by adding a third bus we could get the time down to only one cycle Now all of this is somewhat oversimpli ed we have not accounted for time needed to fetch the instruction from memory and decode it etc but you can at least begin to see the principle hereia classic computer science timespace tradeoff If we are willing to use greater amounts of precious space on the CPU chip more buses take up more room we can reap a savings in m With this example the need for edgetriggering or other antifeedback mechanism should be more apparent It would be worthwhile for you now to go back and review that section earlier in this document 5 Example Memory Chips and Systems 51 An SRAM Memory Chip To illustrate the principles developed here we will consider the design of simple memory chips and memory systems First consider the design of a 4X2 memory chip meaning that it contains four twobit words This is much much smaller than the sizes of typical commercial memory chips but the principles are the same We will call the four words Word 0 Word 1 Word 2 and Word 3 Remember though that these are word numbers within this chip not within a system constructed from this chip and others more on this later The chip will have the following pins address pins Al and A0 two pins encode 2 2 rl addresses which indicate which of the four words is to be accessed datain pins D11 and D10 for writing data to the chip dataout pins D01 and D00 for reading data from the chip a writeenable pin WE used to inform the chip that we wish to write to it an outputenable pin OE used to inform the chip that we wish to read from it and a chipselect pin CS to inform the chip that it rather than some other memory chip will be involved in the current memory transaction Again the 4X2 designation for this chip means that the chip contains four words each two bits wide Note that this might be a quite different viewpoint than that held by the CPU of our system The CPU might say view an 8X4 system would consist of eight fourbit words The memory for such a system could then be constructed by using in combination four 4X2 chips as we will do later The CPU though would be unaware of the chip structure of the system The use of separate pins for data input and output here is not standard but simpli es the design somewhat Digital Logic l7 5 EXAWLEl1EMORY CHIPS AND SYSTEMS 51 An SRAM Memory Chip If we were to have a single set of pins for both functions as we will assume later the design below could be modi ed in a straightforward way To design this chip let us rst design a onebit cell which will serve as the basic building block for the chip D Q OUT Here there is a D ip op which will hold the stored bit together with three inputs IN WL and WR and one output OUT When we write data to this bit the data will come in on the IN line and the WR line will be 1 When we read data from the bit it will come out the OUT line and WR will be 0 Recall that the ip op is clocked and responds to pulses their leading or trailing edges rather than to levels of a signal In our case here it is likely that the WR line will send such pulses because it will be the result of ANDing with a clock Suppose for example that our system bus which connects the CPU to memory contains a W line and a CLOCK line We could AND those two lines together and feed the result into WR Then if the CPU asserts the W line when the clock pulse occurs that pulse will appear on WR as well WL word line has the following function As you will see below our full memory chip will consist of a 4X2 array of the onebit cells we are now examining Each row of that array consists of one word within the memory chip ie one address within the chip The WL line for the two bits of a given word will go to 1 when we wish to access that word If WL is 0 then you can see from the diagram above that no data will be allowed into or out of the bit cell note the role of the tristate device for the latter case By the way note that if WR is l ie we are doing a write to this bit cell data actually is allowed out of the cell which seems wrong However this will be remedied by other tristate devices in the chip as a whole Now here is our design for that chip Digital Logic 18 5 EXAWLEl1EMORY CHIPS AND SYSTEMS 51 An SRAM Memory Chip DIl DIO IN OUT IN OUT WL WL WR WR IN OUT 1 IN OUT WL WL i WR WR A1 2gt4 v dcdr A0 i I IN OUT 1 IN OUT WL WL WR WR IN OUT 1 IN OUT WL WL WR WR WE CS OE LY D1 D0 As mentioned earlier the main part of the chip consists of a 4X2 array of the bit cells designed above The top row is Word 0 of the chip the row just below it is Word 1 and so on A 2to4 decoder at the middle left of the diagram selects the proper row of bit cells ie the proper word depending on which address is desired The designis straightforward Let us con rm for instance that if CS is 0 no data will be allowed into or out of this chip First note that if CS is 0 then the inputs to WR in the bit cells will also be 0 thus no data will be allowed into any bit cell exactly as planned Second note that if CS is 0 the inputs to the two tristate devices near the D01 and D00 pins will also be 0 insuring that no data ows out of the chip Again all of this is important we will be connecting several of these chips to a system bus and must insure that we do not have data from two chips owing onto the same bus lines at the same time Consistent with our earlier comment on the 1bit cell design the WE input here would likely be set up as the ANDing together of say W and CLOCK lines in the system bus The same comment applies to our memory system in the following subsystem even though the CLOCK line is not drawn Digital Logic l9 5 EXANLPLE lVlEMORY CHIPS AND SYSTEMS 52 A Memory System 52 A Memory System Now let us see how a memory system can be constructed from memory chips Again for simplicity we will continue to assume 4X2 chips 9 and we will assume an overall system of eight fourbit words 10 Here is how we can construct the system from 4X2 chips CS A0 CS A0 CS A0 CS A0 D1 D1 D1 D1 OE OE OE OE The bus here is a system bus like you learned in ECS 50 or equivalent course not the buses internal to CPUs and memory chips which we have discussed earlier The CPU and IO devices are also connected to this bus but are not shown here nor is the CLOCK line shown We are assuming that no direct memoryto memory access is possible all reads from and writes to memory are performed by the CPU Let s call the four chips I II III and IV from left to right By inspecting which chip pins are connected to bus lines D3D0 you can see that chips I and III contain the lower two bits of each fourbit word while chips II and IV contain the higher two bits By noting the connections of bus line A2 to the CS pins of the chips you can see that of the entire address space 07 now speaking from the CPUsystem viewpoint chips I and II contain system words 03 and chips III and IV contain system words 47 Suppose for example we have a C program with an int variable X and that the address of X happens to be 3 in this system Then X will be stored in chips I lower 2 bits and II upper 2 bits If the C source code has something like X5 then on say an Intel CPU the compiler will produce code like 9For even more simplicity we now assume that each data pin does both input and output loRemember the CPU will see only the latter and not know how the system breaks down in terms of chips Digital Logic 20 6 EXAAlPLE A SIAlPLE CPU 53 Memory Interleaving MOV X5 In executing this instruction the CPU will put 011 on lines A2 A1 and A0 and put 0101 on D3D0 and so on 53 Memory Interleaving The fourchip system in the above example is said to use high order interleaved which means that the most signi cant highorder bits of the address determine which chips in this case a chip pair a given address is stored in With low order interleaving the least signi cant bits are used instead Note that think about this and make sure you understand it in a highorder interleaved system consecutive addresses are stored within the same chip until we reach a chip boundary while in the loworder case consecutive addresses are stored in consecutive chips mod the number of chips 54 DRAMs The kind of memory chip described above in which each 1bit cell is implemented as a ip op are known as static RAM SRAM By contrast the bit cells in a namic RAM DRAM chips consist of tiny capacitors rather than ip ops a charged capacitor represents a 1 while a discharged one represents a 0 The term static refers to the fact that each ip op in an SRAM continuously maintains itself as noted when rst discussed ip ops in this tutorial it will not change as time passes until we want it to change Except for the structure of individual bits the connections between the bits in a DRAM is very similar to that of an SRAM One difference though arises from the fact that a bit in a DRAM will lose its charge as time passes so it must be periodically refreshed ie recharged by additional circuitry The refresh operation of a DRAM also brings some reduction in system performance as a bit or row of bits is not accessible during the time it is being refreshed On the other hand the simplicity of DRAM bit cells means that we can t more bit cells on a chip thus saving cost 6 Example A Simple CPU As another illustration of how these principles can be used we will examine the design of a simple CPU Digital Logic 21 6 EXAAlPLE A SINLPLE CPU connections not shown more regs not shown ut same DCDR DCDR DCDR src src op dst br target IR memory RAM or ROM 7 PC MUX add 1 We will assume 8 registers Only one of them is shown here but the others all have the same connections as the one shown All data accessed by the program will be in the registers unlike most CPUs in which data can be either in registers or in memory The program itself is in memory Let s review some terms rst A CPU has a special register typically called a Program Counter PC which speci es the address in memory of the next instruction to be executed At the beginning of a fetch execute cycle the CPU will fetch the instruction from memory which is pointed to by the PC depositing the instruction in the Instruction Register IR There the instruction will be decoded meaning that the digital logic in the CPU will execute the instruction according to the op code and operands speci ed in the instruction In our case here the latter are speci ed in terms of which two registers will be used as sources for the instruction and which one is to be the destination Thus each of these register elds will be 3 bits wide The execution of the instructions is performed mainly by the Arithmetic and Logic Unit ALU 11The diagram does not indicate which lines are inputs and which are outputs Here is a guide Ins Left of R le and bottom of ALU left of NZ bottom ofIR right of memory le ofIR top and right of MUX right of add 1 Outs Right of ALU right ofNZ bottom of R top of DCDRs top and bottom ofIR le of MUX top ofmemory le of PC le of add 1 Digital Logic 22


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