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Digital System Fundamentals

by: Gerda Bernier

Digital System Fundamentals COMP SCI 352

Gerda Bernier
GPA 3.98

Yu Hu

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Yu Hu
Class Notes
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This 7 page Class Notes was uploaded by Gerda Bernier on Thursday September 17, 2015. The Class Notes belongs to COMP SCI 352 at University of Wisconsin - Madison taught by Yu Hu in Fall. Since its upload, it has received 56 views. For similar materials see /class/205106/comp-sci-352-university-of-wisconsin-madison in ComputerScienence at University of Wisconsin - Madison.

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Date Created: 09/17/15
University oiWisconsin Madison Overview of Chapter 7 EC Comp Sci 352 Digital Systems Fundamentals KewalK Saluja andYuHen Hu SpringZOOZ Review from Chapmr 1 Dzmpzth and Control Unit 5 1 i E Logic and Computer Design Fundamentals Chapter 7 Register Transfer Strucmres I Multiplexer basal Bus based I Three eatelms I Memory transfer I I 0th transquot Reg ter Transfers amp Datapaths pupil 39 39 ALU 39 Shifter mderrel Shifmr Originals by CharlesR Kime Dam aLhRepresentatjun and Control p I P39 l39 d D L th Modilied for course use by Kewal K Saluja and Yu Hen Hu 391 m 2 Iquot 2001 PrenticeHall Inc rage md Campqu my Mmmuk Chapter 7 2 Review 39om Chapter 1 Computer Diagram Datapath and Control Unit CP entralecessingUnil U c Performs sequences ufprucessing mred in Cu nlrul Un ll In Datapath Performs basic operation an dam stored in untrul Data Outputs inputs 39 ig ge e g fjc mg I mum signals that con gure data transfers a eratj ube performed inthe and establish operations to be performed me ff39m addmszbk I Status signals that represent the state of data repesimryier dam such as over ow 395 quotzeroquot t sm etc These d m A clleciun a signals are tested to change the sequence of evices ztstnre i a an convert informatioan y peram ns chapel 7 3 chapel 7 4 Register Transfer Operations Register Transfer e m a collection of binary storage flip W m flops organized in a logical fashion El I W5 7 The movement 15 s 7 0 15 0 and processing ofdata stored in registers I Three basic componenm 0 Letters and numbers 7 denotes a register ex R2 PC IR ses 7 denotes a range oi register bits ex I control ofoperations R11PC70ARL I Elementary Operations 7 load count shift AIWW F i denotes data mills CX RU RZ l CL add bitwise quotORquot etc R0 I Elementary operations are called micmapera nnx Comma separatesparallel operations Brackets e Speci es a memory address ex R0 MAR R3 MPC rage md Campqu my Mmmuk cmquot 7 5 tags md Compqu my Mmmuk cmquot 7 5 Conditional Transfer IfK1 1 then R2 K1 R1 is shortened to K1 R2 R1 where K1 is a control variable specifying a Clo Load 2 Microoperations LogicalGroupings I Tm star 7 move dam than one set or regismrs to another I Arithmetic 7 perform arithmetic on data in regisms I Logic W manipulam dam orusebitwise logical operations I Shiftquot shift dam in registers conditional execution condition 5mm Arithmetic operations Logical operations bitwise I Conditional execution J T v Logical OR is used to modify the I T Asduon A LogicalAND sequence of Tmnsferoccurs Here 0 63 Logical Exclusive 0R microoperations M quot1P1 caquot Not Division tagk micmpmcsmammm Chp7 7 tag mammogramth Chp7 a Example Miorooperations I Add the content of R1 to the content of R2 and place the result in R1 R1 R1 m I Multiply the content of R1 by the content of R6 and place the result in PC PC R1 R6 I Exclusive OR the content of R1 with the content of R2 and place the result in R1 Example Microoperations Continued I Take the 139s Complement of the contents of R2 and place it in the PC I PC R2 I On condition K1 QRK2 QRthe content of R1 with the content of R3 and place the result in R1 I K1K2 R1 R1vR3 I NOTE quotquot as in K1 K and means Control expression values If X 0 the X i X K1 1 activating the Logic quot1quot the operation add or R1 and R2 takes Place EX 1 then X K1 1 I Logic quot0quot the operation is activating the add or R1 inhibited and the two39s comp oI39RZ subtract in ma cam my Mmmuk Chapter 7 ll R1 R16 R2 OR In R1 R1 R3 means plus comm 9 comm in Control Expressions Arithmetic Miorooperations The 39 or Ex 1 From an operation appears to the amp 539 Table hit or the operation and is K1 R1 R1 1 R2 77 separated from it by a colon X K1 R1 R1 1 R2 1 1 39 39 C quot 1 XP SS SSP Y VariableK1enablesthe 391 or add or subtract the operation to occur perm Note that any register may be speci ed ror source 1 source 2 or destination These simple microoperations operate on the whole wordquot except ror 139s complement which is abitwise eration in ma cam my Mmmuk Chapter 7 12 Logical Miorooperations I From Table 7 Symb olic mgr md Camilqu may Mmmub Chapter 7 13 Logical Microoperations Continued I Let R1 10101010 and R2 11110000 I Then after the operation R0 becomes mgr md Camilqu may Mmmub Chapter 7 Shift Microoperations From Table 75 Symbol Dem m n LetRz 11001001 Designation R14 is2 ShirtLert ShinRi t Then arter the operation R1 becomes R1 10010010 01100 Note These shifts quotzero fillquot Sometimes a separate quotlinkquot bit can beused 0 provide the data shifted in or to quotcatchquot the data shifted out I Other shifts are possible circular arithmetic Chapter 7 l5 Register Transfer Structures MultiplexerBased Transrers Register inputs are connected to multiple sources via a multiplexer Bu ased Transrers Register inputs are connected to a single bus driven by a multiplexer reeState Bus Register inputs and outputs are connected to a single bus viatristate drivers We designing arepresentative cell ror the register Registers provide a source ror and a source or sink or 12m Was Use multiple multiplexers multiple busses combinations or all the above etc Chapter 7 MultiplexerBased Transfers Multiplexers connected to register inputs produce ilexible trans er structures Note Clocks are lert oir ror clarity K1 R0 R1 I The transfers are Figure 75a mgr md Camilqu may Mmmub Chapter 7 l7 MUX Based Transfers Continued Multiplexers connected to each register inpu produces a very ilexible ansre structure ruc re How many operations can occur in parallel mgr md Camilqu may Mmmub Chapter 7 BusBased Transfers I A single input bus driven by a multiplexer limits the available transfers M I What transfers can occur here L2 net at emquot been autumn cube 7 ThreeState Bus I The 3 input M39UX can be replaced by 3 state buffers Transfers are still limited I What transfers are allowed here Lagk md Campqu Design human Chapter 7 2n Register Cell Design need and what is it In Chapmr 7 Regimer transiers intrnduced There may be multiple transrers intu a egister gas I Dt ne cuntrnl signals that muse mch distinct transfu39 I Find an equatinn in each cnntrnl signal in terms nfinputs and AsM seate Given the ab eve we need to design the register This design is done if pussible by 39 D igling 2 represenmtive til at the gs I Cnnnenjng cupies nfthe nil tuguher tn fm m thertgistu I A plying 2pprnpriate hnunt lary cnnditjnns39 m end cells W is the first smp ul39the abuve prucess Foundations for Register Cell Design I Assuming that the register has a hold mction When n occur use a D ip op plus multiplexer register with a LOAD contro I The LOAD for the cell is the OR of all ofthe control signals under which a transfer into the register occurs I The Dinput for the cell can be designed using a Kma for a small number of transfers and a multiplexer encoder or CAFE for a large number of transfers CXBA one EOR A I Kmap method can be used to minimize the logic or it can be implemented using mux and decoder Lagk md Campqu Design human Chapter 7 Chapler7 2t Chapler7 22 Example 1 Register Cell Design Memory Transfer I Register A has the following transfers into it 39 Memory operations require I ADDRESS CX A lt B v A o And require CY A lt39 B XORA I DATA write uperatiuns I Design register cell Ai for A 0r provide I What is the LOAD input for Ai 39 Df TA Md quotPm39j mg cx CY Typically What is me Di input fmAi bemnre than unememury address suurce In a 39 There can be mure than me dam suurce ur dam sink in a stem 5y I Same strucmre of buses and multiplexers is needed to access the memory Lagk md Campqu Design human Chapter 7 24 Other Transfer Structures Fast systems require that parallel operations occur within the same clock Parallel operations imply quotresourcesquot required to move the data I SO 39 Multiple buses are used and 39 Multiplexers are used to select input sources THIS REQUIRES MORE HARDWARE Logic and Computer Design Fundamentals Chapter 7 25 r nnni Dr quotH Other Transfer Structures Continued I What transfers does this system allow Logic and Computer Design Fundamentals r 7001 Dr quotH Uull Tn Chapter 7 26 Datapath I Unit that can perform multiple functions and store results often contains functional units such as ALU shifter and register le I Example Figure 79 Logic and Computer Design Fundamentals Chapter 7 27 c 2001Prenticel lall lnc Anthmeltrjt gtc mm mm Logic and Computer c 2001 Prentice Hall lnc Chapter 7 28 ALU Shifter and Barrel Shifter I ALU 39 Can perform multiple operations such as add subtract and or EOR increment decrement transfer see table 7 8 for an example set of operations 39 Realization I MuX based gure 7 15 I Further reduction of logic possible using logic minimization methods I Shifter Barrel Shifter 39 Can be used for one or multiple bit shifts 39 MuX based realizations given in Figures 7 16 and 7 l 7 Logic and Computer Design Fundamentals Chapter 7 29 r nnni Dr quotH Nbit ALU Fig 710 4 AD Data Ar input A 39 en 4 4 A 1 Gl 4 Data output G I 30 mm 4 B arithmetic G logic Ui lll 4 en ALUH Data input B Carry mputgh in Emu gtCarry output Operation 339 act 5 I Made setettgb 32 Logic and Computer Design Fundamentals Chapter 7 30 r 7001 Dr quotH Uull Tn An Arithmetic Circuit A gtquot x n Hrblt n avaiiei gsmwwcm E 7 addel 13 input n so I logic 7 V 514 gt Cm Logic and Computer Design Fundamentals Chapter 7 31 i o i u ii I B input logic for one stage of Arithmetic Unit Inputs Output s1 50 B v 0 U 0 O YI 0 0 O 1 0 o I o 0 I B O 39l 1 1 1 0 0 1 Y E 1 o 1 o 39 39 1 I O 1 1 1 1 1 Y39 1 by Map Sii iliifhtaiion a Tmth table Y Bng E Si Logic and Computer Design Fundamentals Chapter 7 32 in t u ii I 4bit Arithmetic Unit Logic and Computer Design Fur Chapter 7 33 001Pr nil T TaH Tn 1stage of logic unit 51 51 Output Dpemllon 3 0 G A A B AND 0 1 G A V a OR 1 O G 2 A6 B XOR 1 1 G 7 NOT bi Function T211319 lay Logic Dlaglam Logic and Computer Design Fundamentals Chapter 7 34 0m Dr nti T TaH Tn 1 stage of ALU Ci C i Ai One stage 0 Bi arithmetic circuit 4 4 One stage of loglc circuit Logic and Computer Design Fundamentals Chapter 7 35 i o u ii I 4bit basic shifter A3 A2 SH ial output L 1 M S U X H2 Logic and Computer Design Fundamentals Chapter 7 36 i o i u ii I 4bit Barrel Shifter Loglc and Computer Deslgn Fundamentals r o u u r Chapter 7 Datapath Representation and Control I Datapath representation 39 See Figure 718 Table 710 I Control 39 Control signals for function unit are shownm see 39 Control variables and functions of datapath shown in Figure 719 and Table 711 Loglc and Computer Deslgn Fundamentals r o u u r Chapter 7 38 Data Path t D data 4 Wnle L D addless 2an Renteterme m m 4gt Aaddvess Baddvess lt7 A data 5 data Constant m Funmon umt Loglc and Computer Deslgn Fundamentals m Dr ntl T Tall Tn Addvess out Data out Pipelined Datapath I A method of improving performance I Tradeoff between latency and throughput 39 Increases clock frequency 39 Many clock cycles to complete thejob Loglc and Computer Deslgn Fundamentals m Dr ntl T Tall T Chapter 7 40


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