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# Digital Logic Design CSE 2300

Americo Huel
UCONN
GPA 3.73

Zhijie Shi

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COURSE
PROF.
Zhijie Shi
TYPE
Class Notes
PAGES
66
WORDS
KARMA
25 ?

## Popular in Engineering Computer Science

This 66 page Class Notes was uploaded by Americo Huel on Thursday September 17, 2015. The Class Notes belongs to CSE 2300 at University of Connecticut taught by Zhijie Shi in Fall. Since its upload, it has received 63 views. For similar materials see /class/205923/cse-2300-university-of-connecticut in Engineering Computer Science at University of Connecticut.

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Date Created: 09/17/15
Sequential Circuits Latches and FlipFlops 939 UC NN Z Jerry Shi Computer Science and Engineering University of Connecticut Thank John Wakerly for providing his slides and gures Sequential circuits Output depends on current input and past history of inputs The circuits can remember past inputs Memory to remember state between two inputs How can you tell an input combination is current or past Clock signals Very important with most sequential circuits State variables hange state N dge tHtL CLK state changes occur here period tper CLKL I state changes occur t I tH per frequency 1 tper duty cycle 2 tH tper here iF duty cycle 2 tL tper State and state variable The memory of the circuits is nite Most applications do not need long histJ A circuit is built with limited resources They cannot remember all past inputs The number of past input patterns are nite Each possible history can be characterized as a state State embodies all the informatioii about the past needed to predict current output based on current input State can be represented with bits State variables one or more bits of information Bistable element The simplest sequential circuit TWO states One state variable say Q V outl HIGH vim LOW Q Bistable element The simplest sequential circuit TWO states One state variable say Q V outl Vinl HIGH Q Analog analysis Assume pure CMOS thresholds 5 V rail Theoretical threshold center is 25 V VOUT HIGH 35 undefined 1 5 50 LOW undefined HIGH Analog analysis Assume pure CMOS thresholds 5V rail Theoretical threshold center is 25 V 25V V inl 25 V Analog analysis Assume pure CMOS thresholds 5V rail Theoretical threshold center is 25 V Your 50 HIGH 35 undefined 0 15 35 50 LOW undefined HIGH 00V 50V Metastable state Metastability Metastability is inherent in any bistable circuit V stable outl V Transfer function Voutl TVinl V0ut2 TVin2 i112 metastable stable metastable Vnl V 1 ouIZ 0 Two stable points one metastable point stable stable Control bistable How to control it Control inputs S and R SR latch R S R 0 GM 0 O u 0 0 last Cl Mast ON I 1 l 71 1 11 1 11 S ON 1 1 0 11 S R latch operation s R O Metastability is possible if S and R are negated 0 simultaneously S R latch timing parameters 39 Propagation delay 39 Minimum pulse Width 7 pwso lpHLgpo SR latch symbols S R latch using NAND gates SL or Q 0 S Q O R O RL QN or SL RL Q ON 0 0 1 1 0 1 1 O 1 0 0 1 1 1 lastQ last QN S R latch with enable S R c Q QN Let C decide Whether S and R can 0 0 1 last Q last QN reach the bistable circuit 0 1 1 1 0 1 1 O 1 1 1 1 1 x x 0 last Q last ON 5 o C D 1 O 1 1 0 x Q ON 0 1 1 0 last 0 last QN Dlatch operation WhenC1 QD When C O Q does not change Dlatch timing parameters WhenC 1 Q follows D 7 Pro avation dela from C or D When C 0 Q remembers D s value at the 1 90 transition 7 Setup time D before C s falling edge 7 Hold time D after C s falling edge Positive edgetriggered D ip op CLK CLKiL Latch l QM Latch 2 Q Status Status 1 0 Disabled me T Enabled QMme T i T me T me T 0 l Enabled N D Disabled me T T i D me T l 0 Disabled TD T Enabled QM D T Positive edgetriggered D ip op behavior 0 lastQ lastQN 1 lastQ IaSIQN D ip op timing parameters Propagation delay from CLK 0 Setup time D before CLK 0 Hold time D after CLK D r CLK K x 0 SWquot HT Moo pHHCO CMOS positive edgetriggered D ip op 0 Two feedback loops master and slave latches 0 Uses transmission gates in feedback loops TA Positive edgetriggered D ip op with preset and clear Preset and clear inputs a Like S R latch 43 PR D Q CLK gt CLR Q0 PRL CLRL TTL positive edge triggered D commercial circuit x74 Preset and clear inputs PM 723 3 feedback loops 7 interesting CLR L analysis Sec 79 7 Light loading on D W i LR J ON Negative edgetrigged D ip op Invert the input CLK signal 0 C 0 0 D QN CLKL n i Ogt 7 D CLKL Q QN O 1 0 1 1 1 1 O D Q x 0 last 0 last QN OgtCLK Q 0 x 1 lastQ lastQN b C Positiveedgetriggered D ip op with enable O x How does EN works EN CLK Q QN D Q 1 0 1 I EN 1 I 1 0 CLK Q o O I lastQ lastQN x 0 lastQ lastQN x 1 lastQ lastQN Scan ip op HOW is this circuit different from the previous one TE TI D CLK Q QN 0 x o I o 1 D o x 1 I 1 0 TE Q 1 o x I 0 1 n 1 1 x I 1 o M Q x x x 0 IastQ IastQN x x x 1 lastQ lastQN Scan ip ops for testing As to external pins 0 TE 0 9 normal operation 0 TE l 9 test operation 7 All of the ip ops are hooked together in a daisy chain from external test input TI 7 Load u scan in a test 7 attern do one normal of eration shift out scan out result on T0 Edge Triggered J K ip op Not used much anymore Don t worry J K CLK 0 ON about them x x o Iast IasmN x x 1 Kale lasION J O 0 o I Iasm lastON CLK D 1 K C Q 1 o 1 1 I v I rest ON last 0 Masterslave JK ip op pulse triggered 0 last Q last QN J X X IQ 0 0 E 151510 lastQN Q o 1 0 1 1 0 IL 1 o 1 1 last QN lastQ Timing diagram of masterslave J K ip op Ignored Ignored Ignored Ignored Ignored since 0 is 0 since OM is 0 Since G is now 0 since Q is 0 since QN is 0 Masterslave SR ip op QN S R C Q 0 IastQ astQN J L lastQ astQN IL 0 1 IL 1 0 IL undef undef A Aoogtlt IQ T ip ops T ip ops with enable Impo ant for counters Many types of latches and ip ops SR latch SLRL latch SR latch with enable D latch Edgetriggered D ip op Edgetriggered D ip op With enable Edgetriggered D ip op With preset and clear Scan ip op Edgetriggered JK ip op Masterslave SR ip op Master slave J K ip op T ip op T ip op with nable Switching Algebra and Logic Representations UC NN Z Jerry Shi Department of Computer Science and Engineering University of Connecticut CSE2300WDigital Logic Design Boolean algebra English mathematician George Boole invented a twovalue algebraic system Boolean Algebra A proposition can have one of the two values TURE or FALSE Claude E Shannon uses it to describe the behavior of circuits Switching Algebra A variable can take one of the two values 1 or 0 Positivelogic convention Analog voltages LOW HIGH 9 O l N egat1ve log1c Signal values denoted by variables X Y FRED etc Axioms A1XOifX1 Al X1ifXO A2IfX0thenX 1 A2 IfX1thenX O A30000 A339111 A41011 A4 OOO A50011000 A5 iuui1 Principle of Duality Any theorem or identity in switching algebra remains true if 0 and 1 are swapped and o and are swapped throughout Boolean operators Complement X39 opposite of X AND X Y D 39bdf t39 11 escrl e unc lona y OR39 X Y by truth table H AND 1 r39 X CIR Y X NOT X 0 7 L 4 5 ags dgd quot El 5 LED LQLQ LL More de nitions Literal a variable or its complement X X39 FRED CSL Expression literals combined by AND OR parentheses complementation XY P Q R A B C FRED z39 CSL A B C Q5 RESET39 Equation Variable expression P FRED z CSL A B C 5 RESET39 Assignment Assign a speci c value to each variable Logic symbols T Gates 0 Gates are basic digital devices 0 A gate takes one or more inputs and produces an output Can be considered as a function Inputs are either 0 or 1 Although they may have very different values of voltage Example of basic building blocks AND OR NOT X Y XANDY XORY X NOTX X Y XY X39 X Y XANDY x Y XORY X NOTX o 0 o o o o o 1 o 1 o o 1 1 1 0 1 o o 1 0 1 1 1 1 1 1 1 NAND and NOR Y X NAND Y Y X NOR Y X Y X Y X Y X NAND Y X Y X NOR Y 0 0 1 0 0 1 o 1 1 o 1 o 1 o 1 1 o 0 1 1 o 1 1 o Truth Table XOR gates Like an OR gate but excludes the case Where both inputs are 1 XNOR complement of XOR xce Y X Y Y XOR XNOR jDi XOR 0 0 1 1 1 0 0 1 0 D XNOR 1 0 1 h Ioox Theorem s Tl x 0 x Tl x 1 x Identities T2 X 1 1 T2 O 0 Null elements T3 X X X T3 X X X Idempotency T4 X X Involution T5 X X 1 T5 X X 0 Complements gtlt Proofs by perfect induction Example In TLXhas two valueSO or 1 leV Vv V0X IfX1X0101X More Theorems T6 X YY X Tb X YY X Commutativity T7 X Y Z X Y Z T739 X Y Z X Y Z Associativity T8 XYXZXYZ TS39 XYXZXYZ Distributivity T9 XX YX T9 X XYX Covering T10 X Y x Y X T10 x Y x Y x Combining Tll XYX39ZYZXYX Z Consensus Tll XYX39ZYZXYX39Z Duality Swap0amp lANDampOR Result Theorems still true Why Each axiom AlA5 has a dual Al A539 Counterexample X X Y X T9 XA r Xdual X Y X T339 99999999 XXYXT9 X X Y X dual XXXYXT8 X I KA39Y XT339 parentheses operator precedence NVariable Theorems T12 X X X X Generalized idempotency TIZ x xx T13 X1 39 X2 X 2 X139 X2 Xn DeMorgan s theorems T1339 x1X2Xn X139X239 Xn39 Tll FX1X2 Xn FX139X2 Xn Generalized DeMorgan s theorem T15 FX1X2 Xn X F1X2 Xn X FOX2 Xn Shannon s expansion theorems T153 FX1X2 XnX1FOX2Xn Xl F1X2 xnn Prove using finite induction Most important DeMorgan theorems Change the gate types and locations of inverters DeMorgan Symbol Equivalence X xv X r Y gt072XY YD0727XY X x Y ZX Y X3gt72gtlt39Y V Likewise for OR x xw x 7 Y zgtltv YDi 270mm x x x Y zzxw vagtizxv v be sure to check errata DeMorgan Symbols D on 2 D 2 3 33w D XOR XEDYXY39X39Y X XO X Xe1 X OX X 1X39 X mzX w Z X Y YX Q YYW YX Y39 X Y DH C Y Z IfX 1 ZthenX 1 u Examples XXY o LI L39Y A39B39C39AB39C39AB39C X YY X YY39 X YY 15X YLxZ YZ Dual of a logic expression Let F be a fully parenthesized logic expression FX1 X2 X3 X11 The dual to F written FD is the same expression with AND and OR swapped FDX1 X2 X3 Xn 9 X2 X3 9 X113 399 DeMorgan s theorem T14 X2 X3 9 FX19 X28 X39 39 39 399 Xn9 9 FDX1 Xz X3 Xn39 Type 1 gate LOW HIGH LOW HIGH LOW LOW HIGH HIGH HIGH X X ZXY Y X Y Z X Y Z 0 o o 1 1 1 o 1 0 1 o 1 1 0 0 o 1 1 1 1 1 0 0 0 Type 2 gate LOW LOW LOW LOW HIGH HIGH HIGH LOW HIGH HIGH HIGH HIGH X Z X Y X Y ZXY Y X Y z x Y z 1 1 1 g 1 1 1 o o 1 o 1 o 1 o 1 1 1 o 0 0 A circuit with positivelogic convention Copylight 2000 by Plenuce Hall m Digwta Desigu Plinmpxes and Frac ces 35 FX1 X2 X3 Xn The same circuit with negativelogic convention FDX1 x32 xn39 I type 1 Copyright E 2000 by Premlce Hall lnc Digital Design Principles and Practices 3le FDX139 Xz39 X339 Xn39 39 FX1 X2 X3 Xn More de nitions Product term A single literal or a product of two or more literals AABABC39 Sumofproducts A logic sum of product terms ABC39 C DE Sum term A single literal or a logical sum or two or more literals A B Productofsums A logic product of sum terms ABCDE Normal term A product or sum term in which no variable appears 1110f than 01106 o X Y Z X Y Z If a term is not normal it can be reduced to a constant or a normal term Minterm and maxterm An nVariable minterm a normal product term with n variables Only one assignment makes a minterm l An nVariable maxterm a normal sum term with 72 variables Only one assignment makes a maxterm 0 Consider an nvariable function how many minterms and maxterms Truth table minterms and maxterms Row X Y Z F Minterm Maxterm 0 0 0 0 F000 X Y Z XYZ 1 0 0 1 F001 X Y Z XYZ 2 0 1 0 F010 X vY Z XY Z 3 0 1 1 F011 X Y Z XY Z 4 1 0 0 F100 X Y Z X YZ 5 1 0 1 F101 X Y Z X YZ 6 1 1 0 F1l0 X Y Z X Y Z 7 1 1 1 F111 X Y Z X Y Z More Canonical sum A sum of the minterms corresponding to truthtable rows for which the function produces a l ouptut Onset for the logic functions Canonical product A product of the rnaxterrns corresponding to truthtable rows for which the function produces a 0 ouptut Offset for the logic functions Example XYZ F Minterm O X39 0 Y39 0 Z39 1 Minterm 3 X39 0 Y 0 Z 001 O Minterm 4 X 0 Y39 0 Z39 010 0 Minterm6zXoYoZ39 011 1 Minterm7XoYoZ 100 1 M t 1 XYZ39 axerm 101 O Maxterm2XY39Z 110 1 Maxterrn5X39YZ39 111 1 F ZX W z 0 3 4 6 7 X39OY39OZ39X 0YOZXOY OZ39 XOYOZ39XOYOZ F Hxyz 1 2 5 X Y Z39oX Y39ZoX39 Y Z39 Another example Find all the minterms and maxterms for the following function XY39Z XYYZ A logic function can be represented with Truth table Canonical product Canonical sum Minterm list with 2 Maxterm list with H

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