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by: Brandon Douglas


Brandon Douglas
GPA 3.75


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Class Notes
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This 2 page Class Notes was uploaded by Brandon Douglas on Friday September 18, 2015. The Class Notes belongs to EEL 4712 at University of Florida taught by Staff in Fall. Since its upload, it has received 6 views. For similar materials see /class/206843/eel-4712-university-of-florida in Electrical Engineering at University of Florida.

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Date Created: 09/18/15
7 Sample Models The DP32 Processor This chapter contains an extended example a description of a hypothetical processor called the DPBZ The processor instruction set and bus architectures are first described and then a behavioural description is given A test bench model is constructed and the model checked with a small test program Next the processor is decomposed into components at the register transfer level A number of components are described and a structural description of the processor is constructed using these components The same test bench is used but this time with the structural architecture 7 1 Instruction Set Architecture The DP32 is a 32bit processor with a simple instruction set It has a number of registers shown in Figure 771 There are 256 general purpose registers R07R255 a program counter PC and a condition code register CC The general purpose registers are addressable by software whereas the PC and CC registers are not On reset the PC is initialised to zero and all other registers are undefined By convention R0 is readeonly and contains zero This is not enforced by hardware and the zero value must be loaded by software after reset The memory accessible to the DP32 consists of 327bit words addressed by a 32bit wordeaddress Instructions are all multiples of 327bit words and are stored in this memory The PC register contains the address of the next instruction to be executed After each instruction word is fetched the PC is incremented by one to point to the next word The three CC register bits are updated after each arithmetic or logical instruction The Z zero bit is set if the result is zero The N negative bit is set if the result of an arithmetic instruction is negative and is undefined after logical instructions The Voverflow bit is set if the result of an arithmetic instruction exceeds the bounds of representable integers and is R0 PC 31 39 0 cc R255 Figure 77 DP32 registers 771


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