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This 111 page Class Notes was uploaded by Ms. Rosamond Fritsch on Saturday September 19, 2015. The Class Notes belongs to CPEG422 at University of Delaware taught by Staff in Fall. Since its upload, it has received 29 views. For similar materials see /class/207108/cpeg422-university-of-delaware in Computer Engineering at University of Delaware.
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Date Created: 09/19/15
The Hardware Reading XSA 5O Manual D892LV16 Data Sheet D892LV16 Design Guide LVDS Owner s Manual XSA50 Prototyping Board Valage RagaMm 1w MHz Flag agarm Voltage cl 45V 3 3V XSA 5O Prototyping Board PC Parallel Pod J8 External 7 Cl Clock Input JE my 100 MHz Osc K EJE IISE QVDC Power Supply 0 1 33V Pushbutton 7 GND CPLD Flash RAM 7 5V 7 Spartanll FPGA SDRAM 7 Pushbutton 25V PSZ Mouse VGA Monitor or Keyboard XSA 50 Prototyping Board XILINX XC285O FPGA 7 m l 7 XXILINXE SPARTAN E Device Type XCZSSDTM Date Code Package La PQZOBAFPOOZS 7 A1134280A LoI Code Speed r SC 1 r J q H I u x r r 1 Sample package with parl marking for XCZSSOGPQZOEC FPGA used on XSA 5O Proto Board 25K 50K Programmable Logic Gates 208 Pin Package 140 User Definable O Pins Logic Synthesis Design Flow FPGA Synthesis Timing Analysis FPGA SignOff In CPEG422 you will write and synthesize VHDL programs for XSASO proto boards Programming XSA 5O x 9mm E Ema m m mu v Laad Full LPN M on Fgwmg deb l ssgaaalm39lx lv El ExesscavaRDDUTSgtltSABRDBlTSTREAMSlmp wagm RAM FlashlEEPRDM Emma 1 nheclsl sauna g Mthum j d Lawmales LlplaadFavmal HEX v El HEX v E Powerthe board connect parallel cable to PC run GSXLOAD utility to load BIT file on FPGA Gigabit DaughterBoard The UDEL GDB Physical View The daughterboard implements a gigabit serial interface using D892LV16 LVDS SERiaIizer DESeriaIizer SERDES chip from National Semiconductor The external lO for the daughterboard consists of4 SMA connectors implementing one differential gigabit LVDS input port and one differential gigabit LVDS output port Using this daughterboard together four SMA cables enables one to implement a bidirectional gigabit link between two XSA50 boards D892LV16 And Bypass Components 39 xs Board J Sockets Diagnostic LED Display 4 SMA Connectors Implement Bidirectional Gigabit Serial Link The UDEL GDB Functional View Transmitter Receiver E DSQZLV16 II E DSQZLV16 II E I E I E I E I TTL E l E TTL E Serializer 3 1 gt E Deserializer 3 16 E II Single E I 16 Channels E 3 Differential E 3 Channels 332133 a c maxim E I E I LVDSVDD Pin Mapping ltPNMAPUCFgt File NET datalt3gt LOC P49 NET datalt2gt LOC P48 NET datalt1gt LOC P47 SPART a NET datalt0gt LOC P46 XCZSSO NET SEGSlt6gt LOC P90 A1134280A NET SEGSlt5gt LOC P91 NET SEGSlt4gt LOC P92 NET SEGSlt3gt LOC P93 NET SEGSlt2gt LOC P94 NET SEGSlt1gt LOC P95 NET SEGSltDgt LOC P96 Pin Mapping Clock Generator IC File my designvhd File my designucf entity mydesign is port Pinquot Map to gig abit d augh terb oard Clkin in stdogic NET quotclkinquot LO C quotP88quot 1 end mydesign Comment This input pin provides your design with a 25MHz clock that you can use to clock your design It is generated by a programmable oscillator chip on the XSA50 board Pin Mapping LED Display 80 82 83 86 S5 SO 34 S4 S1 S l m0 6 r l t File my designvhd 5 fl hp ILJ E JD WLQB ILA Y entity mydesign is port LEDS out stdogicvector6 downto 0 LEDDP out stdlogic t 2quot end mydesign maid 9 quot460 NET quot TLl liDL l w fl Pin Mapping User Input Fi y designv enmy myideswgn 5 pon xsporLd m stdjogwcivector end myideswgn 6 downto 0 Pin Mapping Gigabit Daughter File my designucf SerDes Chip Control Signals NET quotrpwdnquot LOC quotP83quot NET quottpwdnquot LOC quotP27quot NET quotrelquot LOC quotP85quot NET quottclkquot LOC quotP86quot NET quotrclkquot LOC quotP18quot NET quotlockquot LOC quotP20quot File my designvhd entity mydesign is port din out stdogicvector5 downto 0 rout in stdogicvector5 downto 0 rpwdn out stdogic SerDes Chip Inputs FPGA outputs NET quotdinlt0gtquot LOC quotP12quot NET quotdinlt1gtquot LOC quotP13quot ref out stdogic NET quotdinlt2gtquot LOC quotP21quot tclk out stdogic NET quotdinlt3gtquot Loo quotP22quot rclk in stdogic NET quotdinlt4gtquot LOC quotP38quot lock out stdogic NET quotdinlt5gtquot LOC quotP28quot end mydesign SerDes Chip Outputs FPGA inputs NET routlt0gtquot LOCquotP41quot NET routlt1gtquot LOCquotP59quot NET routlt2gtquot LOCquotP74quot NET routlt3gtquot LOCquotP75quot NET routlt4gtquot LOCquotP66quot NET routlt5gtquot LOCquotP79quot I um I 3r1EditiuISprIng2UDA V 39l LVDS Receiver Low Voltage Differential Signaling Open standard for gigabit signaling Two wires transmit signal positive and negative Current mode signal transmitter Voltage mode receiver Transmission line wiring multiple bits in ight Controlled impedance traces and termination resistors LVDerza LVDS Circuits Driver Receiver Lvnsnm Figure 11 Simpli ed diagram 01 LVDS Driver and receiver connected via 1009 differential impedance media LVDS Standard AN 51 TIAEIA 644VA LVDS standard Table 11 ANSI39l39lAElAE44 LVDS standards Parameter Max Units VOD Differential output voltage 454 mV V05 Offset Voltage 1125 1375 V VOD ICliange to VODI 50 ImVI V05 IChange to V03 50 ImVI 15A 153 Short Circuit current 24 ImAI trtf Output rise 111 times 200 Nibps 026 15 ns Output risefall times ltZOO 1V1bps 026 30 riftuiT ns 1IN Input current 20 IpAI VTH Receive threshold voltage 100 mV VIN Input Voltage range 0 24 V LVDS Applications 15 LVDS applications The liiglyspeed and low powernoiseCosr benefirs ofLVDS make it a compelling technology rim ts into 1 broad range or ippliwionsi Some examples are listed in Table 142 PCcomputing Table 12 Sample applications Telecnmldatacnm Consumercommercial Fla 3 nel displnzs es Homecommer 1 video links lVloniror link SCI processor interconnect Primer engine links Diwital Copiers System clustering lVlultimedia peripheral links Adddrup mulriplexers Set top boxes Hubs ln i ht Routers Game quot 39 39 Access systems Brondband Base stations LVDS vs Others Table 21 Comparison 01 LVDS with IS422 and PEEL Parameter RS 422 PECL LVDS Differential driver output voltage 2 to 5V 600 to 1000 mV 230 450 mV Receiver input threshold 1200 mV 1200 to 300 mV 100 mV Data rate lt50 l llps gt400 Mbps gt400 Mbps Parameter RS422 PECL LVDS Suppr current quad driver no load static 60 mA max 32 to 65 mA max 80 mA Suppr current quad receiver no load static Propagation delay of driver Propa ation delav of receiver Pulse skew driver or receiver 39LV39DS device noted are DSOOLV047A048A 23 mA max 11 ns max 30 115 max NA 40 mA max 45 ns max 70 ns max 500 ps max 15 111A max 17 ns max 27 ns max 400 5 max LVDS Speed vs Distance 2000 SCANBOCPDZ 1000 1600 1400 1200 Highend 1000 000 Data rate Mbps 600 Midrange FPGA LVDS 400 200 Lvnslms 0 5 10 15 CAT5 cable length m VH DL Simulation to Synthesis Chapter 1 Introduction Traditional vs Hardware Description Languages Procedural programming languages provide the how or recipes 7 for computation 7 for data manipulation 7 for execution 011 a speci c hardware model Hardware description languages describe a system 7 many different facets 7 behavior 7 structure 7 functional properties 7 physical properries Why do we Describe Systems Design Specification unambiguous de nition of components and interfaces in a iarge esign Design Simulation verify systemsubsystemchip performance prior to design impiementation Design Synthesis automated generation of a hardware design A Synthesis Design Flow Requitements vym Made Functional Design VHDL Made Register Transfer Level Basin 9quot WWW Behavioral Simulation V wot Automation of design refinement steps Feedback for accurate simulation Example targets ASICs FPGAS The VHDL Language V Very High Speed Integrated Circuit H Hardware D Description L Language Interoperability between design tools standardized portable model of electronic systems Technology independent description Reuse of components described in VHDL History of VH DL 39 Designed by IBM Texas Instruments and Intermetrics as part of the DoD funded VHSIC program Standardized by the IEEE in 1987 IEEE 10761987 Enhanced version of the language defined in 1993 IEEE 10761993 Additional standardized packages provide definitions of data types and expressions of timing data IEEE 1164 data types IEEE 10763 numeric lEEE 10784 timing Describing Systems microphone 39 Hiieadphoues ampli er 0 e Processor speakers System An assemblage of objects united by some form or regular interaction or dependence What aspects of a digital system do we want to describe interface function behavioral and structural Attributes of Digital Systems A Event 5 10 15 20 25 30 35 4O Timems Digital systems are about signals and their values Events propagation delays concurrency Time ordered sequence of events produces a waveform Attributes of Digital Systems Timing R g igg emu D Q l O i 71k mi 15 2 25 Tune L15 Timing computation of events takes place at specific points in time Need to wait for an event in this case the clock Timing is an attribute of both synchronous and asynchronous systems Attributes of Digital Systems Signal Values We associate logical values with the state of a signal 47 L possible signal values Signal Values Modeling Digital Systems We seek to describe attributes of digital systems common to multiple levels of abstraction events propagation delays concurrency waveforms and timing signal values shared signals Hardware description languages must provide constructs for naturally describing these attributes of a specific design simulators use such descriptions for mimicing the physical system synthesis compilers use such descriptions for synthesizing manufacturable hardware specifications Execution Models for VHDL Programs Two classes of execution models govern the application ofVHDL programs Simulation discrete event simulation understanding is invaluable in debugging programs Synthesis inference of hardware a function of the building blocks used for implementation D39xm x re 6 MW 5m yamu gs Sgn u V f4 8 C W M i A 02 quot03mg 1 42 6 62mm EES 15 2550 0 smlmz WWW25 Dgsc x mOxS kg awE gc gmgr39zc WPWSmwnj DES Mu arm9 yw w xTE 30 062513 VHdz wb Wang zaJ Ams Skmdhmow39 Tum Ado EdaUT QUEUEKOZ LL39 CM Ngw VgLvLVquot A 5amp3 0 DSM W E 6mm SthJE WON EX chLf W H jgtv E 1 AJLf HR Us 9862 419 a f manif 5gmuA 9w AJZZTZi awnrig 0 9 my 1 ww am motVar we 749 Owsw 2d 30 0 THEE 356 sz 51w WWW 75 amp OnS suwla w mg 13pr Us SEwpr a v 414 NFLT Sl N LS E TE AA Jam1 4 018 39 1 QM INPUT 551 s A107 quotbgthNI ET 909 H245 zW 126 Mn529 Jp ol t O C s U A lt25 n W v f w QM 5 um 0 32 4 Ifquot m w I 2 0 I a 9 Sq Fi I 5 3045 522 90 071 A fawnI kg 9 1 a 4 rim75 My quot 39 av ngow 7amp03 uST Sy 5amp5 047 gang fm ms ouTynVES NTL xxx927 ngf Lj I D0 MOTquot L AJE Na nOQE gl mg 25 4M EVEW LIST 3 rm7 v J WE r g a AA 77K AA 3351 pf mS 39 W M zm wazw 55wa MITL g n page 830539ng 15 ai Thmz 0amp5 w z a W y fw mf l y Aquot 9w 4QAT 5m z Oz wa 754 stczexe Quay Slmv TUZ 9866 749455 dig at W rm LANEE oceans 8 52 5N3 z 1 Ev I39D 510 50 77mg QW be LZA M 5 o fA and M Ifquot W gt WW 9879 8 go m 5N5 w m B j vaE 5215 3 HW YI BM Dela s e V6732 os fv a m a YUVH Efg 9 Wig 4 3 Magma A4 9955 OMS a 5M5A b 5ms2b C 55053920u I mfM Q 315 Zia 3Qb 2Wquot H mm 79 quotquot1331 gt bw 7 9153212 3174 WM C 63 9A 5N5 ga 39 1M m quotquot quot amoa m FEI I460 9 fc9v2a 5mg 2A EL 2 mm C7 21 E g LE g W V64W Am 5L few Q 5 4M0 35m L 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dzMCE SzmdQTpu mo e ZMW39 w 5mH1L6 57 7 me 57mg w 7le amt 0a 5732 EXECUTE ALL EWA TS 47 was mg 5799 i UFOFT Sgn c auag 5711223 EXWW E SMwM39xou weakg 4w FOVW TS g3 94763 621 my 9g New 95mm U u ltF o x W 64424062 A furl 6 gum7L5 wf W Q gumE Ls 52729 EXECWTE prcrm dampoMEMr p 91 5 L6 W H r 5 4 Cam00mer maQEa 9 17 cos aw WW M 50 000 5w 4 CadE eaW 1M 4 a a w 9f tsp e omouayfg UV ZUSSU JU We 6555 TAES W T 0SKg I m aram Hallow9236 WWW4M Maoach 0e 4 quotCquot F o m um 4 CrAALMQCE 92 AcKAv Norma EX1 Um ED NQTL1 VQ Q C QT09 0g 4 MX 0F Luszpma39 9 ogg W1 500E r wajram owca r g ME Commw PrU hat32 a A39 M0 LS agW491 grip M AVL ACd g d l f VKQKLE SWTHESB m s QVTOmaTED W OCQSL NFezwce or mam5 FAQw VHDL COMpQMNTquot MODEL 5 mg j 0 Wm 72gt Six ew ygf 6045 Tg m j WM 3 T Cdow 6 l W W mmme USEW OFTM725 am speap p Wiw 92 ALPEa op mw fagqu 00 Dagnyg ooAS d d 749 CM 714M 00779127quot 5 DA EXAMPLE TQCHNow tg g VU 0 MMMAV 481ng AMAD EFF Mrclx W In Du28E we 04 USE XILAX Ted ugmg 14a spawn r2 A5 pd 0 gtltS v o 60 S3W TA SrS Em VHS m GEM A A g mc wgtg C 1mm 00g 714740016 6 60 IF sag0 TMA E x44 5 g 45 L519 39 f 4cs CD C i7 pa4 55p REHLU 0mpLgr II fpg COPE FQQ L M w 69 00 awe sawealjil 2 N XT L Q Svmm sis S WWsz DZWEM YOU DoM T OMTQOL GATES peooucg 6U You 00 COAT Zou WHENWHERE mama sLS ME a earrap He CE THE Mm synTH 5133 WMMUQ CooMg e gAflaesis 3 N07quot 263a LA VZO nmw IQQUST a LoJquot WNWb3 I 140 7 C EuS D g gVD Hquot 4 IF A 70 ea c W3 5 Q Q WWW7 lg I Elmae e39U 0 g n my W A39aMyg 29 C j 8M1 76 f 9155 Simulation vs Synthesis emit myckt is 1011X y in bil 39 In I and mm architecm myc is begin W mine code here yckL re behavioral a and archilecnue behavioral unity myckt is pol X y in bii z am hi and emil myclltt u39cllhel mre behavioral myc is 2qu W some code m 4 and architecture behavioral synfllesis A i L l i 4quot j l 4 a l l L r I MINIMUM017 Simulation and synthesis are complementary processes Synthesis and Hardware Inference HDL Description Both processes can produce very different results Summary Simulation Model discrete event execution model for VHDL programs accuracy vs time Synthesis Model need for inference from language constructs basic principles behind the use of FPGAs challenges in the design flow ICFCQLZZ Lac39t lk Q VHDL IS EXTMMeLg COMPLEX 9 VHO Is 1250 7 22 Mama 4 0 JELL4M9ML26 We quot9003 pp H w 1692quot N O VHQL e M mm 1256 femur5 7 79 That Lq pjLM LH 12401 lt r OnC LHIT Calh a al bl Table 11 Trmh mblc of n 1bi equality comparator input outpul 13901 1391 00 1 01 o 10 0 11 1 m nrchiltclure sap arch of V HOL Mo 0v L9 library iaea entityis pnrti in ii in Btdlogic J and sql 1 ng MUz 8 4c 4gt J m gdngzTaeg 1 N TQzz L Jr937 llll 4 D 0 1r1L5 out stdalogic m eq A Isp rl r 7x tampf uk i signal no pl stdlogic my I Ml sun 0f nu pradur terms 6 e N aq lt p0 or pi C n 39 a pruducr lermn 7 7 7 7 g g p0 4 nal 10 and nut 11 OJ quot p1 and aaparch 3 10 and 11 4L VHUL Dam T1055 0M3 shLlobcL M Wm Ame 39 X sz Qu eeFm m pml a SMJo JUf 850K Jo KL tMu 63 0 Zogio 039 IV 603 quot239 u sk mpcd nLZ UNMWWLM M C gt afed lnKIO39WL H39 L MOT mad he cm 5quot s mw39m 039 ll Two H LOhM l oe ST quot71104 Iihrnry ieea u c ieeestd1og1cus4 nll enllly eq2 3 par a b in aeqb oul L105 and up mnrcllilcuure ol39 5 signal p0plp2p3 Lnng he in 7 mm 2 muluu rum aeqb lt p0 or pl or 112 or 91 a s s E p0 ltx mm 31 mud nol b1 nml altD nnd not b0 1 and no hl and no and 50 p2 ltn 31 and b1 and mm a0 Ind not bum p3 lt 31 und b1anda0und b0 end soparch 1 1 A I 3 on n HHHH IHIIHH TWOSW LomPAM39me 3104 M67104 archileclure r Is nl ea 91 5d1agic re 7 W inxlanliuu Inlrl bl39l unmpurumrx eqbuounjc enlily uotkeq1soparch porl mapltMa0 WU 90 a and I my equul i individual bila are aqua aaqb lt 0 and al and strucarch 11 um I a J EL 739 D quotl quotHn I y I F1 A h I tar y l I 17 bl i quot n39 l V dudV l MLquot LA M a quot u 4 n Test b ench me Wlklpedla me free encyclopedia Reduected from Testbeuch A test bench is a 39itla1 em imnmem used to ven39fy me correctness or soundness of Samm Texlingpmar a design m model eg a sofmare pmduct T V 39 39 39 would sit a a n u u in v n 11 soldenng irons we cutters and so on and manually unify the conecmess of he device under cur 39 39 39 r 39 Onen L 39 ch slur of Iesnug c5015 15 duigned xlwci cally for the produn under m A m bank 0 Wing mkbcnclu has foul cmnponems LIXPUT The nu ance c relm o lalivexablts needed to ptlfonn 39oxk 291m CEDURES T0 Dom msks m pmcesses um in Il39ausfom the input mto he ampm 3R0CEDITRES T0 FH FIquot 1 39 JOY 1quot 39 39 in nu V HDL Te STBMCH Ilbrnry 1929 gt 801m use jean std1ngic1164 nll bench entity aq2tastbanch IS and eq2cestbench is Etdlngicvectorl downm 0 re cbaxch of aq2tast testin1 scdlogic archllcclu si tsst1n0 signal te tout begin inxlunn ulp hr rirrui under IE5 uut enlily vark eq2scrucarch por mnpagtcsstiu0 hgttestin1 aaqbgtlestout gcnarulnr VH DL Tesr eALH Lani Magi all I end barch Lestin0 lt quot10quot tesLinl lt quot01quot W 39 process More about hardware Reading XSA 5O Manual D892LV16 Data Sheet D892LV16 Design Guide LVDS Owner s Manual LVDS Eye Patterns Unit interval tui Von 100 reference Optimum receiver threshold level for minimum iitler i 1 mm VOL 0 reference I k Wurstcase jitter tms Tllreslmltlcrussmg jmer Peaktupe ak jitter tms tui 100 mum Figure 72 NR2 data eye pattern Figure 72 describes the measurement locations for minimum jirter Peaktopeak jitter is the width of the signal crossing the op ritual receiver thresholds For a diner5mm receiver rim would correspond to 0v differential However the receiver is speci ed to switch between gt100 mV and 100 mV Therefore for a worse case jitter measurement a box should be drawn between 100 mV and the jitter measured between the rst and last crossing at 1100 mV If the vertical axis units in Figure 72 were 100 mVdiv the worse case jitter is at 1100 HIV levels Forminq Eve Patterns Constant quotonequot hits Constant quotzeroquot hits Isolated 01 transition Isolated 1 transition Isolated 010 Isolated 101 Superposition ol ahove signals V H 5 A g 1111111 H unit 1 uInt interval interval Figure 71 Formation ol an eye pattern by superposition Binary eye patterns LVDSJJW Example Eye Patterns BAD GOOD D892LV16 SERDES Bus Lvns Sernes Arch eenne 7 page a BusTnpnlngies 7 page 4 Backplanss 7 page 5 PCB Rennlmnendalinns 7 pay 6 Cables 8 cpnnecuus 7 page 7 iner amp manna 7 pages 39 Clnckinu 7page 10 Inpnma lllplm 7page11 Evaluating me 032mm 7 page 12 Lonphauk Testing 7 page r3 luck m andnm DaIa ns Sync Fallems 7 page 14 llllelcnnnem Iiuer Nudge 7 pages 154 7 Tmuhleshnulinu 7 page 1a Additinnal nesnnms 70333 19 National Semiconducz m I de Simpler alcamIvds j NNatiomll Semiconductor DSQZLV16 General Description The DSSZL ME SenahlerDesena lzerSERDES pzwruans 16Bit Bus LVDS SerializerIDeserializer 25 80 MHz Femuary 2002 Features I 25780 MHZ 5 H 16 senahzeruesenahzer 2 SEGbpS stream mm embeaueu clock mmrmaupn Tms srngve senm suearn srmplmes Lransrernng a 157m or less nus over PCB arauel daaa and dock ams u saves system cost bv narr rowmg aara pams mar m rum reduce PCB layers came mum and cunnedar srze and puns nus saunas paxr ncludes puntm sysrem anu aewce resl capannny The me 00 back arm local loo back features plowde me ronpwmg mncucnamy me man laopuack en a s me user to check me mlegnty at me rranscewerimm the local paraHelauus sure and me system can check me Integnry of me data pansrnrssran nne by enablmg me nne loo back The DSSZLWG Incomcrmes BLVDS srgnzrmg on me mgrr speea no ELVDS provmes a law power and law noise enwronmem vor renamv ransvemng aa a over a senar naus mrssmn pa m e urrrerennal data path canlrm Em by coupung me resumng mnglng ems rugemer I lndependem lrznsmmer and receiver operahan wrm separate duck enable pnwer Govn pins syncnrunlzalmn recewer rocks m randum can I wche e5 reverence clock lrequency lolerance or easy s stem uesngn using hacaHygenerated docks I LIIe and mean loopbatk muaes I us EL 5 Sena transmissmn across backplznes and cames rm I I eqmled l Inlemal PLL nu exlemav PLL componems regunea I Smgle 43 w power Supp y I Lew pnwev 1D4mAypmusmmeL I9mAp recelver at EDNle I momv receiver rnpur mresnom I I Inuusmar an m 35 c lemperature range I gt25kv HEM ESD I Compacl standam 80pin PDFP package Block Diagram nssszIs RDU N LOCAL LE 2002 Navarre Semlwnducwv Cowommn 05200143 www nakann mm 2Him 08 39 92 Jezueueseauazueues SCI I SHE l8399l9LA39IZGSCI D892Lv16 Physical View Physical Dimensions inches mlHimeters unless otherwise nmed NHL srr omii A miiim ii Dimensions shown in mllllmelels only rder Number DSSZLV1STVHG N5 Package Number VHGEUA D892LV16 Block Diagram LINELE Input Parallel toSerial DO DNO15 DO TCLK Timing and Control SYNC DEN TPWDN gt Power RPWDNquot gtCon roi LOCALLE Output Serial to Latch Parallelv ROUT 015 14 W RN REN LOCK 4 Timing and Control Riga Clock Recovery 20014301 D892 LV1 6 Link Example DSSZLVIE 35730 MHz1E1l1 Sevdes 5607128 Mhps quotmum W n am 7 um um W thm a Llncklnn 39 mmum v n m m 25 u M m 5mm hum am pm In Mn um um mm s m mm mm WWII MINES Rummymenus mam W mquot Dawn 7 W2 mm um m 15 LVTI L LvBs Functional Description The D892LV16 combines a serializer and deserializer onto a single chip The serializer accepts a 16bit LVCMOS or LVTTL data bus and transforms it into a BLVDS serial data stream with embedded clock information The deserializer then recovers the clock and data to deliver the resulting 16bit wide words to the output The device has a separate Transmit block and Receive block that can operate independent of each other Each has a power down control to enable efficient operation in various applications For example the transceiver can operate as a standby in a redundant data path but still conserve power The part can be configured as a Serializer Deserializer or as a Full Duplex SERDES The D892LV16 serializer and deserializer blocks each has three operating states They are the initialization Data Transfer and Resynchronization states In addition there are two passive states Powerdown and TRlSTATE The following sections describe each operation mode and passive state Initialization Before the DS92LV16 sends or receives data it must initial ize the links to and from another DSQZLV16 Initialization refers to synchronizing the Serializer s and Deserializer s PLL s to local clocks The local clocks must be the same frequency or within a specified range if from different sources After the Serializers synchronizes to the local clocks the Deserializers synchronize to the Serializers as the second and final initialization step Step 1 When VCC is applied to both Serializer andor Dese rializer the respective outputs are held in TRISTATE and internal circuitry is disabled by onchip poweron circuitry When VCC reaches VCC OK 22V the PLL in each device begins locking to a local clock For the Serializer the local clock is the transmit clock TCLK For the Deserializer the local clock is applied to the REFCLK pin A local onboard oscillator or other source provides the specified clock input to the TCLK and REFCLK pin The Serializer outputs are held in TRISTATE while the PLL locks to the TCLK After locking to TCLK the Serializer block is now ready to send data or synchronization patterns If the SYNC pin is high then the Serializer block generates and sends the synchronization patterns syncpattern The Deserializer output will remain TRlSTATE while its PLL locks to the REFCLK Also the Deserializer LOCK output will remain high until its PLL locks to an incoming data or sync pattern on the RIN pins Step 2 The Deserializer PLL must synchronize to the Seri alizer to complete the initialization The Serializer that is generating the stream to the Deserializer must send random nonrepetitive data patterns or syncpatterns during this step of the Initialization State The Deserializerwill lock onto syncpatterns within a specified amount of time The lock to random data depends on the data patterns and therefore the lock time is unspecified In order to lock to the incoming LVDS data stream the Deserializer identifies the rising clock edge in a syncpattern and after 150 clock cycles will synchronize If the Deserial izer is looking to a random data stream from the Serializer then it performs a series of operations to identify the rising clock edge and locks to it Because this locking procedure depends on the data pattern it is not possible to specify how long it will take At the point where the Deserializer s PLL locks to the embedded clock the LOCK pin goes low and valid data appears on the output Note that the LOCK signal is synchronous to valid data appearing on the outputs The user s application determines whether syncpattern or look to random data is the preferred method for synchroni zation If syncpatterns are preferred the associated deseri alizers LOCK pin is a convenient way to provide control of the SYNC pin Data Transfer After initialization the D892Lv16 Serializer is able to transfer data to the Deserializer The serial data stream includes a start bit and stop bit appended by the serializer which frame the sixteen data bits The start bit is always high and the stop bit is always low The start and stop bits also function as clock bits embedded in the serial stream The Serializer block accepts data from the DlNODlN15 par allel inputs The TCLK signal latches the incoming data on the rising edge if the SYNC input is high for 6 TCLK cycles the DSQZLV16 does not latch data on the DlNODIN15 The Serializer transmits the data and clock bits 162 bits at 18 times the TCLK frequency For example if TCLK is 60 MHz the serial rate is 60 X 18 1080 Mbps Since only 16 bits are from input data the serial 39payload rate is 16 times the TCLK frequency For instance if TCLK 60 MHz the payload data rate is 60 X 16 960 Mbps TCLK is provided by the data source and must be in the range of 25 MHz to 80 MHz When the Deserializer channel synchronizes to the input from a Serializer it drives its LOCK pin low and synchro nously delivers valid data on the output The Deserializer locks to the embedded clock uses it to generate multiple internal data strobes and then drives the recovered clock on the RCLK pin The RCLK is synchronous to the data on the ROUTO15 pins While LOCK is low data on ROUTO15 is valid Otherwise ROUTO15 is invalid ROUTO15 LOCK and RCLK signals will drive a minimum of three CMOS input gates 15pF total load at a 80 MHz clock rate This drive capacity allows bussing outputs of multiple Deserializers and multiple destination ASIC inputs REN controls TRlSTATE of the all outputs The Deserializer input pins are high impedance during Re ceiver Powerdown RPWDN low and poweroff VCC 0V Resynchronization Whenever the Deserializer loses lock it will automatically try to resynchronize For example if the embedded clock edge is not detected two times in succession the PLL loses lock and the LOCK pin is driven high The Deserializer then enters the operating mode where it tries to lock to random a data stream It looks for the embedded clock edge identifies it and then proceeds through the synchronization process The logic state of the LOCK signal indicates whether the data on ROUT is valid when it is low the data is valid The system must monitor the LOCK pin to determine whether data on the ROUT is valid Because there is a short delay in the LOCK signals response to the PLL losing synchroniza tion to the incoming data stream the system must determine the validity of data for the cycles before the LOCK signal goes high The user can choose to resynchronize to the random data stream or to force fast synchronization by pulsing the Seri alizer SYNC pin Since lock time varies due to data stream characteristics we cannot possibly predict exact lock time The primary constraint on the random lock time is the initial phase relation between the incoming data and the REFCLK when the Deserializer powers up An advantage of using the SYNC pattern to force synchronization is the ability for user to predict the delay for PLL to regain look This scheme is left up to the user discretion One recommendation is to provide a feedback loop using the LOCK pin itself to control the sync request of the Serializer which is the SYNC pin If a specific pattern is repetitive the Deserializer s PLL will not lock in order to prevent the Deserializer to lock to the data pattern rather than the clock We refer to such pattern as a repetitive multitransition RMT This occurs when more than one LowHigh transition takes places in a clock cycle over multiple cycles This occurs when any bit except DlN 15 is held at a low state and the adjacent bit is held high creating a 01 transition The internal circuitry accomplishes this by detecting more than one potential position for clock ing bits Upon detection the circuitry will prevent the LOCK output from becoming active until the RMT pattern changes Once the RMT pattern changes and the internal circuitry recognized the clock bits in the serial data stream the PLL of the Deserializer will lock which will drive the LOCK output to low and the output data ROUT will become valid Special Modes Powerdown The Powerdown state is a low power sleep mode that the Serializer and Deserializer will occupy while waiting for ini tialization You can also use TPWDN and RPWDN to re duce power when there are no pending data transfers The Deserializer enters Powerdown when RPWDN is driven low In Powerdown the PLL stops and the outputs go into TRISTATE which reduces supply current to the pA range To bring the Deserializer block out of the Powerdown state the system drives RPWDN high When the Deserializer exits Powerdown it automatically enters the Initialization state The system must then allow time for Initialization before data transfer can begin The TPWDN driven to a low condition forces the Serializer block into low power consumption where the supply current is in the uA range The Serializer PLL stops and the output goes into a TRISTATE condition To bring the Serializer block out of the Powerdown state the system drives TPWDNquot high When the Serializer exits Pow erdown its PLL must lock the TCLK before it is ready for the Initialization state The system must then allow time for Initialization before data transfer can begin Loopback Test Operation The DSQZLV16 includes two Loopback modes for testing the device functionality and the transmission line continuity As serting the Line Loopback control signal connects the serial data input RIN to the serial data output DO and to the parallel data output ROUTO15 The serial data goes through deserializer and serializer blocks Asserting the Local Loopback control signal connects the parallel data input DNO15 back to the parallel data out put ROUTO15 The connection route includes all the functional blocks of the SERDES Pair The serial data out put DO is automatically disabled during the Local Loop back operating mode D892LV16 Coding Scheme nannnnnnnmnnnnnnnnnm lib70b Ending Scheme Twn 10bit Dudes I l I 539 WWWWWWWWWWWWWWWM quotquot0 DSEZLVTb Ending Scheme 7639 bits plus Embedded Block Bits D892LV16 Eye Pattern Note There are actually 16 data bits not 10 as shown Please disregard the error in this gure D892LV16 Pin Diagram D552LV1STVHG Top Vlaw I I I I I I I Eu 7 7a 77 7a 75 n 73 72 7 7a 59 58 a7 aa aa a 53 a2 5 wwnw x an nnmgt 2 S onmgt cqu x 53 VW MFCLK a7 mm M 5 as nums am a as anms mm 7 5A wuuvlt mu 8 53 DD cun a 52 mm av m 5 am SSW D592 LV16TVHG WWW Amu x2 a mx noo u M wum 1107 u n nnu72 avm v5 6 wmm mu a 45 mum u aam7 cwm is u qu DEN a 42 rPu nM swc 2n u 7a 2x 22 2a 2o 25 2a 27 2a 2a 30 3 2 53 u 35 35 17 as 35 m I L I l I i I a i nl I i I I Pin Descriptions 27 28 33 34 35 56 57 64 BE 66 Used to strobe ROUT 015 LVcMos Leve Pin Mapping Gigabit Daughter File my designucf SerDes Chip Control Signals NET quotrpwdnquot LOC quotP83quot NET quottpwdnquot LOC quotP27quot NET quotrelquot LOC quotP85quot NET quottclkquot LOC quotP86quot NET quotrclkquot LOC quotP18quot NET quotlockquot LOC quotP20quot File my designvhd entity mydesign is port din out stdogicvector5 downto 0 rout in stdogicvector5 downto 0 rpwdn out stdogic SerDes Chip Inputs FPGA outputs NET quotdinlt0gtquot LOC quotP12quot NET quotdinlt1gtquot LOC quotP13quot ref out stdogic NET quotdinlt2gtquot LOC quotP21quot tclk out stdogic NET quotdinlt3gtquot Loo quotP22quot rclk in stdogic NET quotdinlt4gtquot LOC quotP38quot lock out stdogic NET quotdinlt5gtquot LOC quotP28quot end mydesign SerDes Chip Outputs FPGA inputs NET routlt0gtquot LOCquotP41quot NET routlt1gtquot LOCquotP59quot NET routlt2gtquot LOCquotP74quot NET routlt3gtquot LOCquotP75quot NET routlt4gtquot LOCquotP66quot NET routlt5gtquot LOCquotP79quot Pins not accessible from VHDL REN1 CONFG11 CONFG21 DEN1 SYNCLOCK LNELEO LOCALLEO DNO9 DOUTO9 Gigabit Daughter Transmit Pattern Chapter 4 HDL Alphabet Soup Signal Design Entity Port Port rnode Entity Architecture Library Package Configuration Transaction Driver Inertial Delay Transport Delay Signals PU Controller FPDP Intense Digital systems transport and operate on signals Signals can be of many types IEEE 1164 integer bit boolean string Unlike variables signals have an associated time value The signal retains this value until it is assigned a new value at a future point in time The sequence of values assigned to a signal over time is called a waveform Design Entity an bl carry Primary programming abstraction is a design entity register logic block chip board or system What aspects of a digital system do we want to describe interface how do we connect to it function what does it do VHDL 1993 vs VHDL 1987 Entity case insensitive entity half Dde a l sum port a b in bit 17 sum carry out bit end entity halfiadder I carry VHDL 1 993 The interface is a collection of ports ports are a new programming object signal ports have a type eg bit ports have a W in out inout bidirectional Entity Examples entity ALU32 is port A B in bitivector 31 downtu 0 l l C out bitivectur 31 downtu 0 Op in bitivector 5 downtu 0 N N Z out bit Z end entity ALU32 MSB LSB entity Diff is port D Q Clk R S in bit Q Qbar out bit end entity Diff VII Entity Examples 16661164 B entity ALU32 is port A B in stdiulogicivector 31 downtu 0 l C out stdiulogicivector 31 downtu 0 Op in stdiulogic Vector 5 downtu 0 lt 3gt Op N N Z out stdilogiic Z end entity ALU32 entity Diff is D Q purt D Q Clk R s in stdiulogic Q Qbar out stdiulogic end entity Diff Clk Architecture a entity halfiadder is b sum port a b in bit sum carry out bit end entity halfiadder carry architecture behavioral of halfiadder is begin sum lt a xorb after 5 ns carry lt a and b after 5 ns end architecture behavior VHDL 1 993f Description of events on output signals in terms of events on input signals the signal assignment statement Specification of propagation delays Type bit is not powerful enough for realistic simulation use the IEEE 1164 value system Architecture carry Example ieeel 164 library IEEE use IEEEstdilogic1164all entity halfiadder is part a b in stdiulogic sum carry out stdiulogic end halfiadder architecture behavioral of halfiadder is begin sum lt axur b after 5 ns carry lt a and b after 5 ns end architecture behavior Use ofthe IEEE 1164 value system simply requires inclusion of the library and package declaration statements EntityArchitecture Pair library IEEE use IEEEstdilogic1 1642111 sum Half Adder entity halfiadder is port a b in stdiulogic sum carry out stdiulogic end halfiadder architecture behavioral of halfiadder is a begin 1 sum lt a xor b after 5 ns carry lt a and b after 5 ns carry end architecture behavior sum Configuration con guration oAn entity may have multiple architectures oSeparation of interface from implementation o Binding rules default and explicit Putting it all together o Primary design units o Entity o Configuration o Package Declaration o Secondary design units o Package body o Architecture o Design units are created in design files o Now you know the layout of a VHDL program Signals u Pct Coritl39hl le r CSA Qoncurrent 1 gnal Assignment library IEEE architecture data ow of fulliadder is use 1EEE5td10gic71 164a11 signal 51 52 53 stdiulogic entity fulliadder is constant gateidelay Time 5 ns port 1111 1112 c7111 in stdiulogic begin um ciout out stdiulogic L1 51 lt 1111 xor 1112 after gateidelay end entity fulliadder L2 52 lt c7111 and 51 after gateidelay L3 53 lt 1111 and 1112 after gateidelay L4 sum lt 51 xor c7111 after gateidelay L5 ciout lt 52 or 53 after gateidelay end architecture data ow 5 1 1111 sum 1112 52 53 ciout c7111 How does it work transaction s lt 1111 nand 1112 after galeidelay value expression time expression l V waveform element Key Points to Remember CSA textual order does not imply execution order CSA speci es new signal value and the time at which the signal will change A CSA is executed when one of its input signals on RHS changes value Multiple CSA statements can be executed at the same simulated time concurrently Simulated Time 75 Simulation Time More Points Initial signal values determined by Initialization when you declare signal Signal type when not initialized Waveforms describe timevalue history of signals Transactions represent signal value assignments One CSA can specify multiple transactions Driver is set of future signal values Multiple drivers is BAD BAD BAD Multiple Transaction Example 1 10A 304 signal transitions for each wavefonn element signal lt 0 l after 10 ns 0 after 20 ns l after 40 ns o Multiple waveform elements can be specified in a single signal assignment statement Multiple Driver Example Bad Stdlogic VS Stdulogic architecture arch4 of nandcircuit is signal Sel A B stdlogic signal Y stdlogic begin Y lt not A and B and Sel Y lt not A or B and not Sel end arch4 l Stdlogic allows multiple drivers 2 Resolution function gets called to clean up the mess 3 Resolution function is an LUT 4 Many people do this Without intention and this leads to long debug sessions signal signal Y begin 1 Stdulogic does not allow multiple drivers 2 This code Will not compile Conditional CSA library IEEE use 1EEEstdilogic71164a11 note type Sel in stdilogicivector downto Z out stdilogicivector 7 downto 0 end entity mux4 entity mux is port 1110 1111 1112 1n3 in stdilogi Vector 7 downto 0 architecture behavioral of mux4 is egin Z lt 1110 after 5 ns when Se1 00 else 1111 after 5 ns when Se1 01 else 1112 after 5 ns when Sel 10 else 4 Eyaiuauon yd 1113 after 5 ns when Se1 11 else 15 Impomm39 00000000 after 5 ns end architecture behavioral o First true conditional expression determines the output value Selected CSA use 1EEEstd10gic71 164911 entity mux4 is port 1110 1111 1112 1113 in stdilogicivector 7 downto 0 Sel in stdilogicivector downto 0 Z out stdilogicivector 7 downto 0 end entity mux4 architecture behavioral2 of mmc4 is egin with Sel select Z lt 1110 after 5 ns when 00 1111 after 5 ns when 01 gagg o dlgl yjoze 1112 after 5 ns when 10 must be me 1113 after 5 ns when 11 1113 after 5 ns when others end architecture behavioral oThe when others clause can be used to ensure that all options are covered oThe unaffected clause may also be used here Conditional CSA order matters library EEE use EEEstdIogic1164a entity prencoder is port 80 818283 in stdlogic Z out stdogicvector 1 downto 0 end entity prencoder architecture behavioral 0f prencoder is begin Z lt 00 after 5 ns when 80 1 else 01 after 5 ns when S1 1 else 10 after 5 ns when 82 1 else 11 after 5 ns when S3 1 else 00 after 5 ns end architecture behavioral RHS Right Hand Side expressions are evaluated in the order they appear The 1St true conditional expression decides the output value If all conditional expressions are false the output value stays unchanged Synthesis will preserve evaluation order when making hardware Selected CSA order not important library IEEE39 use EEEstdlogiC1164all39 entity regfile is port addr l addr2 in stdogicvector 2 downto 0 regout l regout2 out stdogicvector 31 downto 0 end entity regfile architecture behavior of regfile is signal regO regZ reg4 regG stdogicvector 31 downto 0 x 12345678 signal reg l regB regS reg7 stdogicvector 31 downto 0 Xquotabcdef00 begin with addr l select regout l lt regO after 5 ns when 000 reg l after 5 ns when 001 regZ after 5 ns when 010 regB after 5 ns when 011 regB after 5 ns when others with addr2 1 downto 0 select regout2 lt regO after 5 ns when 00 reg after 5 ns when 01 regZ after 5 ns when 10 regB after 5 ns when 11 regB after 5 ns when others39 end architecture behavior RHS expression order is NOT important All possible values of conditional expression must be tested for Exactly one conditional expression must be true in all cases CSA and Synthesis Only 0 1 Z and can be assigned to signals 0 Only 0 and 1 can be part of evaluation expression in conditional or selected CSA Delay Models o Inertial delay o default delay model o suitable for modeling delays through devices such as gates o Transport Delay o model delays through devices with very small inertia eg Wires o all input events are propagated to output signals o Delta delay owhat about models where no propagation delays are specified o infinitesimally sma delay is automatically inserted bythe simulator to preserve correct ordering of events Intertial Delay Input 39 t 8 s mpu output out 1 a 3 2 115 Out 2 gt e 5 10 15 20 25 30 35 8ns Out1 lt X xor y after I Out2 lt reject 2 ns inertial X xor y after 5 ns Transport Delay architecture transportidelay of halfiadder IS 51 signal 51 52 stdilogic 0 b sum begin 51 lt a xor b after 2 ns 52 lt a and b after 2 ns 52 sum lt transport 51 after 4 ns Cm carry lt transport 52 after 4 ns end architecture transportidelay a 17 Sum Delta Delay library IEEE use 1EEEstdlogicl l64all entity combinational is port 11111112 in stdilogic z out stdilogic end entity combinational 1111 51 52 architecture behavior of combina onal signal 51 52 s3 s4 stdilogic 0 be 3911 51 lt not 1111 52 lt not 111239 53 lt not 51 and 1112 54 lt not 52 and 1111 z lt not 53 and s4 39 end architecture behavior s3 s4 Delta Delay Deha evems Ordering s
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