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This 6 page Class Notes was uploaded by Misael Dooley on Saturday September 19, 2015. The Class Notes belongs to ELEG403 at University of Delaware taught by Staff in Fall. Since its upload, it has received 30 views. For similar materials see /class/207137/eleg403-university-of-delaware in Electrical Engineering at University of Delaware.
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Date Created: 09/19/15
Appendix A Host Computer Interface The host computer interface is contained on a plugin module designed for the IBM PCXT AT bus It includes the converters counters registers and programmedlogic components which control the receiver and produce timing signals It normally produces an interrupt upon completion of each ND conversion which occurs three times in each GRI one each for the I and Q integrators plus a third for the signallevel indicator which results in between 30 and 75 interrupts per second depending on the LORANC chain rate or GRI At interrupt time the program can modify the timing generator registers read the ND converter buffer ADCBUF set the AD converter multiplexor address ADCMUX pulsecode buffer PCBUF and parameter register PAR for the next GRI Since the integrators used in the receiver itself accumulate only over the 8ms PCI it is the responsibility of the program to accumulate these three channels of data for subsequent GRIs At any time the program can output previously computed values to the D A converter A DACA and D A converter B DACB to set the precision oscillator frequency and receiver gain control voltages respectively A1 Programming Registers The receiver has eight programming registers located in the port block 03000307 heX as shown in Figure A 13 and described below A11 0300 AMD9513A Timing Generator control TGC and 0301 AMD9513A Timing Generator data TGD The TGC and TGD registers correspond to the control and data paths described in the AMD9513A documentation Both registers are readwrite A12 0302 NB Converter Buffer and Multiplexor Address ADCBUF For read operations the ADCBUF register contains the result of the most recent ND conversion The data are accurate for only a few milliseconds since the integrators have a small but signi cant amount of leakage The data format is offsetbinary with 0 the most negative value 255 the most positive and 128 the nominal zero value When the data are read bit 7 DONE of the ADCGO register is automatically cleared 0300 TGC Timing Generator Control readwrite 0301 TGD Timing Generator Data readwrite 0302 ADCBUF ADC Buffer read ADC Multiplexor Address write 0303 ADCGO ADC Status read ADC Start write 0304 DACA DAC A VCO Buffer write 0305 DACB DAC B AGC Buffer write 0306 CODE Pulse Code Buffer write 0307 PAR Parameter Buffer write Figure Al Receiver Controller Registers 28 For write operations the ADCBUF register contains the multiplexor address for the input to be converted Note that an MD conversion cannot be started until 50 ns after the multiplexor address has settled therefore the two operations cannot be combined in the same instruction The multiplexor address assignments are given in the following table Channel Input 0 I channel integrator output l7 V 1 Q channel integrator output l7 V 2 receiver signal level l7 V 37 not used A13 0303 AD Converter Status and AID Converter Start ADCGO For read operations bit 0 BUSY indicates the AD converter is actively converting a value while bit 7 DONE indicates the conversion has completed and data are ready to be read from the ADCBUF register For write operations the ADCGO register is used to start an AD conversion which normally takes about 100 us Writing anything to this register starts the conversion and sets bit 0 BUSY of the ADCGO register When complete bit 0 is cleared bit 7 DONE is set and an interrupt is signalled at the PC interrupt level determined by dipswitch S301 see Drawing Sheet 5 A14 0304 DA ConverterA DACA and 0305 DA Converter B DACB The DACA and DACB registers contain the values to be converted to analog representation and are writeonly The data format is offsetbinary with 0 the most negative value 255 the most positive and 128 the nominal zero value DACA controls the gain of the receiver while DACB controls the precision oscillator frequency The gain and offset for each DAC can be adjusted by potentiometers as specified in the following table DAC Function Offset Gain A osc frequency R307 R309 B receiver gain R304 R306 A15 0306 PulseCode Buffer CODE The PCBUF register contains the LORANC pulse phase code for the selected master or slave station and is writeonly The pulses are transmitted beginning with the most significant leftmost bit with a value of0 corresponding to a code and 1 corresponding to a code A16 0307 Parameter Buffer PAR The PAR register is used to control various details of system operation The bits of the 8bit byte are interpreted according to the following figure The unlabeled bits are not used 7I6s432I1o IENGI I I IGATEIIGATEOI TCl I TCOI If bit 7 ENG is set the N D converter starts automatically at the end of the next GRI if clear the converter is started by the program upon a write to the ADCGO register Bits GATE1 0 select the gating source for the rf and integrator switches according to the following table 29 GATE10 1f switch integ switch 0 always on always on 1 GRI GRI 2 PCI PCI 3 PCI STB Bits TCl0 control the integrator time constant according to the following table TCl 0 time constant 0 036 ms 1 0264 ms 2 10 ms 3 short caps A2 Timing Generator Operation All signals used by the receiver and provided as outputs are derived from the 5MHZ precision oscillator and a set of counters internal to the AMD9513A timing generator This device consists of five programmable counters together with load and hold registers and gating circuitry In addition a frequency scalar and output divider are provided All counters and the output divider are operated in binary mode while the frequency scalar is normally operated in BCD mode These components are used as described below and in the table Name Pin Function SRCl 33 5 MHz frequency standard SMHZ SRC2 32 lOOkHz clock Pl SRC35 not used GATEl2 not used GATE3 36 group interval GRI GATE4 35 envelope gate PCI GATES 34 special function OUTl 3 200kHz clock P0 OUT2 2 group interval GRI OUT3 40 code shift PCX OUT4 38 cycle strobe STB OUTS 37 special function FOUT 7 countertimer output J 302 A21 Counter 1 P0 P1 Counter 1 counts the 5MHZ precision oscillator to generate a 200kHz asymmetric squarewave signal P0 which is further divided by the ip op IC303A see Drawing Sheet 4 to generate a lOOkHz signal Pl Both of these signals are used by the demodulator which includes internal decoding to generate the four phases required Counter 1 is operated in Mode J as a variable dutycycle rate generator with toggled output and no hardware gating The counter is normally programmed to produce a low interval of 24 us followed by a high interval of 26 us 30 A22 Counter 2 GRI Counter 2 counts the 100kHz output from the external ip op to generate the group interval signal GRI characteristic of the selected LORANC chain The interval is expressed in units of 10 us or one cycle time for instance 9960 for the Northeast LORAN C chain Counter 2 operates in Mode J as a variable dutycycle rate generator with toggled output and no hardware gating The counter is normally programmed to generate a low interval equal to the GRI minus 8 ms followed by an a high interval of 8 ms A23 Counter 3 PCX Counter 3 counts the 5MHZ precision oscillator to generate the lms phase code clock PCX from which the envelope gate PCI is derived It is gated by the GRI signal generated by Counter 2 which persists for 8 ms or eight lms PCI intervals The counter is operated in Mode K as a variable dutycycle rate generator with level gating and toggle output The counter is normally programmed to generate a low interval of 300 us followed by a high interval of 700 us A24 Counter 4 STB Counter 4 counts the 5MHZ precision oscillator to generate the 10us cycle strobe STB which after a programmed delay following the rise of each PCI pulse This pulse brackets the reference zerocrossing of the pulse group which is defined as the zero crossing ending the third carrier cycle of each pulse The counter is operated in Mode L as a hardwaretriggered delayedpulse oneshot with edge gating and toggle output The counter is normally programmed to generate a variable length low interval followed by a lOLls high interval A25 Counter 5 OUT Counter 5 counts the 5MHZ precision oscillator to drive the frequency scalar and output divider which produces the output signals for external devices The counter is operated in Mode K as a variable dutycycle rate generator with level gating and toggle output The gating signal is generated by counter 4 which can be enabled for this purpose under program control When so enabled counter 5 is stopped for the interval programmed in counter 4 enabling precise alignment of the frequency scalar and output divider to UTC The counter is normally programmed to generate a low interval of 5 us followed by a high interval of 5 us for a frequency of 100 kHz This output is programmed internally to drive the frequency scalar and output divider which together divide this frequency by 100000 to generate the lpps output signal The output signal can also be programmed for almost any submultiple of 5 MHz if UTC alignment is not necessary A3 Interface Connectors There are five BNC connectors on the receiver and one on the receiver controller These are intended for use by auxiliary devices including a monitor oscilloscope Connectors J201 J203 J204 J205 and J206 are on the receiver while J301 is on the receiver controller A31 J201 ANT AntennaPreampli er Input This is the antenna input for either a whip antenna or loop preamplifier Selection of either type is by switch S201 31 A32 J203 5MHZ Standard Frequency Output This is the output of the 5MHz precision oscillator which can be connected internally for either sinewave or TTL operation This output is capable of driving only a high impedance load A33 J204 S1 Qlntegrator Output This is the demodulated and integrated Qchannel output This signal ordinarily is connected to the channel2 vertical de ection circuit of amonitor oscilloscope This output is capable of driving only a high impedance load A34 J205 PCI Envelope Gate Output This is the envelope gate PCI signal which consists of eight lms pulses synchronized to the carrier envelope of the pulse group This signal ordinarily is connected to the horizontal trigger circuit of a monitor oscilloscope This output is TTLcompatible A35 J206 SIG 100kHz Signal Output This is the output ofthe lOOkHz receiverjust J J39 the 39 J J 39 This signal ordinarily is connected to the channell vertical de ection circuit of a monitor oscilloscope This output is capable of driving only a high impedance load A36 J301 OUT CounterTimer Output This is the output of the output divider which ordinarily consists of a lpps pulse synchronized to LORAN C reference time but can be programmed for other purposes This output is TTLcompat ible 32 Problem 66 Let PeI average probability of symbol error in to the inphase channel PeQ average probability of symbol error in to the quadrature channel Since the individual outputs of the in phase and quadrature channels are statistfcally independent the overall average probability of correct reception is Pc 1 1 PeI 39 PeQ PeI PeQ The overall average probability of error is therefore Pe II H I O U 309
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