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Microprocessors & Digital Sys

by: Teagan Klocko MD

Microprocessors & Digital Sys ECE 331

Teagan Klocko MD
GPA 3.93

Andrew Mason

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Andrew Mason
Class Notes
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This 20 page Class Notes was uploaded by Teagan Klocko MD on Saturday September 19, 2015. The Class Notes belongs to ECE 331 at Michigan State University taught by Andrew Mason in Fall. Since its upload, it has received 45 views. For similar materials see /class/207384/ece-331-michigan-state-university in Electrical Engineering & Computer Science at Michigan State University.

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Date Created: 09/19/15
ECE331 Announcement HW solution will be posted by Tuesday Exam 1 is on Mon Feb 16 in about 10 days Quiz 3 is Monday Feb 9 last quiz before exam 1 HW4 is due next Friday last HW before exam 1 Lab 3 is next week Start early on the prelab it s longer than previous prelabs but essential for the lab No lab quiz or homework on the week of the exam yay Outline uC Architecture Instruction execution Instruction set Architecture block Computer Bus ecture notes A Folx H39ampo0 r a 1 gum vk Malwe r j F39 Frieda CDh rzzL Lag r93 5 er 3 1 MC68HC812A4 block diagramhandout 1 pp2 MC9312DP256B block diagramhandout 1 pp3 Memory Space Handoutl pp4 Registers RAM EEPROM Expanded memory Vectors Figure 59 IO and peripherals A Simplified ALU 1bit ALU circuit RpartiaEE E l can in A B l l Select inputs Select outputs l ALU Comrol Logic Logic function A OR B Op code in Bin 00 00103 Op code in Hex 02H Nnemonics eg LORAB MESSAGE An op code is decoded to control a bunch of switches Assembly Language Format label opcode operand comments Begin Idaa 10 39abe begins in column 1 Instruction cycles Fetch instruction is read from program memory Decode instruction is examined and operands determined Execute instruction is executed Example code book pp21 LDAA 3000 39 load the contents of 3000 to A STAA 2000 39 store the contents A to memory location S3000 Instruction Set Load store move and transfer instructions Arithmetic instructions Boolean logic and bit Instructions Data test instructions Branch and jump Instructions Function ca Instructions Load Store Move and Transfer Instructions copy data from one location to another Load instructions copy data from memory to a register Store instructions copy data from a register to memory Transfer instructions copy data from a register to another register Move instructions copy data from one memory location to another Exchange instructions are a special case of instruction where the contents of two registers exchange positions Example LDAA Arithmetic Instructions AddSubtract to A from memory AddSubtract to A from memory with carryborrow used to implement multi byte addition AddSubtract to B from memory or from A AddSubtract to B from memory with carryborrow AddSubtract to D from memory IncrementDecrement A B X Y SP memory byte Negate 239s complement A B memory byte Multiply and Divide in registers Example ADDA Boolean Logic and Bit Inst In a microcontroller data is often treated as a set of bits rather than as an integer value The bit oriented instructions allow manipulation of data as a set of bits and to manipulate individual bits within a byte To AND OR or Exclusive OR a memory location into accumulator A or B CCR Example ANDA bitbybit AND ofA and a 8 bit value Data Test Instructions compares two values and is used along with the conditional branch instruction to implement control structures such as decision trees and loops A test instruction compares a single value to zero Instructions exist to compare any register A B D X Y or SP with a value in memory as well as compare register A to B Instructions exist to test register A B or a byte in memory for being zero or negative Example CM PA compare A with a 8 bit value Branch Instructions To execute out of sequential memory locations based on the contents of the condition code register Branch conditions include greater than less than greater than or equal to less than or equal to equal not equal overflow no overflow zero and nonzero Example BEQ branch if previous result is 0 Function Call Instructions Initiate or terminate a subroutine or a service routine Example JSR jump to a subroutine RTI return from a service routine Program Architecture Initialization Main Interrupt Services Subroutines Fault traps EXTERNAL M EMORY EXA MPLES 39 In Expandui opeyfhn mode Ports qssigm 3939o gasses whit dd39q Mimi quot usdh 39wfquotev quot sclt w d39h u HMMl mcwwrj or I ll duiw a1102009 39 Consider 5 o X 8 eltwng dwice mow n flou39s b341 5uarkd oc caud b0 39 9 Channel AD 6 0 RAM 391 waququme H s EX Councd MUL txqu Mada 0 lbxg RAM 39o cm ugh 0 32968 ad39me mm 39 Assame mmanmpd 170 7 How may3 gurbH39S WW3 7 How Mung lbk8 dunes nudzd D ATA 750 7 ADDR Hie A RG 7 Mom I IV CT 3 Es j M8 was A b A b 7 WHd dyuicg Ts offerlower WP EX BuiHm bklb Mcmor usivls 15x4 quotEK VW39mi dbw oe For is LaAcol quot10 5 DATA 050 ADD 1 so we Nfo V New Y a 339 1y 639 1y 539 OH OH OH W A D A b A D A b EX Guvcn rum wml 64k8 RoM con373m Q ZSGNUO nutmeg iv evque BHow Nuns Q EXB chip hltohd4d 2 Ml l I Z How mung address Hm 7 A Addr mm For oh 5 Mom addv lines Program Assembly Illustration ASSEMBLY OF DIRECTIVES AND ASM INSTRUCTIONS Assembly Code 1 Assembled Code LST file label mnemonicz operand3 progdata machine opcode5 directive39 mem addr4 ORG 6000 00006000 DREC FCB AABBCCFFEEO1 6000 AA BB CC FF EE 01 FCB A1B2C3F401 6006 A1 B2 C3 F4 01 FOB 8172635445E501 6008 81 72 63 54 45 E5 01 RESULT RIVIB 0A 6012 000A DCPY RIVIB 10 601C 0010 ORG 4000 00004000 LDS 8000 4000 CF 8000 LDX DR EC 4003 CE 6000 LDY DCF Y 4006 CD 601C LDAA 0 4009 86 00 PSI IA 400B 36 LOOF LDAB 0X 400C E6 00 STAB 0Y 400E 6B 40 CMPB 01 4010 C1 01 BEQ ENDLF 4012 27 05 INX 4014 08 INY 4015 02 INCA 4016 42 BRA LOOP 4017 20 F3 ENDLP PULB 4019 33 PSI IY 401A 35 LDY RESULT 401B CD 6012 STAA BY 401 E 6A ED PULY 4020 31 INCB 4021 52 PSI IB 4022 37 CPX RESULT 4023 BE 6012 BEQ DONE 4026 27 05 INX 4028 08 INY 4029 02 CLRA 402A 87 BRA LOOP 402B 20 DF DONE TBA 402D 18 0F END Notes 1 3 Labels and Directives are used by the assembler to simplify writing code and direct the assembly process During assembly all labels are replaced with appropriate hexadecimal values Directives do not result in any program opcodes although they can generate data to be stored in memory Mnemonics are shorthand names for assembly instructions Mnemonics will be converted to hexadecimal opcodes machine code during the assembly process that are loaded into microcontroller program memory to form the program that can be executed Operands are the data parameters needed to complete a program instruction or assembly directive statement Hexadecimal operands must be begin with a so the assembler knows the value is not a decimal The address mode for instructions is determined by the format of the operand eg specifies an immediate instruction where the operand is the parameter value not an address containing the parameter value Multiple operands can be separated by comma or tabs depending on the assembler used to assemble the code 4 Once ASM code is assembled all instructions and data are assigned to memory addresses The addresses are determined by ORG directives in the ASM code It is useful to differentiate between program memom where instructions and their operands are stored and data memom where non instruction data fields are stored Program memory contains the opcodes that will be fetched and decoded during program execution Data memory contains data values read during program execution or results stored during program execution 5 Operation codes or opcodes are hexadecimal values representing instructions and their operands Opcodes are also referred to as machine code because the binary equivalents ofthese codes tell the microcontroller exactly what do to For assembly instructions the first byte of each line of opcode translates to a specific instruction mnemonic while the remaining values are instruction parameters operands Assembly instruction opcode values will be stored in microcontroller program memory at the address indicated beside each line of opcode and executed when the program is run For data directives data values are stored directly to data memory at the address specified before the data values These values are not instructions and can not be executed as program opcodes Machine Code Upload Record 519 file SOOSOOOOFC show data for data memory show reserved memory bytes in data memory initiated with value 00 show ASM program opcodes to be stored in program memory MEMORY SPACE ADDRESS MEMORY 4 top of 0000 MCU program ReQISterS one instruction Unused Reserved 3 end of 4000 Pprogram top of data more program 6000 gum end of data 8000 Unused t f ta k lt7 op o s c Reserved vares lt7bottom of stack Handout 3b lnstruction Tables Functional Instruction Groups 0 Data TransferManipulation WWW o Arithmetic 0 Logic amp Bit Operations Lngcalshi lenn 39 Data TeSt Lugmaismungmnemmy 39 Branch Lugicalshi nghm 0 Function Call Subroutine Lagical sum quotng Ailiiimeticsm ieftA Ailiiimetic smmenu Ail imenn 5m right memury Arl ime c smhngnm Rotate lnsmmions imam le A maugn navy Rmaie ngm memniymm navy imam ngntA thinugh my Tabie 27 l Summary of shift and rotate insliuctions ShiftRotate CCR Actions 0 CA VA ZA NA except LSR Where N0 Arithmetic Logic amp Bit Operations Mnemon m Functian Operation ANDA ltonrgt ANDAwIthmemury APMJM ANDE mp ANDBwithmemury BENDM ANDcCltuurgt AND ECRwILhmemuryDleavCCR bus CCRPKICWM ORA mp Exciuswe OR Awllh memmy A A A e M ORE ltuurgt ExniusweOREwim memory BHBJWM RM mph on mm memo A M ORABltonrgt RBwim BFiEJHM GRCCltoDrgt DRCCRwimmemary CER CCRvM CLC Cie Don C cpo cu Cieari mm CCR ig CLV Ciear um CCR COM ltunrgt Dne39s campiamemmemary M P am My CDMA Dne cum i am A FHA COMB One s cumni memE B e SFFV B NEG ltaDrgt Twu39scumuiememmemury M 7 sun 7 M NEGA Twa39slmmuiememA APSUOVW NEGE Twa scompremema E 9 3007 Bi Table 23 Summary of Booiean ioglc instructions Mnemnnic Functian Ouemtion mm ltuprgt mski Cenv ms in memnry M 7 N m1 WA ltnprgt ErnesrA A HM EWltHWgt39 Eill s39B BHW BSanpstka Satoism memm MHsttmm mm 1 mph can be specl en using an exam velawe addressing modes in arm and arm 2 lton can hc nwhcd osmgoum memo and mode mm indwmct addressmg m e ue able 29 Summary of bit operations Logic COR Actions 0 AND OREOR V0 ZA NA except ANDOR CC 0 OMCOMAICOMB C 0 A NA o E lNEGANEGB C A V ZA NA o BITABITBBCLRBSET V0 ZA NA


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