Introduction To Digital System Design
Introduction To Digital System Design ECE 27000
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Introduction to Digital System Design Page 1 DESIGN OF A SIMPLE COMPUTER As a comprehensive case study in digital system design we would like to examine the design and implementation of a simple computer In particular the overall approach based on a topdown specification of functionality followed by a bottomup implementation of the various mp39d m functional blocks will prove useful to our basic understanding of how b0tt0m39quotP real microprocessors and microcontrollers work Earlier in this course we learned about a number of digital system building blocks This included combinational elements such as decoders priority encoders and multiplexers as well as sequential elements such as latches and ip ops We then reviewed how these combinational and sequential elements can be combined to build digital systems We also learned how digital systems could be speci ed using a hardware description language and subsequently ngmmmable implemented using programmable logic devices P LDs logic devices Our purpose here is to apply this background to the design of a simple computer Before we go any further though some basic de nitions are in order First what is a computer What distinguishes computers computer from random combinations of logic or from simple light ashing state machines Simply stated a computer is a device that sequentialy storedprogram executes a stored program The program executed is typically called software if it is a userprogrammable general purpose computer software system or called rmware if it is a singlepurpose nonuser rmware programmable system also referred to as a turnkey system A given program consists of a series of instructions that the machine understands Instructions are simply bit patterns that tell the computer what operation to perform on speci ed data That a program is stored implies the existence of memory To perform the series of instructions memory stored in memory two basic operations need to be performed First an instruction must be fetched read from memory Second that instruction must be executed eg two numbers are added together to produce a result The memory that is used to store a program can take many different forms ranging from removable media devices such as CDROMs to patterns in the metal layer of an integrated circuit While the physical implementation of the memory in which the program is stored may vary the information stored in memory is interpreted ie fetched and executed the same way Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design Given the basic de nition of a computer above what is Page 2 microprocessor Classically it is a singlechip embodiment of the microprocessor major functional blocks of a computer Today though the term microprocessor is o en applied to a wide range of single and multi chip computational devices ranging from mainframes on a c ipquot use in personal computers and workstations to small dedicated controllers used in a wide variety of intelligent devices They can range in physical size from packages with several hundred pins to packages with only a few pins some examples are illustrated in Figure 21 They can range in cost from less than one dollar to hundreds of dollars The simple computer we will be designing here c n be im lemented using a modestsize PLD we could therefore rightfully call this singlechip embodiment of our simple computer a microprocessor a Figure 21 Contrasting contemporary microprocessors a an ampbit PIC microcontroller b a 16bit Motorola 68HC12 microcontroller and c a 64bit MIPS microprocessor Finally what is a microcontroller and how does it differ from a microprocessor Typically a microcontroller integrates in addition to a microprocessor a number of peripheral devices that are commonl used in controltype applications onto a single integrated circuit and are thus often referred to as singlechip microcontrollersquot Peripheral devices get their name from the fact that they provide interfaces with devices that are external ie For example a common series of operations o en performed in control applications is 1 input analog signals from sensors 2 process them according to some algorithm 3 and output analog control voltages to actuators A device that digitizes an analog input voltage is called an analogtodigital A toD converter Conversely a device that produces an analog output voltage based on a digital code is called a digitaltoanalog Dto A converter AtoD and DtoA converters are of peripherals one might nd integrated onto a microcontroller chip 392 Little Bits of Digital Wisdom 7 Supplemental Text microcontroller Y pm39pheral devices 2001 by D G Meyer Introduction to Digital System Design Page 3 Other common peripherals include communication controllers timer modules and pulsewidth modulation PWM generators Later we will see a variety of applications for all ofthese integrated peripherals 21 Computer Design Basics How can we apply what we have learned thus far about basic digital system building blocks toward building a simple computel Basically what we need is some way to structure and break down this design problem because now it is a somewhat bigger than drawing a single state transition diagram or lling out a truth table We will need a structured approach that enables us to take a written description of the functions performed by our simple computer and create a highlevel block diagram Based on this diagram we can proceed to de ne what each block does and ultimately design the circuitry required to implement each block Before starting this process though we need to de ne what we mean by the structure of a computer Architecture is a word commonly architecture used to depict the arrangement and interconnection of a computer s functional blocks While some might argue that this de nition of computer architecture is a bit simplistic it will serve our purposes for the discussion that follows Before starting to design our simple computer let us rst consider a real world analogy building a house Where is the logical place to start Probably with a big picture ie an exterior elevation or plan bigpicmre view of the entire project Of course the oor plan and exterior elevation are greatly in uenced by the size shape and grade of the lot chosen for the house Once we know the physical constraints dictated by our choice of lot we can then begin to develop a oor plan At this stage we can de ne the overall functionality of the house ie the purpose of each room Once we have de ned the functionality of each room the next step is to determine their arrangement and interconnection Once we have a working oor plan we can begin to embellish it with a number of details for example the location and size of windows the location of light xtures and their associated wall switches the location of power outlets the routing of plumbing etc The important thing to note f39om this analogy is that we have described a topdown design process starting with a big picture and progressively embellishing it with layers of details Figure 2 2 depicts such a progression Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design l L l I V r 7 quot a ma quot lohen V 1 I 7 ll 6 jailiklii mlgwii W a 0 Great u 39 in l riquot I 1 X 7 l Room c Figure 22 Topdown design of a house a the big picture b the floor plan c details of a particular room Once all the design specifications have been formulated how would we proceed to build our house From the ground up assuming we have adequate financing of course We have to dig a hole first perhaps analogous to going into debt then pour a foundation stick build the basic structure put a roof on it complete the exterior walls and finally embellish each room with its finishing details Note that the order in which this bottom up implementation proceeds is quite important certainly one would not wish to start hanging drywall before the roof is in place or run plumbing lines before the floor joists are in place Clearly there is a structured ordered way in which the entire process must take place an approach strikingly similar to the one we will follow in designing our simple computer What would be a good name for the overall process described above Ignoring the financial aspects for a moment we could aptly call it the topdown specification of functionality followed by bottomup implementation of each basic step or block More succinctly we could call it topdown speci cation and bottomup implementation This is the process we will apply to the design and implementation of our simple computer First a disclaimer The initial machine we design will be very very simple It will be an 8bit machine with just a few instructions Further there will be a single instruction format layout of bit patterns as well as a single addressing mode way that the processor accesses operands in memory By the time we finish this first phase design however we will find out that even this rather simple machine is fairly complex in terms of implementation details Once we have mastered our simple computer we will then add modern conveniences such as input and output or lO transfer of control instructions stack manipulation instructions and subroutine Little Bits of Digital Wisdom 7 Supplemental Text Page 4 topdown specification bottomup implementation instruction format addressing mode 2001 by D G Meyer Introduction to Digital System Design Page 5 linkage instructions We will have the makings of a socially socially redeeming computer once we get done plus have a rm footing upon redeeming which to understand the architecture and instruction set of a real computer 22 Simple Computer Big Picture Just as one might begin the design of a house by sketching an exterior elevation view we will begin the design of our simple computer with a big picture of its control console In the old days which was actually old days not so long ago computers had lots of lights and switches on their front panels The Digital Equipment Corporation PDP8 the rst commercial minicomputelquot illustrated in Figure 2 3 was a good minicomputer example of such a computer The Intellect 8 microcomputer system one of the rst commerciallyavailable microprocessor development systems from Intel based on the 8008 microprocessor was another example Frankly these groundbreaking computer systems were a lot more interesting and fun to watch crunch numbers than today s computersand a lot less irritating than the this application has performed an illegal function and will be shut down message we ve all become accustomed to today crunch numbers Figure 23 World s rst desktop Figure 2394 our Simple minicomputer the PDP8 ComPUterconSOIe39 Our computer s console then will have some lights that indicate the result of the most recent computation along with some switches that will be used to input data A START pushbutton will be included to get the machine into a known initial state in preparation for running a program and a CLOCK pushbutton will be included to facilitate debugging as we manually clock the machine from statetostate An artist s conceptionquot of our simple computer s console is shown in Figure 24 Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design Returning to the house analogy for a moment the oor plan of a computer is basically its instruction setand programming model The instruction set is simply the list of operations that the computer performs There are ve fundamental groups or categories of machine instructions data transfer arithmetic logical or Booleanquot transfer of control and machine control Some computers include a sixth group dedicated to speci c applications eg multimedia extensions or graphics support The addressing modes that instructions can use to access operands in memory are also a key aspect ofa computer s instruction set The programming model of a computer is the software writer s view of the machine Basically it tells what resources are available for the programmer s use in particular the machine s registers A register is simply a memory location within the processor that can be used to store intermediate results andor as an operand or as a pointer to an operand used in a computation As alluded to above the programming model and instruction set of our computer will be relatively simple Initially there will only be one register called the accumulator or A register sonamed because it is the register in which the result of computations accumulate Our computer will also include several condition code bits a zero ag ZF negative ag NF over ow ag VF and carryborrow ag CF Before we complete this chapter we will add a stack pointer register and discuss the role of index registers The instructions executed by our simple computer will be of the xed length variety ie all 8bits in size hence its designation as an 8bit computer that consist of two xedlength elds The upper 3bits of each instruction will indicate the operation to be performed and is therefore called the operation code eld or opcode eld The lower 5bits will indicate the memory address in which the operand is located or a result is to be stored The 5bit memory address dictates a maximum memory size of 25 32 locations For those who have become jaded by multimegabyte programs that appear to do trivial things this may not seem like much memory Fortunately though it will be enough to illustrate basic principles of instruction execution despite being too small to contain a practical ie useful and socially redeeming program In addition to xed eld decoding another simpli cation in our initial design will be a single addressing mode An addressing mode is the mechanism or functionquot used to generate what is often called the Little Bits of Digital Wisdom 7 Supplemental Text Page 6 instruction set programming model addressing modes pointer condition code bits Z F NF VF CF opcode eld addressing mode 2001 by D G Meyer Introduction to Digital System Design Page 7 effective address of an operand ie the actual address in memory e em ve where an operand is stored The addressing mode our machine will address support might aptly be called absolute addressing based on the fact that this 5bit eld directly indicates the effective address in memory where the operand is stored It is important to note at this point that not all manufacturers of microprocessors agree on the names ascribed absolute to certain addressing modes What we have just referred to as an addressing absolute addressing mode is typically called extended by Motorola mode or direct by Intel One other bit of terminology worth mentioning before delving into the instruction set concerns the number of addresses a given instruction or more generally a machine can accommodate Our simple computer here could be described as a two address machine which means that two different locations at two different addresses are used in a given operation eg ADD In our computer one location will be the A register the accumulator and the other will be contained in memory Note that a sideeffect of such an arrangement is that the result of the computation will ovenNrite one of the operands here the value in the A register the operand in memory will be unaffected As one might guess there are a lot of variations in instruction format and addressing capability ranging from singleaddress instructions to threeaddress or more instructions twoaddress machine 23 Simple Computer Floor Plan We are now ready to introduce the oor plan instruction set of our simple computer Note that we will initially de ne six of the eight possible instructions afforded by our 3bit opcode field We will save the last two opcode bit patterns to de ne some extensions to our instruction set later in this chapter Our simple computer s instruction set is given in Table 21 Table 21 instruction set Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design The rst two instructions LDA and STA are examples of data transfer group instructions As their assembly mnemonics imply these instructions transfer data between the A register accumulator and memory For the load A LDA instruction the source of the data is memory location addr and the destination is the A register For the store A STA instruction it is just the opposite here addr indicates the location in memory where the value in A also referred to as the contents of A is to be stored As it turns out load and store instructions are the most popular instructions in any machine s instruction set often comprising as much as 30 of the compiled code for typical applications A shorthand notation we will use throughout the remainder of this text is the use of parenthesis to indicate the contents of a particular register or memory location This allows us to describe what an LDA instruction does as simply A lt addr and what an STA does as addr lt A An important point to note in both cases is that the source of the data transfer ie addr for LDA and A for STA does not change or is unaffected as a result of the instruction execution Continuing down the list of available instructions we next nd two arithmetic group instructions ADD and SUB The ADD instruction performs the operation A lt A addr using radix or two s complemenb arithmetic and sets the condition code bits based on the result obtained Details on radix arithmetic and condition codes can be found in the material presented earlier in this course The SUB instruction performs the operation A lt A addr and sets the condition code bits accordingly Recall that there is an important difference regarding how the carry ag CF is affected in an addition versus a subtraction Following an ADD the carry ag is the carry out of the most signi cant or sign position whereas following a SUB the carry ag is the complementof the carry out of the sign position based on its interpretation as a borrow Because of this difference between ADD and SUB the CF bit is sometimes referred to as the carryborrow ag which is the way we will formally refer to it If what we just described seems a bit fuzzy now would be a good time to review this material Moving down the chart we nd that our next instruction AND is from the logical or Boolean group Because logical group instructions perform bitwise operations they are sometimes referred to as bit manipulation instructions At minimum most microprocessors worth their silicon generally have at least three Boolean instructions AND Little Bits of Digital Wisdom 7 Supplemental Text Page 8 data transfer group instructions assembly mnemonics LDA S TA arithmetic group instructions ADD SUB two s complement arithmetic carryborrow ag logical group instructions bit manipulation instructions 2001 by D G Meyer Introduction to Digital System Design OR and NOT many also include XOR Our simple computer however will just implement the rst of these operations which can be described using the notation A lt A n addr where the m symbol is used to denote the bitwise logical AND of the two operands to produce the corresponding result bits No instruction set would be complete without a way to stop the machine Our sixth and nal for now instruction HLT for halt serves this purpose The HLT instruction is an example of a machine control group instruction Execution of the HLT instruction will freeze the machine at its current point in the program being executed and prevent the machine from fetching or executing any additional instructions until it is restarted by pressing the START pushbutton described previously 24 Simple Computer Programming Example To better understand how our simple computer operates we will walk through the execution of a short program This program will exercise each instruction in our simple computer s repertoire An important point to consider before proceeding is that it would be rather dif cult to design a simple computer that directly interprets the instruction mnemonics ie LDA STA etc we have de ned Rather it is much easier to design a machine that directly interprets bit patterns 0 s and 1 s that represent these instructions This means that before we can place our program in memory we must translate the instruction mnemonics into bit patterns code the machine understands called machine code This translation process is called assembly since machine code is created directly assembled based on instruction mnemonics As one might guess instruction mnemonics are typically referred to as assembly level mnemonics or simply assembly language A software program that translates assembly level mnemonics into machine code is called an assembler If one is unfortunate enough to perform the translation by hand the process is called hand assembly Fortunately most computer programming is done at a higher level of abstraction using highlevel languages such as Here a compiler program is used to translate code written in highlevel language into assembly code An assembler program is then used to translate the compiler s output into machine code for the target processor We will nd though that a rm grasp of assembly language programming techniques is essential for effectively utilizing the resources integrated Little Bits of Digital Wisdom 7 Supplemental Text Page 9 AND OR NOT XOR HLT machine control group instructions machine code assembly language h and assembly highlevel language compiler 2001 by D G Meyer Introduction to Digital System Design into a modern microcontroller Once we master assemblylevel programming we ll consider how to program a microcontroller using But to get there we need to start at the basic bit level so let s return to the illustrative simple computer program in Table 22 Table 22 Programming example Addr Instruction Comments 00000 LDA 01011 Load A with contents of location 01011 00001 ADD 01100 Add contents of location 01 1 00 to A 00010 Store contents ofA at location 01101 oad A with cntents of location 01011 00110 LDA 01011 I 00111 ISUB 01100 ISubtract contents oflocation 01100 fromA STA 01111 Store contents ofA at location 01111 One of the rst things we need to know is where in memory our program needs to be located The logical thing to do is place our program at the beginning of memory ie starting at location 000002 We can then design the circuitry that alter the START pushbutton is pressed begins fetching instructions from memory at location 000002 Recalling that instructions are of xed length 8 bits and that memory locations are 8bits wide we realize that consecutive hstructions will occupy consecutive memory locations We can then imagine a pointer that tells us which instruction is to be executed and that gets incremented after each instruction is fetched Such a pointer is typically referred to as either an instruction pointer or a program counter A snapshot of what our short program looks like in memory prior to execution is provided in Figure 25 just the rst half of memory from locations 000002 to 011112 is shown The lightly shaded part corresponds to the assembled machine code Referring back to Table 22 note that the rst instruction at address 000002 is load accumulator LDA with the contents of memory location 010112 Since the 3bit opcode for LDA is 000quot this instruction is encoded as the bit pattern 000 01011 in memory Stated another way the instruction LDA 01011 has been assembled into the machine code 000 01011 We could go through a similar hand assembly process for the rest of the instructions that comprise the program up to and Little Bits of Digital Wisdom 7 Supplemental Text Page 10 instruction pointer program counter 2001 by D G Meyer Introduction to Digital System Design including the HLT instruction at location 010012 note that the address eld ofthis instruction is not used and is shown here to be 00000 Contents llL Beam in the Bits Scotty One important detail we will ignore for the moment is how these bit patterns get loaded into memory In a later chapter we ll discuss how to write what s called a loader program which as its name implies does just that For now assume Scotty of Star Trek fame for those of you much younger than the author has used a molecular beam transporter to beam the bitsquot into memory 1 01010 01011 10101010 01100 01010101 Figure 25 Memory snapshot prior to program execution The operands used by each arithmetic ADD SUB or logical AND operation will be stored at locations 010112 and 011002 in the darker shaded area of Figure 25 note that we have initialized these two locations to arbitrarily chosen values The results of each operation ADD AND SUB will be stored in three consecutive locations starting at location 011012 Note that our computer s memory will contain a mix of instructions and data operands and results No Stopping It Now What happens if the HLT instruction is omitted Perhaps even worse than not stopping the computer will start executing data which as one might imagine is not a pretty sight or stated less formally causes bits to fly all over the place and at best leads to very strange program behavior Any honest programmer not to be confused with an honest politician however will confess that heshe has inadvertently done this at least oncequot Given that our computer only understands 0 s and 1 s rather than the more humanfriendly assembly mnemonics the question that begs is How is our computer able to distinguish between instructions and dataquot The hopefully obvious answer is It can t Rather it has to be Little Bits of Digital Wisdom 7 Supplemental Text Page 11 executing data honest programmer 2001 by D G Meyer Introduction to Digital System Design Page 12 told which locations contain instructions and which contain data The convention we will use to make this distinction is that our programs will always start at location 000002 and continue until they reach a halt HLT instruction any locations following the HLT instruction may be used for data operands or results Location Contents 10101010 01010101 11111111 Figure 26 Result alter executing the rst three instructions We are now ready to step through the execution of this program Referring back to Table 22 we see that the purpose of the rst three instructions is to add the two operands at locations 010112 and 011002 respectively and store the result at location 011012 As illustrated in Figure 26 the result obtained will be 111111112 recall that this is the 8bit representation for quot 1quot in two s complement notation Also the negative ag NF will be set to the carry ag CF will be cleared to the over ow ag VF will be cleared to and the zero ag ZF will be cleared to selfmodi ing code Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design Page 13 Again referring back to Table 22 we see that the purpose of the next three instructions is to logically AND the two operands and store the result at location 011102 Note that for the AND operation the carry ag CF and over ow ag VF are meaningless and therefore should be unaffected by the execution of the AND instruction The result obtained however may be negative in a two s complement sense or zero so the negative ag NF and zero ag ZF should be affected A snapshot of memory following execution of the three ANDrelated instructions is provided in Figure 27 Note that since the result obtained is 000000002 the zero ag is set to 1 Location Contents AND 10101010 n01010101 00000000 Figure 27 Result after executing the middle three instructions The purpose of the next group of three instructions is to take the difference of the two operands at locations 010112 and 011002 Speci cally we are going to subtract SUB the operand at location 011002 from the operand at location 010112 and place the result at location 011112 Recall that a radix subtraction is realized by forming the two s complement of the subtrahend here the operand at location 011002 and adding it to the minuend the operand at location 010112 Further the easiest way to generate the radix complement of a signed number is to add one to its diminished radix complement or ones compemenb Figure 28 shows what happens Note that while the result 010101012 will be stored at location 011112 it will be invalid because over ow has occurred denoted by VF set to quot1 Note also that CF the carryborrow ag is cleared to 0quot due to its interpretation here as a borrow ag recall that following a subtract operation CF is set to the complementof the carry out of the sign position which in this case was quot1 A borrow ag of 0 following a subtract operation essentially means that no borrow is propagated fonNard Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introductmn ta ngxtal swam Design Page 14 Sub 10101010 701010101 10 10 10 10 10 10 1010 1 01010101 rrai m Before We eave an fast brock of Code yet anotner ques uon nat rnrnd 5 How n S ourd error Condmons We over ow be nand ed AS one rnrgnt UeSS We WM need Sorne new rnStrucUonS tnat aHoW US to test tne State of ne venous Condmon Codes nere VF 1 E 8 Q 8 m g E g u m 3 g 9 m 3 2 9 g z a o 1 n exce tron nand er rf an error has occurred Before We frnrsn an cnapter We WrH earn noW to rrnp ernent Sucn Condmonar transfer of contror rnstructrons The Max rnStrucuon rn our snort program HLT Srrnpry teHs our computer to Stop execuung Once the program hag stopped We 11112 3st 2ngme Wxsdam 7 Supplemenml Tex 2001 by D G Meyer Introduction to Digital System Design could presumably look at the contents of each location to determine the results of the program execution What we should nd is the memory image depicted in Figure 2 8 note that memory location 010102 was unused by our example program and may contain a random value 25 Simple Computer Block Diagram Now that we know how our simple computer works we are ready to consider the functional blocks necessary to make it work Basically we want to build what appears to be a big state machine that performs the calculations just done by hand At a fundamental level there are two basic steps associated with the processing of each instruction The rst step is to read the instruction from memory called an instruction fetch cycle The second step is to extract the opcode and address elds from the instruction just fetched and perform the operation speci ed by the opcode on the data located at the speci ed address this step is referred to as an instruction execute cycle What are the basic functional blocks then that are necessary to implement the simple computer described here Clearly a memory unit for storing instructions and data is one of the major functional blocks necessary This memory unit needs to be capable of reading the contents of a speci ed location indicated on its address lines as well as writing a new value to a speci ed location Another major functional block needed is me that will keep track of which instruction is next in line to be executed In our simple computer the instructions are stored in consecutive memory locations starting at location 000002 What is needed is a pointer that keeps track of which instruction is next Because this block is nothing more than a binary counter we will call it the program counterPC Once it is fetched from memory a place is needed to temporarily stage an instruction while the opcode eld is decoded and the address field is extracted We can think of this block as a place to hold the instruction just fetched while it is being digested While more creative biologically inspired names for it are certainly possible we will simply call this functional block the instruction registerlR Little Bits of Digital Wisdom 7 Supplemental Text Page 15 instruction fetch cycle instruction execute cycle memory unit program counter PC instruction register IR 2001 by D G Meyer Introduction to Digital System Design Address Bus Figure 29 Simple computer core block diagram Next we realize the need for a functional block that performs the arithmetic and logical operations we have de ned in the simple computer s instruction set Not surprisingly this block is usually called an arithmetic logic unit or simply ALU Note that the accumulator A register and condition code bits CF NF VF ZF are part ofthe ALU Finally we realize that our simple computer needs a manager a functional block that orchestrates the activities of all the other functional blocks delineated above This managelquot is responsible for indicating whether a fetch or an execute cycle is to be performed and once an instruction is fetched for decoding the opcode eld of that instruction and telling the other blocks in the system what to do in order to execute it Because our simple computer s manager controls the sequencing of events that taken together constitute the completion of a machine instruction we often refer to the state machine part of the manager s personality as a microsequencer similar to perhaps but not to be confused with a micro managel And because decoding the opcode eld of the instruction is an essential part of the sequencing process we award our simple computer s manager the grand and glorious name instruction decoder and microsequencer IDMS This more extravagant sounding name helps prevent images of kicking bits around that might be associated with a manager think baseball Returning to the house analogy for a moment what we have just done is de ne the rooms of the structure or system we wish to Little Bits of Digital Wisdom 7 Supplemental Text Page 16 arithmetic logic unit AL U manager microsequ en cer IDMS 2001 by D G Meyer Introduction to Digital System Design build What we have not yet done however is interconnect the functional blocks into a working oor plan In order to do this we need an understanding of the traf c patterns here of address data and control information that need to ow among the various functional blocks Starting with the memory unit we note that a series of address lines tell which location is being accessed the collection of address lines is referred to as the address bus Recall that a bus is a set of signal lines that have a common purpose At the location in memory accessed data can be read output or written input the memory s data lines and the associated data bus must therefore be bi directional Further control signals need to be supplied to the memory unit that tell whether or not it is enabled to respond or selected and if enabled to respond whether it should perform a read operation or a write operation Next we realize that the program counter PC will supply the instruction address to memory during a fetch cycle and that the instruction register IR will be used to temporarily stage the instruction after it has been read from memory Further on an execute cycle the IR will supply the operand address to memory and the destination or source of the data in this transaction is the A register of the ALU Thus there are two potential sources of address information the PC and the IR on the address bus Since only one device can talk on the bus at a given instant in time we will need to provide each ofthese functional blocks with threestate outputcapability and it will be our manager s job to keep them from talking at the same time Further there are two potential destinations of data read from memory On a fetch cycle an instruction destined for the IR is read from memory On an execute cycle an operand destined for the ALU is read from memory alternately data in the ALU is destined for memory if an STA instruction is being executed Again we note the need for threestate buffers in all the functional blocks involved with driving the data bus Putting this all together the core of our simple computer is depicted in Figure 29 Left on their own however these functional blocks are incapable of doing anything intelligent let alone successfully executing instructions Hence the need for a manager the instruction decoder and microsequencer to tell each block Vlhat to do when As such the IDMS can aptly be thought of as the heart of Little Bits of Digital Wisdom 7 Supplemental Text Page 17 address bus bi direction al threestate output capability 2001 by D G Meyer Introduction to Digital System Design Page 18 the machine The simple computer augmented with an IDMS is shown in Figure 2 10 Address Bus Figure 210 Complete simple computer block diagram We now have a complete oor plan for our house that we have speci ed in a topdown fashion Before actually building it though let s make sure we understand how the rooms work together 26 Instruction Execution Tracing To get a better idea of how the various functional blocks of our simple computer work in concert to process instructions we will return to our short program of Table 2 2 and use a technique called instruction tracing to help us visualize the ow of information On a cyclebycycle basis we will examine the address and data paths as well as the bit patterns in each register for the rst three instructions of this short program Recall that we used the term microsequencer because there is a sequence of events associated with processing an instruction here a fetch cycle followed by an execute cycle instruction tracing Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design Page 19 The instruction trace worksheet in Figure 211 sets the stage for this exercise which shows the initial state of the machine after START is pressed Note that there are several things we will keep track of as our machine executes the program In particular we will be monitoring what happens to the PC IR and A register as well as the contents of memory We will also practice naming each cycle as it occurs Address Bus Figure 211 Instruction trace worksheet for machine state after START is pressed prior to rst fetch cycle Recall that pressing the START pushbutton places the machine in a known initial state the PC is reset to 00000 and the state counter in the IDMS is set to fetch Note that the initial state of the IR and ALU may be random and that memory is initialized to the values indicated although at this point we don t care what is in the unused location 010102 or the locations where the results will be stored 011012 011112 During the rst fetch cycle shown in Figure 212 the instruction at memory location 000002 is read and placed in the IR As the IR is being loaded with the instruction the PC is incremented by one ie once the fetch of the current cycle is complete the PC is pointing to the next instruction to execute Note that the values in each register are those obtained afterthe fetch LDA cycle is complete Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design Page 20 00000 00001 00000 Address Bus Data Bu 00001011 Figure 212 Instruction trace worksheet for rst fetch cycle Address Bus Figure 213 Instruction trace worksheet for rst execute cycle Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design Page 21 Address Bus 00001 Address Bus 10101010 Figure 215 Instruction trace worksheet for second execute cycle Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design Page 22 00010 00011 00010 Address Bus Data Bu 001 01101 01101 Address Bus Data Bu 11111111 Figure 217 Instruction trace worksheet for third execute cycle Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design Page 23 During the rst execute cycle shown in Figure 213 the LDA 01011 instruction in the IR is executed When this cycle is complete the A register contains the contents of memory location 010112 ie the value 101010102 Note also that the NF is set to 1 and ZF is cleared to 0 The execute LDA cycle does not however affect the contents of any memory location nor does it change the contents of IR or PC condition code bits CF and VF are also unaffected We are now ready for the second fetch cycle fetch ADD shown in Figure 214 Here the instruction at memory location 000012 is fetched and placed into the IR and as that occurs the value in the PC is incremented by one The results of executing the ADD instruction are shown in Figure 215 Here the contents of memory location 011002 ie the value 010101012 are added to the value previously loaded into the A register A result of 111111112 is obtained along with condition code bits CF NF 1 ZF and VF This brings us to the third fetch cycle fetch ST of our tracing example shown in Figure 216 Here the instruction at memory location 000102 is fetched and placed into the IR and as that occurs the value in the PC is incremented by one The results of executing the STA instruction are shown in Figure 217 Here the contents of the A register are stored at the memory location indicated in the instruction s address eld 011012 When the execute STA cycle is complete then memory location 011012 contains the value 111111112 Note however that the A register as well as the condition code bits are unchanged Several observations are in order First all of our simple computer s fetch cycles are identical ie they are independent of the instruction opcode In fact this has to be the case since our machine basically knows nothing about the instruction being fetched until it is placed in the IR Second it may appear strange that our simple computer is incrementing the value in the PC on the same cycle that it is being used as a pointer to memory Another way to say this is that the increment of PC is overlapped with the fetch of the instruction The overlapped reason this can happen will become apparent when we start implementing each functional block in the next section For now though suf ce it to say that because each register will be implemented using edgetriggered ip ops the same clock edge that causes the IR to load the instruction being fetched also causes the PC to increment The IR though will be loaded with the value on the data bus prior to the clock edge while the value output by the PC driving the address Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design bus will change after the clock edge thus facilitating the desired overlap This is an important point that we will revisit several times before the end ofthis chapter One nal suggestion before we move to the bottomup phase of our simple computer design process Practice the instruction tracing process outlined in this section on other code segments to become more familiar with what happens when as each instruction is fetched and executed As we say in the education industry this is a good test question GTQ 27 BottomUp Implementation of Simple Computer Armed with a thorough understanding of how our simple computer works we are now ready to start building it from the bottomup In practice the preferred approach is to implement and test each block as it is designed Then when we put the various functional blocks together we have a much better chance of the entire system working the rst time 271 Memory The block we will start with is memory Although most of the time we would simply choose a memory chip of appropriate size and speed a knowledge of what s under the hood is essential to understanding how the various functional blocks of our simple computer work together First some terminology Normally we think of memory as an entity that from the computer s perspective can be read or written In read mode the memory unit simply outputs on its data bus lines the contents of the location indicated on its address bus inputs ln write mode the memory unit stores the bit pattern present on its data bus lines at the location indicated on its address bus inputs The correct acronym to describe such a readwrite memory is RWM Despite valiant efforts the name RWM never caught on Instead it is more popular to refer to these devices as random access memories or RAMs sonamed because any random location can be accessed in the same amount of time not because something random is read after a given value is written The speci c type of RAM we wish to concentrate on here is static RAM or SRAM This is in contrast to dynamic RAM DRAM which Little Bits of Digital Wisdom 7 Supplemental Text Page 24 good test question static RAM SRAIW dynamic rum DRAM 2001 by D G Meyer Introduction to Digital System Design Page 25 requires constant refreshing to retain information In DRAM data is stored as a charge on a capacitor since the charge dissipates over time it must be periodically refreshed SRAM consists of a collection of D latches that will retain data without the need for refreshing as long as power is applied Once power is turned off however all volatile information previously stored in the SRAM is lost this is referred to as mm a volatile memory In addition to address and data bus connections where for our simple computer the address bus is 5bits wide and the data bus is Sbits wide an SRAM needs three control signals First an SRAM needs an chip mm overall enable typically called a chip select CS or chip enable CS CE This enable signal is needed to differentiate among multiple SRAMs or as we will see later in this chapter between m ory and Millimenable inputoutput devices Second an SRAM needs an output enable OE 0E signal which provided the SRAM is selected turns on a serie of threestate buffers that drive the data from the addressed location out onto the data bus Finally an SRAM needs a write enable WE signal which if the SRAM is selected opens the row of latches associated with the addressed location and allows it to take on the value presented to the SRAM on the data bus wn39te mable at The basic building block of an SRAM is a memory cell such as the one depicted in Figure 218 consisting of a Dlatch and a threestate buffer When the select SEL signal is asserted the threestate buffer is enabled placing the data stored in the latch on the cell s OUT line When both SEL and WR are asserted the latch opens and accepts the data present on the IN line by virtue of asserting the latch enable or C input of the Dlatch When WR is negated the latch closes and retains the new value N W om l u q our E SEL SEL C W WR D Figure 218 SRAM cell adapted from Wakerly A complete SRAM can be constructed by combining an array of memory cells with a large decoder plus some additional logic The internal structure of an eight location 4bit wide or 8x4 SRAM is shown in Figure 219 Note that the number of address lines needed is log2numberoflocatlons here log28 3 Stated another way the number of locations in an SRAM is 2 where n is the number of Little Bits ofDigital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design Page 26 address lines A location in the SRAM corresponds to a row of memory memory cells to select a particular row an nto2n binary decoder is location needed DIN DlN2 DlNl DINO J39 l lN 0m lN Ml 34078 decoder lN OUT W our lN our DOUT3 DOU 392 DOUTl DOU TD 2quot x b RAM AD In address input An 1 DlNU DOUTU dzila mm DOD dam lllplll outputs Dlel mourn1 cnmml mpm 0E WE Figure 219 SRAM internal structure and symbol adapted from Wakerly Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design Page 27 kilo mega giga tera bi gubyte In addition to a decoder some logic is needed to qualify the actions associated with the OE and WE signals based on the assertion of CS the overall chip enable When WE is asserted in conjunction with CS the data present on the DIN pins DIN3 DINO is written at the location specified on the address lines note that the operation completes upon negation of the WE signal When OE is asserted in conjunction with CS the data output by a given row is routed to the threestate buffers that drive the external data lines Since the read and write operations are mutually exclusive however there is usually no need for separate data input and output lines Instead the data input and output lines are tied together and bidirec 0nal connected to the rest of the system using a tildirectional data bus dumb Such a configuration is shown in Figure 220 Note that an additional buffer is used to receive the incoming data during a write operation to reduce the load seen by the entity driving the bus 7 l l l i N i N i i SEL SEL SEL WR WR WH WE g A WW1 DIOS DIOZ DlOl DKOD Figure 220 SRAM bidirectional data bus adapted from Wakerly Little Bits afDigital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design Page 28 Before moving on a few notes concerning memory timing are in order Because an SRAM read operation is a purely combinational function the order in which the address and control signals CS and OE are asserted is of no consequence As we will see in Chapter 5 though critical each of these signals represents a critical timing path with respect to timingputh receiving valid data from memory on a read cycle tAA is the address access propagation delay time tcs is the chip select access time and M tOE is the output enable access time When interfacing an SRAM to a tcs computer all ofthese read paths need to be analyzed tOE Since a D latch is used to store each bit of data in an SRAM the timing relationship between the information on the address and data buses as well as the requisite control signals CS and WE is more stringent than for a read cycle In particular the address information needs to be stable and the chip select CS needs to be asserted for some time taV before WE is asserted opening the set of latches tCW associated with the selected location Also the information supplied rm to the SRAM on the data bus must be stable tsErUP prior to the tmm negation of the WE signal and MOLD following the negation of the WE signal These setup and hold timing parameters will be given speci c names in Chapter 5 The consequence of violating the data setup or hold timing speci cations of an SRAM or of not asserting the WE control signal for a suf cient period of time is the possibility of metastable metastable behavior All of these write related timing parameters behavior need to be analyzed when interfacing an SRAM to a computer Returning to our simple computer we note that by simply doubling the width of the SRAM depicted in Figure 2 19 from 4 bits to 8 bits and quadrupling the length from 8 locations to 32 locations as well as adding the bidirectional data bus interface shown in Figure 2 20 we will have the exact structure of SRAM needed The only difference is MSL the unique names we will use for our simple computer s memory MOE control signals MSL for the memory select signal MOE for the MWE memory output enable and MWE forthe memory write enable 272 Program Counter The next functional block we wish to address is the program counter PC Basically this is nothing more than a 5bit binary up counter with an asynchronous reset and threestate outputs The asynchronous reset ARS will be connected to the START ARS pushbutton so that the rst instruction fetched is from location 000002 There are two other control signals needed one that enables the PC to increment by one when a lowtohigh positive edge of the system Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design Page 29 CLOCK signal occurs which we will call PCC and one that turns on FCC the threestate buffers that gate the value in the PC onto the address POA bus which we will call POA Note that if PCC is negated while a positive CLOCK edge occurs the program counter should simply retain its current state To document the design of each functional block we will present an ABEL ABEL Advanced Boolean Expression Language source le The ABEL source le for the program counter module is shown in Table 2 3 Table 23 Program counter module MODULE pc TITLE Program Counter Module DECLARATIONS CLOCK pin PCOPC4 pin istype regDbuffer PCC pin quot PC count enable POA pin quot PC output on address bus tristate enable ARS pin quot asynchronous reset connected to START EQUATIONS quot retain state count up by 1 PCOd PCCampPCOq PCCampPCOq PC1d PCCampPC1q PCCampPC1q PCOq PC2d PCCampPC2q PCCampPC2q PClqampPCOq PC3d PCCampPC3q PCCampPC3q PC2qampPC1qampPCOq PC4d PCCampPC4q PCCampPC4q PC3qampPC2qampPC1qampPCOq PCOPC4oe POA PCOPC4ar ARS PCOPC4clk CLOCK Examining the source le we see that when PCC is negated the next state is simply the current state When PCC is asserted the equations for a synchronous 5bit binary up counter determine the next state Assertion of POA causes the threestate buffers associated with each register bit to be enabled and assertion of ARS causes each ip op comprising the PC to be asynchronously reset Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design Page 30 273 Instruction Register The instruction register IR has a very simple mission temporarily hold stage the instruction fetched from memory so that it can be peeled apart and executed As such it is simply a series of D ip ops with two control signals The rst control signal which we will call IRL enables the instruction register to be loaded with the instruction read from memory the load should occur on the positive edge of the IRA system CLOCK The second control signal which we will call IRA turns on the threestate buffers of the lower 5bits of the IR to gate the address eld ofthe instruction onto the address bus IRL Table 24 Instruction register module MODULE ir TITLE Instruction Register Module DECLARATIONS CLOCK pin quot IR4IRO connected to address bus quot IR7IR5 supply opcode to IDMS IROIR7 pin istype regDbuffer DBODB7 pin quot data bus IRL pin quot IR load enable IRA pin quot IR output on address bus enable EQUATIONS quot retain state oa IROIR7d IRLampIROIR7q IRLampDBODB7 IROIR7clk CLOCK IROIR4oe IR5IR7oe IRA 111 END Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design Several items in the IR module source le shown in Table 2 4 deserve explanation First when IRL is negated note that the IR simply retains its current state Second note that unlike the PC there is no need to asynchronously reset the IR when the START pushbutton is pressed since its random initial value is of no consequence Finally note that IRA only controls the threestate outputs associated with the lower 5bits of the IR and that the three state buffers of the upper 3bits ie the opcode bits are always enabled The reason the threestate buffers associated with the upper 3bits are always enabled is that they are connected directly to the IDMS module ie they do not drive a bus Recall that the IDMS uses the opcode bits to determine which system control signals are asserted on the next cycle when the instruction is executed 274 Arithmetic Logic Unit As mentioned earlier the arithmetic logic unit ALU is sonamed because it performs the arithmetic add subtract etc and logical Boolean operations de ned by the instruction set A real ALU performs a wide range of arithmetic and logical functions on operands stored in either registers or in memory Fortunately our ALU is relatively simple it performs four different functions on a single register which we have called the accumulator or A register and sets four condition code bits or ags based on the result obtained As such only four control signals are needed an overall enable which we will call ALE two function select lines which we will call ALX and ALY and a threestate output enable for gating the value in the A register onto the data bus which we will call AOE The data bus interface must be bi directional in order to input data supplied by memory on LDA ADD SUB and AND operations and to output data to memory for STA operations The condition code bits CF NF VF ZF are output directly to the IDMS we will see how these ags can be used to implement conditional transfer of control instructions later The ABEL source le for the simple computer ALU is shown in Tables 2 5 2 6 and 2 7 Referring rst to the declaration section Tables 2 5 and 2 6 we note that signals used for internal purposes are declared as nodes These include the carry bits and the combinational ALU outputs In the declarations that continue in Table 2 6 the least signi cant bit carryin CIN is de ned as ALY Noting that ALY is O for ADD and 1 for SUB we realize this is exactly what is needed to add one to the diminished radix complement of the subtrahend to obtain the radix complement when performing a SUB operation Little Bits of Digital Wisdom 7 Supplemental Text Page 31 arithmetic and logical operations ALE ALY condition code bits nodes 2001 by D G Meyer Introduction to Digital System Design Page 32 Table 25 Declarations section ofALU module MODULE alu TITLE ALU Module quot 8bit 4function ALU with bidirectional data bus quot ADD Q7QO lt Q7QO DB7DBO quot SUB Q7QO lt Q7QO DB7DBO quot LDA Q7QO lt DB7DBO quot AND Q7QO lt Q7QO amp DB7DBO quot OUT Value in Q7QO output on data bus DB7DBO quot AOE ALE ALX ALY Function CF ZF NE W quot quot 0 1 0 0 X X X X quot 0 1 0 1 X X X X quot 0 1 1 0 X X quot 0 1 1 1 AND x x quot 1 0 d d OUT quot 0 0 d d ltnonegt u quot X gt flag affected gt flag not affected quot Note If ALE 0 the state of all register bits should be retained DECLARATIONS CLOCK pin quot ALU control lines enable amp function select ALE pin quot overall ALU enable AOE pin quot data bus tristate output enable ALX pin quot function select ALY pin quot Carry equations declare as internal nodes CYOCY7 node istype com quot Combinational ALU outputs D flipflop inputs quot Used for flag generation declare as internal nodes ALUOALU7 node istype com quot Bidirectional 8bit data bus also accumulator register bits DBODB7 pin istype regdbuffer quot Condition code register bits CF pin istype regdbuffer quot carry flag VF pin istype regdbuffer quot overflow flag NF pin istype regdbuffer quot negative flag ZF pin istype regdbuffer quot zero flag Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design Page 33 Table 26 Continuation of ALU source le declarations section quot Declaration of intermediate equations quot Least significant bit carryin 0 for ADD 1 for SUB gt ALY CIN ALY quot Intermediate equations for addersubtractor SUM SOS7 quot selected when ALX 0 DBOpin DB1pin DB2pin ALY DB3pin ALY ALY DB4pin ALY ALY DB5pin ALY DB6pin ALY DB7pin ALY mmmmmmmm lmU39lbhbuNHO u u u u u u u do mm thud aaaaaaaa mmmmmmmm O lt LA U w 4 quot Intermediate equations for LOAD and AND quot selected when ALX 1 H ALYampDBOpin ALYampDB1pin ALYampDB2pin ALYampDB3pin ALYampDB4pin ALYampDB5pin ALYampDB6pin ALYampDB7pin ALYampDBOqampDBOpin ALYampDB1qampDB1pin ALYampDB2qampDB2pin ALYampDB3qampDB3pin ALYampDB4qampDB4pin ALYampDB5qampDB5pin ALYampDB6qampDB6pin ALYampDB7qampDB7pin H H H H H H H H H H dammle o H H H II kk kk H Intermediate equations for the full adder outputs used for the ADD and intermediate SUB functions as well as the logical functions here LDA and AND equations are shown in Table 26 Note that the sole purpose of these intermediate equations is to simplify the task of writing the ALU equations One can think of these as simply de nitions since they are part of the declaration section of symbols that will be used in higher level equations The real equations start in Table 27 First are the carry equations that implement a simple ripple addersubtractor Next are the combinational equations that generate the ALU outputs based on the intermediate equations de ned in Table 26 The data bus equations appear next note that if ALE is negated the A register retains its current state Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design Page 34 Table 27 Equations section ofALU source le EQUATIONS quot Ripple carry equations CY7 is COUT CYO DB 0qampALYDBOpin DBOqampCIN ALYDBOpinampCIN CYl DB1qampALYDB1pin DB1qampCYO ALYDB1pinampCYO CY2 DB2qampALYDB2pin DB2qampCY1 ALYDB2pinampCYl DB3 CY3 DB3qampALYDB3pin ALYDB3pinampCY2 CY4 DB4qampALYDB4pin DB4qampCY3 DB5 ALYDB4pinampCY3 ALYDB5pinampCY4 ALYDB6pinampCY5 ALYDB7pinampCY6 qampALYDB5pin DB5qampCY4 CY6 DB6qampALYDB6pin DB6qampCY5 CY7 DB7qampALYDB7pin DB7qampCY6 kk kkk quot Combinational ALU equations ALX ALUO ALXampSO ALUl ALXampSl ALXampL1 ALU2 ALXamp52 ALXampL2 ALU3 ALXampS3 ALXampL3 ALU4 ALXampS4 ALXampL4 ALU5 ALXampS5 ALXampL5 ALU6 ALXampSG ALXampL6 ALU7 ALXampS7 ALXampL7 quot Register bit and data bus control equations DBODB7d ALEampDBODB7q ALEampALUOALU7 DBODB7Clk CLOCK DBODB7oe AOE quot Flag register state equations CFd ALEampCFq ALEampALXampCY7 ALY ALXampCFq CFclk CLOCK ZFd ALEampZFq ALEampALU7ampALU6ampALU5ampALU4ampALU3ampALU2ampALU1ampALUO ZFclk CLOCK NFd ALEampNFq ALEampALU7 NFclk CLOCK VFd ALEampVFq ALEampALXampCY7 CY6 ALXampVFq VFclk CLOCK END Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design Last but not least are the equations that govern the four condition code bits All of these ags retain their current state if ALE is negated The carry ag CF and over ow ag VF are only affected by the ADD and SUB instructions For ADD the CF bit is set to the carry out of the most signi cant position here CY7 for SUB the CF bit is interpreted as a borrow and is therefore set to the complement of the carry out of the sign position The VF bit is simply the XOR ofthe carry in to the sign bit CY6 with the carry outofthe sign bit CY7 The negative ag NF and zero ag ZF are affected by all four functions implemented by our ALU The NF bit is simply the sign bit ALU7 of the result generated by the ALU while the ZF bit is set to 1 ifall the ALU result bits are zero Before moving on to the nal block of our simple computer design there is an important practical point worth noting All of the functional blocks designed thus far the memory PC IR and ALU can be independently implemented or simulated and tested as well as debugged before they are all assembled together into a completed computer Independent testing and debugging of each functional block in fact is an important aspect of the topdown bottomup strategy we have espoused in this chapter 275 Instruction Decoder and Microsequencer As described previously there are two basic steps involved with processing each instruction the combination of which is referred to as a microsequence During a fetch cycle the instruction pointed to by the PC is read from memory and loaded into the IR the PC is incremented by one as the instruction is loaded During the ensuing execute cycle the instruction staged in the IR is peeled apart into an opcode eld and an operand address eld the opcode eld indicates the operation to be performed using data obtained from or destined for the memory location speci ed by the address eld The functional block that orchestrates the sequencing of these activities is called the instruction decoder and microsequencer IDMS Since in this initial version of our simple computer there are only two different kinds of cycles etch and execute a single ip op can be used as a state counter SQ In reality this state counter is simply a singlebit binary counter ie it simply toggles between 0 and 1 Note that the state counter must be placed in he fetch state when START is pressed therefore it makes sense to assign the reset state Little Bits of Digital Wisdom 7 Supplemental Text Page 35 independent testing and debugging stnte counter S Q toggles 2001 by D G Meyer Introduction to Digital System Design Page 36 of the SQ ip op SQO to the fetch cycle and the set state of the SQ ip op SQ1 to the execute cycle V th the structure of the state counter established the next step is to determine which control signals of the functional blocks designed previously need to be asserted when SQO fetch and SQ1 execute To accomplish this we will need to refer back to each of the previous subsections on the design of the individual functional blocks as well as the instruction tracing worksheets completed previously Referring again to Figure 212 we note that the following signals need to be asserted to complete a fetch cycle First to gate the value in the PC onto the address bus the signal POA needs to be asserted by the IDMS To read the instruction the memory needs to be selected MSL asserted and its data bus output enabled MOE asserted To load the instruction read from memory into the IR the signal lRL needs to be asserted Finally to increment the PC as the instruction is loaded the signal PCC needs to be asserted A total of ve system control signals therefore needed to be asserted by the IDMS during a fetch cycle when SQO POA MSL MOE IRL and P00 The control signals that need to be asserted during an ALU function execute cycle ie LDA ADD SUB AND operation can be inferred from Figure 213 First to gate the operand address staged in the IR onto the address bus the signal IRA needs to be asserted by the IDMS To read the operand the memory needs to be selected MSL asserted and its data bus output enabled MOE asserted To perform the operation speci ed by the instruction opcode supplied to the IDMS from the upper 3bits of the IR ALE needs to be asserted along with the prescribed combination of ALX and ALY based on the ALU design documented in Table 25 The store A STA instruction execute cycle is similar but notably different than an ALU function execute cycle Here the address supplied to memory from the IR upon assertion of lRA speci es the destination for the data in the A register To complete the write to memory it needs to be selected MSL asserted and write enabled MWE asserted To gate the data in the A register onto the data bus AOE needs to be asserted A total of four control signals need to be asserted then to execute a store A STA instruction lRA MSL MWE and ACE Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design Page 37 A succinct summary of all the system control signal assertions is provided in Table 28 Note that for the sake of clarity signal assertions are denoted using H signals that are either negated or don t care are left blank By way of contrast the control signal negations that are effected by execution of the HLT halt instruction are denoted using Table 28 System control table Decoded Instruction l Lu State Mnemonic g g The ABEL source le for the simple computer s IDMS module is shown in Tables 29 and 210 Referring rst to the declarations listed in Table 29 we nd decoded opcode de nitions using the instruction mnemonics as pseudonyms for the corresponding opcode bit patterns and decoded machine state de nitions 80 for fetch S1 for execute The purpose of de ning an intermediate equation for each opcode combination is simply to make the job of writing the system control equations that appear in Table 210 easier Perhaps if we were more clever we might have used the name fetch instead of SO and execute instead of S1 to help make the subsequent equations a bit more clear albeit more cumbersome to write Continuing with the IDMS equations in Table 210 we discover three basic components the state counter the runstop ip op and the quotquot1 01 system control equations Looking rst at the state counter we note ip op that if the machine RUN enable is high ie the machine is running the state counter ip op merely toggles each time a positive CLOCK edge occurs If RUN is negated SQ is reset to 0 Le the fetch state Pressing the START pushbutton also resets SQ to the fetch state Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design Page 38 Table 29 Declarations section of IDMS module MODULE idms TITLE Instruction Decoder and Microsequencer DECLARATIONS CLOCK pin START pin quot asynchronous START pushbutton 0P0OP2 pin quot opcode bits input from IR5IR7 quot State counter SQ node istype regDbuffer quot RUNHLT state RUN node istype regDbuffer quot Memory control signals MSLMOEMWE pin istype com quot PC control signals PCCPOAARS pin istype com quot IR control signals IRLIRA pin istype com quot ALU control signals not using flags yet ALEALXALYAOE pin istype com quot Decoded opcode definitions LDA OP2ampOP1ampOP0 quot LDA opcode 000 STA OP2ampOP1amp 0P0 quot STA opcode 001 ADD OP2amp OP1ampOP0 quot ADD opcode 010 SUB OP2amp OP1amp 0P0 quot SUB opcode 011 AND OP2ampOP1ampOP0 quot AND opcode 100 HLT OP2ampOP1amp 0P0 quot HLT opcode 101 quot Decoded state definitions SD SQq quot fetch 1 SQq quot execute Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design Page 39 Table 210 Equations section of IDMS module EQUATIONS quot State counter SQd RUNqampSQq quot if RUN negated resets SQ SQclk CLOCK SQar START quot start in fetch state quot Runstop equivalent of SR latch RUNap START quot start with RUN set to 1 RUNar SlampHLT quot RUN is cleared when HLT executed quot System control equations MSL RUNqampSO SlampLDA STA ADD SUB AND MOE so SlampLDA ADD SUB AND MW39E SlampSTA ARS START PCC RUNqampSO POA o IRL RUNqampSO IRA SlampLDA STA ADD SUB AND AOE SlampSTA ALE RUNqampSlampLDA ADD SUB AND Ar SlampLDA AND ALY SlampSU39B AND END The runstop ip op is de ned next in Table 210 Here we note that pressing the START pushbutton asynchronously sets the RUN ip op thereby enabling our simple computer to start executing instructions Once set the RUN signal remains asserted until asynchronously reset through execution ofan HLT instruction We see how the RUN signal is used to enabledisable machine activity in the system control equations that follow Note that if RUN is high the system control signals are asserted according to the table in Table 28 as described previously For example MSL is asserted if a fetch cycle is being performed 80 high or an execute cycle is being performed 81 high of an LDA instruction an STA instruction an ADD instruction a SUB instruction or an AND instruction If RUN is low Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design however all of the pertinent system control signals are negated Note that it is only necessary to negate the system control signals responsible for causing the various functional blocks to change state ie it is not necessary to negate function select signals such as ALX and ALY nor is it necessary to negate threestate output enables This completes the bottomup phase of the design process for the initial version of our simple computer All of the ABEL code described in this section could be implemented using a single modestsize PLD The addition of a conventional memory chip would yield a working computer Before augmenting the instruction set with some useful extensions though let s take a closer look at system timing 28 System Timing Analysis When we designed the program counter in Section 272 there was an appearance of cheating speci cally of using the current value in the PC to access an instruction in memory while at apparently the same time telling the PC to increment This is an issue that deserves further scrutiny To gain a better understanding of the timing relationship among different activities within our computer we need to understand two basic hardwareimposed constraints The rst is that only one device functional block can drive a bus on a given bus cycle ie bus ghting must be avoided The second is that data can only pass through one edgetriggered ip op per cycle Thus it is not possible to load a value into a register and expect to use it have the value available on the register s outputs on the same cycle Given these constraints we are now prepared to examine in detail the sequence of activities that occur during a fetch cycle A qualitative timing diagram is provided in Figure 221 for this purpose by qualitative we mean that we re not interested in the exact number of nanoseconds between one signal assertion and another just the fact that there is a delay Depicted in this diagram is the sequencing that occurs as the machine nishes an execute cycle performs a fetch of the next instruction and subsequently proceeds to execute the instruction just fetched Our focus here is on the events that constitute a fetch cycle The rst thing to note is that since the functional blocks ofthe machine were designed using positiveedgetriggered flip ops the clock edges drive the machine from statetostate Thus a fetch cycle is the Little Bits of Digital Wisdom 7 Supplemental Text Page 40 bus ghting qualitative timing diagram clock edges 2001 by D G Meyer Introduction to Digital System Design Page 41 time between the clock edge that drives the machine from the previous execute cycle to the current fetch cycle and the subsequent clock edge that transitions the machine from the fetch cycle to an execute cycle Shortly after the first clock edge in Figure 221 then the control signals MSL MOE POA IRL and PCC are asserted the delay relative to the clock edge in generating these signals is due to the propagation delay of the state counter plus the delay associated with the system control equations see Table 210 Previous S1 Execute SO Fetch S1 Execute H l CLK MSL MOE POA IRL FCC Figure 221 Fetch cycle event timing relationship The assertion of POA causes the threestate buffers of the PC to turn on and drive its value onto the address bus The value on the address bus in conjunction with the MSL and MOE signal assertions causes the memory to drive the addressed instruction onto the data bus note that in most practical systems this constitutes a substantial part of the cycle time Provided the instruction is on the data bus at least tsgup of the D flipflop prior to the next clock edge it is successfully loaded into the IR because the IRL signal is asserted when that edge occurs Little Bits of Digital Wisdom Supplemental Text 2001 by D G Meyer Introduction to Digital System Design Page 42 While this may seem to be enough activity already we realize that a related housekeeping activity can be accomplished on this cycle as well incrementing the value in the PC so it points to the next instruction in preparation for the next fetch Again based on the use of edgetriggered flip ops in our design we note that the value on the data bus just prior to the clock edge that loads the IR determines the next state of the IR It follows then that we can use that same clock edge to drive the PC to its next state this is why PCC is also asserted during a fetch cycle Note that the PC state change will occur afterthe clock edge ie alter the instruction has been safely loaded into the IR This allows us to effectively overlap the load of the IR with the overlap increment ofthe PC on the same cycle We will make use of this same principle when we add some extensions to our machine later in this chapter One might ask at this point Could we have delayed the increment of the PC until the execute cycle In the initial version of our simple computer it would clearly be possible here the new value in the PC would be available shortly after the commencement of the fetch cycle thus enabling the correct instruction to be loaded into the IR the only consequence might be a small amount of additional propagation delay for the new value to become stable When we add subroutine linkage instructions to our computer however we will nd it useful to have the new value of the PC available during the rst execute cycle to serve as the return address for a subroutine call instruction In anticipation of this extension we will include the increment of the PC as an integral part ofthe fetch cycle 29 Simple Computer Extensions When we originally designed our instruction set we purposefully left two opcode bit patterns uncommitted The reason we did this was to provide room for expansion We will then add a pair of instructions at a time to our base instruction set The pairs we will add include inputoutput INOUT instructions transfer of control instructions JMPJZF stack manipulation instructions PSHPOP and subroutine linkage instructions JSRRTS 291 InputOutputlnstructions When we rst drew the big picture of our simple computer see inputport Figure 2 4 we included a switch input port and an LED output port amputpm As evident from the initial version of our instruction set we included no Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design provision for using these It nakes sense then to add instructions for providing our machine with the modern convenience of data input and output lO First we need to establish the destination that will be used for data input or read from the outside world as well as the source for data that will be output or written Given that our machine has but one register that participates in data transactions namely the A register it is the most likely candidate to serve as the destinationsource of data that is inputoutput respectively Thus our new IN instruction will function in a manner similar to an LDA instruction except the source of data will be the outside world and the address eld will be used as a pointer to an input device instead of to memory Similarly our new OUT instruction will function in a manner similar to an STA instruction except the destination of data will be the outside world and the address eld will be used as a pointer to an output device A name commonly used for this inputoutput strategy is accumulator mappedlO Second we need to establish how data will be communicated tofrom the ubiquitous outside world Basically a gateway is needed between the system data bus and the external input and output devices along with some new system control signals that enable a read IOR or a write IOW via this gateway Also a means of decoding the lO addresses typically called port or device numbers into individual device selects or enables is needed A diagram illustrating the placement of the lO block is provided in Figure 222 an ABEL source le for a speci c instance of this module is given in Table 211 m x m m m E 1 1 lt Figure 222 Block diagram ofsimple computer with lO Little Bits of Digital Wisdom 7 Supplemental Text Page 43 I 0R 10W port numbers device numbers 10 block 2001 by D G Meyer Introduction to Digital System Design Page 44 Table 211 Basic lO module MODULE io TITLE InputOutput Port 00000 DECLARATIONS data bus address bus input port output port DBODB7 pin istype com ADOAD4 pin INOIN7 pin OUTOOUT7 pin istype com IOR pin quot Input port read IOW pin quot Output port Write quot Port select equation for port address 00000 P5 lAD4amplAD3ampAD2amplAD1amplADO EQUATIONS DBODB7 INOIN7 DBODB7oe IORampPS OUTOOUT7 DBODB7 OUTOOUT7oe IOWampPS END Referring to the ABEL le we see that it contains a speci c port address decoding equation here for port address 000002 When the pattern on the address bus matches this value an IO transaction via this port address is enabled If an IN instruction is being executed assertion of the IOR signal by the IDMS causes the value on the IN pins INON7 to be gated onto the system data bus allowing it to be loaded into the A register If an OUT instruction is being executed assertion of the IOW signal causes the value on the data bus supplied by the A register to be gated to the OUT pins OUTOOUT7 There is a limitation however inherent in the IO port design shown in Table 211 the value output when an OUT instruction is executed is only active for a very short time speci cally the amount of time the IOW signal is asserted by the IDMS For devices such as light Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design Page 45 emitting diodes LEDs the brief assertion of IOW will not provide a satisfactory display A better solution is to latch the value sent to the output port and retain it until execution of a subsequent OUT instruction changes the value An lO module that provides a latched MUMquot output port is provided in Table 212 Here assertion of IOW in W Pmlw t conjunction with the proper port address opens a transparent latch which then assumes the new value sent on the data bus The latch closes retains its value when IOW is negated Table 212 Latched lO port MODULE iol TITLE InputOutput Port 00000 With Output Latch DECLARATIONS DBODB7 pin istype com quot data bus ADOAD4 pin quot address bus INOIN7 pin quot input port OUTOOUT7 pin istype com quot output port IOR pin quot Input port read IOW pin quot Output port Write quot Port select equation for port address 00000 P5 lAD4amplAD3ampAD2ampAD1ampADO EQUATIONS DBODB7 INOIN7 DBODB7oe IORampPS quot Transparent latch for output port OUTOOUT7 IOWampPSampOUTOOUT7 IOWampPSampDBODB7 END The augmented system control table for our simple computer plus lO is given in Table 213 Note that there are two new equations for IOR and IOW along with four equations that need to be updated for IRA AOE ALE and ALX The updated system control equations are given in Table 214 Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design Page 46 Table 213 System control table modi ed for IO Decoded Instruction State Mnemonic a E Lu 0 E Table 214 System control equations modi ed for IO quot System control equations IDMS MSL RUNqampSO SlampLDA STA ADD SUB AND MOE 0 SlampLDA ADD SUB AND MW39E SlampSTA ARS START PCC RUNqampSO POA SO IRL RUNqampSO IRA SlampLDA STAADD SUBAND IN OUT AOE SlampSTA OUT ALE RUNqampSlampLDA ADD SUB AND IN ALX SlampLDA AND IN ALY SlampSU39B AND IOR SlampIN IOW SlampOUT END Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design 292 Transferof Control Instructions Any program worth the silicon it runs on typically does more than execute straight line code Instead execution transfers to different parts of the program based on various conditions encountered Generically we refer to the instructions that allow program execution to jump around as transferof control instructions There are two basic types of transferofcontrol instructions If the address eld of the instruction contains the absolute address in memory at which execution should continue it is most often referred to as a jump instruction If the address eld instead represents the signed distance the next instruction is from the transferofcontrol instruction it is referred to as a branch There is not universal agreement on this nomenclature however see sidebar Jumps or branches that always happen are called unconditional those that happen only if a certain combination of condition codes exists are called conditional The addition of transferofcontrol instructions to our simple computer will require modi cations to the PC as well as to the IDMS Speci cally we will need to provide a mechanism for loading a new value into the PC to implement jumpstyle instructions or for adding a signed offset to the value in the PC to implement branchstyle instructions Here we will focus on the modi cations necessary to implement jumpstyle instructions An ABEL source le for the modi ed PC is provided in Table 2 15 Note that it is the same as the original PC see Table 2 3 except that a load from address bus function and associated control signal PLA has been added Recall that the new value with which the PC is to be loaded is staged in the IR and can therefore be conveniently transported to the PC via the address bus Little Bits of Digital Wisdom 7 Supplemental Text Page 47 struight line code trunsferofcontrol instructions jump instruction brunch instruction unconditionul conditionul PLA 2001 by D G Meyer Introduction to Digital System Design Page 48 Table 215 PC modi cations to support transferofcontrol instructions MODULE pc TITLE Program Counter DECLARATIONS CLOCK pin PCOPC4 pin istype regDbuffer PCC pin quot PC count enable PLA pin quot PC load from address bus enable POA pin quot PC output on address bus tristate enable ARS pin quot asynchronous reset connected to START quot Note Assume PCC and PLA are mutually exclusive EQUATIONS quot retain state load PCOd lPCCamplPLAampPCOq ll PLAampPCOpin PC1d PCCampPLAampPC1q PLAampPC1pin PCCampPC1q PCOq PC2d lPCCampPLAampPC2q PLAampPC2pin PCCampPC2q PClqampPCOq PC3d PCCampPLAampPC3q PLAampPC3pin PCCampPC3q PC2qampPC1qampPCOq PC4d lPCCampPLAampPC4q PLAampPC4pin PCCampPC4q PC3qampPC2qampPC1qampPCOq PCOPC4oe POA PCOPC4ar ARS PCOPC4clk CLOCK The system control table modi ed to include an unconditional jump instruction JMP along with a jump if zero ag set JZF instruction JMP is shown in Table 216 As its name implies the JZF instruction JZF causes a transferofcontrol to the address following the opcode if the zero ag ZF is set ie the result of the most recent ALU operation Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design Page 49 has generated a result of zero in the A register As it turns out this is a fairly popular condition to check in practical applications If the condition speci ed by a conditional jump instruction like JZF is not quot0011 1 10 1 met however nothing happens often called a no operation or NOP NOP execution merely continues with the instruction that follows In order to effect the load of the jump address the IDMS needs to know the state of the various condition code bits generated by the ALU The equations for IRA and PLA then will be a function of ZF for the new instructions added to the machine in Table 217 Table 216 System control table modified for transferof control instructions Decoded Instruction State Mnemonic MOE MWE PCC POA IRL IRA AOE ALE ALX ALY PLA 51 W Ale 7 L L D L A III H 51 JZF ZF Table 217 IDMS modi cations to support transferofcontrol quot System control equations IDMS MSL RUNqampS0 SlampLDA STA ADD SU39B AND MOE SO SlampLDA ADD SUB AND MWE SlampSTA ARS START PCC RUNqampSO POA SO IRL RUNqampSO IRA SlampLDA STA ADD SUB AND J39MP JZFampZF AOE SlampIl ALE RUNqampSlampLDA ADD SUB AND ALX SlampLDA AND ALY SlampSU39B AND PLA SlampJ39MP JZFampZF END Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design One could imagine at this point a number of other conditions that would be useful for determining whether or not a jump or branch should be taken In addition to a separate jump on condition instruction dedicated to each ag CF NF VF ZF there are various Boolean combinations of these ags that are of interest as well eg testing for greater than or less than or equal to All of these variations will be explored when we tackle the instruction set of a real microcontroller in the next chapter 293 Multiple Execute Cycle Instructions To this point all of the instructions we originally de ned or added to our simple computer required a single fetch cycle followed by a single execute cycle As the functions performed by an individual instruction become more complex however additional execute cycles become necessary On the surface this would appear to be a relatively straightfonNard extension accomplished by simply adding extra bits to the state counter in the IDMS along with a binary decoder to decode the various states Adding one additional bit to our original state counter would provide us with four possible states a fetch state 80 followed by three execute states 81 82 S3 The complication that arises is that despite this addition we want our original single execute state instructions to still execute in a single state Further we want any new instructions that require two execute states to consume only two execute states and new instructions that require all three execute states to consume exactly three execute states More succinctly we want our state counter to be able to accommodate variablelength execution cycles here from 1 to 3 One way this can be accomplished is by adding a synchronous reset capability to our now 2bit state counter For this purpose we will add a new signal RST to our system control table that when asserted causes the state counter to reset to zero when the next clock edge occurs In the system control table this signal will be asserted on the nal execute cycle of each instruction For single execute cycle instructions such as LDA STA ADD AND SUB the RST signal will be asserted during 81 the rst execute cycle ensuring that the next cycle will be a fetch For instructions requiring two execute cycles the RST signal will be asserted during 82 the second execute cycle Finally for threeexecutecycle instructions the RST signal will be asserted during 83 note that if RST is not asserted at this point the Little Bits of Digital Wisdom 7 Supplemental Text Page 50 Boolean combinations of ags S1 S2 S3 variablelength execution cycles synchronous reset 2001 by D G Meyer Introduction to Digital System Design Page 51 state counter will wrap around to zero automatically thus ensuring that the next cycle is a fetch regardless Table 218 IDMS modi cations for multiexecutecycle instructions declarations section MODULE idmsr TITLE Instruction Decoder and Microseguencer with MultiExecution States DECLARATIONS CLOCK pin START pin 0P0OP2 pin asynchronous START pushbutton opcode bits input from IR5IR7 quot State counter SQA node istype regDbuffer quot low bit of state counter SQB node istype regDbuffer quot high bit of state counter quot Synchronous state counter reset RST node istype com quot RUNHLT state RUN node istype regDbuffer quot Memory control signals MSLMOEMWE pin istype com quot PC control signals PCCPOAARS pin istype com quot IR control signals IRLIRA pin istype com quot ALU control signals ALEALXALYAOE pin istype com quot Decoded opcode definitions LDA OP2ampOP1ampOP0 quot opcode 000 STA OP2ampOP1amp 0P0 quot opcode 001 ADD OP2amp OP1ampOP0 quot opcode 010 SUB OP2amp OP1amp 0P0 quot opcode 011 AND OP2ampOP1ampOP0 quot opcode 100 HLT OP2ampOP1amp 0P0 quot opcode 101 quot Decoded state definitions SD SQBampSQA quot fetch state Sl SQBamp SQA quot first execute state S2 SQBampSQA quot second execute state S3 SQBamp SQA quot third execute state Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design Page 52 Table 219 IDMS modi cations for multiexecutecycle instructions equations section EQUATIONS quot State counter quot if RUN negated or RST asserted quot state counter is reset SQAd lRST amp RUNq amp lSQAq SQBd lRST amp RUNq amp SQBq SQAq SQAclk CLOCK SQBclk CLOCK SQAar START quot start in fetch state SQBar START quot Runstop equivalent of SR latch RUNap START quot start with RUN set to 1 RUNclk CLOCK RUNd RUNq RUNar S1ampHLT quot RUN is cleared when HLT executed System control equations MSL RUNqampS0 ll SlampLDA ll STA ll ADD ll SU39B ll AND E o m lll so SlampLDA ADD SUB AND MWE S1ampSTA ARS START PCC RUNqampS0 POA S0 IRL RUNqampS0 IRA SlampLDA STA ADD SUB AND AOE S1ampSTA ALE RUNqampS1ampLDA ADD SUB AND ALx SlampLDA AND ALY SlampSUB AND RST SlampLDA STA ADD SUB AND END The state counter modi cations necessary to accommodate multiple execute cycles are shown in Tables 218 and 219 Following conventional notation bit A of the modi ed state counter is the least signi cant bit and bit B is the most signi cant bit Note that if RUN is negated or RST is asserted the state counter is reset to 00 Pressing the START pushbutton also resets the state counter to zero Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design In the sections that follow we will see examples of instructions that require two or three execute states The system control tables for these new instruction sets will therefore include the RST signal 294 Stack Manipulation Instructions An important modern convenience that most real computers enjoy is a stack mechanism Stacks also referred to as lastin rstout LIFO data structures facilitate a number of capabilities including expression evaluation subroutine linkage and parameter passing While there are many variations on stack implementation the most common strategy is to place the stack contents in the uppermost portion of readwrite memory and add a new register to the machine that serves as a pointer to the top item on the stack Not surprisingly this register is called the stack pointer SP An augmented system block diagram illustrating the placement of the SP register in our simple computer is given in Figure 223 Address Bus Figure 223 Block diagram of simple computer with stack Little Bits of Digital Wisdom 7 Supplemental Text Page 53 lastin firstout LI F 0 expression evaluation subroutine linkage parameter passing stack pointer SP 2001 by D G Meyer Introduction to Digital System Design Since program growth or execution direction is toward increasing addresses starting in low memory it makes sense that stack growth should be toward decreasing addresses starting in high memory The stack grows as items are pushed onto it which means the SP register must decrement as it grows conversely as items are popped offthe stack and its size diminishes the SP register must increment At this point we realize there are two possible conventions that can be used as a stack pointer paradigm we can choose to have the SP register point to the top stack item or we can choose to have it point to the next available location The most commonly used convention and the one we will adopt here is to have the SP register point to the top stack item Based on this choice we realize that the initial value of the SP register needs to be one greater than the address in which the rst stack item is placed Because the SP register points to the top stack item it must be decremented in order to allocate space for a new item during a push operation If the stack starts in the uppermost location of memory for our simple computer location 111112 the SP register should be initialized to 000002 ie one greater than 111112 modulo 25 Stack growth and retraction based on this conventional convention is illustrated in Figure 224 Note that items popped off the stack are merely dealocated from the stack area not erased Based on an understanding of how the stack mechanism works we can now consider the design of the SP register module documented in Table 220 The rst thing we note is that the SP register is simply an updown binary counter with threestate output buffers and an asynchronous reset The IDMS then needs to supply the SP register with four control signals an asynchronous reset ARS an increment enable SPI a decrement enable SPD and a threestate buffer enable SPA that gates he value in the SP register onto the address bus We now have all the ingredients available to create two new stack manipulation instructions push the contents of the A register onto the stack PSH and pop the top stack item into the A register POP One possible application for such a pair of instructions is expression evaluation Here intermediate results of a calculation can be placed on the stack and retrieved when needed For example to evaluate the expression WX Y Z we could rst calculate the quantity Y Z and push it onto the stack next calculate the quantity WX and nally pop the stack and subtract that value from our running total Formal methods exist for transforming an arbitrarily complex parenthesized expression into post x form Little Bits of Digital Wisdom 7 Supplemental Text Page 54 execution direction stack growth stack convention top stack item next available location ARS SP1 SPD SPA stack manipulation instructions PSH POP postftx 2001 by D G Meyer Immdmm m ngxtal swam Design Page 55 11100 11101Mm 11110 11111 Addr mmquot M Mammy SP Reg39slel 1111 Addr Addr I39npquot nl Mammy Figure 224 Hustrauon of stack Add growth a pusmngfountemsomo the slack b poppmg these four temS off the stack Tap nlMemnry 11112 3st 2ngme Wxsdam 7 Supplemenml Tex 2001 byD G Meyer Introduction to Digital System Design Page 56 Table 220 Stack pointer module MODULE sp TITLE Stack Pointer DECLARATIONS CLOCK pin SPOSP4 pin istype regDbuffer SPI pin quot SP increment enable SPD pin quot SP decrement enable SPA pin quot SP output on address bus tristate enable ARS pin quot asynchronous reset connected to START quot Note Assume SPI and SPD are mutually exclusive EQUATIONS quot retain state incrementdecrement SPOd lSPIampSPDampSPOq ll SPIampSPOq SPDampSPOq SP1d lSPIampSPDampSP1q ll SPIampSP1qSPOq SPDampSP1qSPOq SP2d lSPIampSPDampSP2q ll SPIampSP2qSP1qampSPOq SPDampSP1qlSPlqamplSPOq SP3d lSPIampSPDampSP3q SPIampSP3qSP2qampSP1qampSPOq SPDampSP3qlSP2qamplSP1qamplSPOq SP4d lSPIampSPDampSP4q SPIampSP4qSP3qampSP2qampSP1qampSPOq SPDampSP4qlSP3qamplSP2qampSP1qampSPOq SPOSP4oe SPA SPOSP4ar ARS SPOSP4clk CLOCK Implementation of the PSH instruction requires two execute states Here the SP register must rst be decremented in order to allocate space for the new item given the convention we have adopted that SP points to the top stack item After the SP has been decremented it can be used as a pointer to indicate where in memory the contents of A should be stored Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design Page 57 For POP however the SP register is already pointing to the right place enabling the A register to be loaded with the contents of that location on the rst execute cycle The bookkeeping step of de allocating the item just popped off the stack accomplished by incrementing the SP register needs to follow which at rst glance Immacuth appears to require a second execute cycle Here though the same clock edge that is used to load the A register with the value pointed to by the SP register can be used to increment the SP register since its value will not change until after the load has safely completed The POP instruction then can be implemented using a single execute cycle Note the similarity between the overlap employed here and the overlap overlap ofthe PC increment used previously in the fetch cycle A modi ed system control table illustrating the addition of PSH and POP to our simple computer s instruction set is given in Table 221 Here only one of the instructions listed PSH requires a second execute state S2 the remaining instructions complete in a single execute cycle Note therefore that RST is not asserted until the S2 state of the PSH instruction while for the other instructions RST is asserted during the S1 state A modified ABEL source le for the IDMS that corresponds to this version of our instruction set is given in Table 222 Table 221 System control table modi cations for stack manipulation instructions Decoded Instruction State Mnemonic an 2 Lu 0 E Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design Table 222 IDMS modi cations for stack manipulation instructions quot System control equations MSL RUNqampSO SlampLDA STA ADD SUB AND POP S2ampPSH MOE S0 SlampLDA ADD SUB AND POP MWE S1ampSTA S2ampPSH ARS START PCC RUNqampS0 POA S0 IRL RUNqampSO IRA SlampLDA STA ADD SUB AND AOE S1ampSTA S2ampPSH ALE RUNqampSlampLDA ADD SUB AND POP ALX SlampLDA AND POP ALY SlampSUB AND SPI S1ampPOP SPD S1ampPSH SPA S1ampPOP S2ampPSH RST SlampLDA STA ADD SUB AND POP S2ampPSH END Before adding our nal set of simple computer extensions some additional comments on PSHPOP are in order Virtually every computer that has a stack mechanism implements some variation of the basic pushpop instruction pair typically for each important register in the machine s architecture Other variations which would be particularly useful for performing expression evaluation on our simple computer include pop and add ie pop the stack and add that item to the contents of the A register pop and subtrac etc In fact instructions like pop and add are simple variations of the basic POP instruction and can be implemented with only minor modi cations to the ABEL source les given 295 Subroutine Linkage Instructions Another important modern convenience that most computers enjoy is a subroutine linkage mechanism which is the nal extension to our simple computer we will explore in this chapter A very effective way to provide this capability is to utilize a stack While there are other ways that subroutine linkage can be implemented in practice use ofa stack is attractive because it a allows arbitrary nesting of subroutine calls b provides a mechanism for passing parameters to subroutines 0 Little Bits of Digital Wisdom 7 Supplemental Text Page 58 p011 and add pop and subtract arbitrary nesting 2001 by D G Meyer Introduction to Digital System Design Page 59 allows recursion the ability of a subroutine to call itself and d allows recursion reentrancy the ability of a code module to be shared among quasi eenmmcy simultaneously executing tasks The two subroutinelinkage instructions we will add to our base instruction set are jump to subroutine JSR and return from subroutine RTS Generically we can simply refer to these as subroutine call and return instructions As can be seen from the subroutine in action illustration Figure 225 one of the key things the call instruction must do is establish a return path to the calling program hence the name linkage Placing the calling program s return address return address on the stack affords nesting of subroutine calls ie one subroutine calls another which then calls another etc MAIN start of main program JS R S U BA next instruction HLT end of main program SUBA stzt 0fsubr0utineA J J S R S B B next ingtruction RTS end 0fsubr0utineA SU BB start of subroutine B K RTS end of subroutine B Figure 225 Subroutine linkage in action Note that the return address is simply the address of the instruction that follows the JSR Recalling that the PC is automatically incremented as part of the fetch cycle we realize that the desired return address has already been calculated The value in the PC simply needs to be pushed onto the stack when a JSR instruction is executed Conversely when a return from subroutine RTS instruction is executed the top stack item needs to be popped off the stack and placed into the PC Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design Page 60 These observations indicate that in order to add JSR and RTS instructions to our machine the PC register needs to be modi ed Speci cally a bidirectional interface to the system data bus needs to be added so that the value in the PC can be pushedpopped Two new control signals need to be added to the PC for this purpose PLD for loading the PC with the value on the data bus popped off the stack when an RTS instruction is executed and POD for gating the value in the PC onto the data bus so that it can be pushed onto the stack when a JSR instruction is executed A block diagram depicting the modi ed system is given in Figure 226 An ABEL le for the modi ed PC is given in Table 223 Address Bus Figure 226 Block diagram of simple computer with subroutine linkage mechanism Upon examining the block diagram of the modi ed system one might initially be disturbed by the fact that the width ie number of bits of the PC register does not match that of data bus andor memory here the PC register is only 5 bits wide while the memory is 8 bits wide In practice though this is of no consequence we will simply use the lower 5 bits of the addressed memory location to store the value of the PC when it is pushed onto the stack In most real computers there is usually a better match between the PC and memory width eg 32 bit address space and 32bit wide memory Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design Page 61 Table 223 Modi ed PC for subroutine linkage MODULE pcr TITLE Program Counter with Data Bus Interface DECLARATIONS CLOCK pin PCOPC4 node istype regDbuffer quot PC register bits ABOAB4 pin quot address bus 5bits Wide DBODB7 pin quot data bus 8bits Wide PCC pin quot PC count enable PLA pin quot PC loa from address bus enable PLD pin quot PC load from data bus enable POA pin quot PC output on address bus tristate enable POD pin quot PC output on data bus tristate enable ARS pin quot asynchronous reset connected to START quot Note Assume PCC PLA and PLD are mutually exclusive EQUATIONS quot retain state load from AB load from DB PCOd PCCampPLAampPLDampPCOq PLAampABOpin PLDampDBOpin quot increment PC1d PCCampPLAampPLDampPC1q PLAampAB1pin PLDampDB1pin PCCampPC1gPCOg PC2d PCCampPLAampPLDampPC2q PLAampAB2pin PLDampDB2pin PCCampPC2qPC1qampPCOq PC3d PCCampPLAampPLDampPC3q PLAampAB3pin PLDampDB3pin PCCampPC3qPC2qampPC1qampPCO PC4d PCCampPLAampPLDampPC4q PLAampAB4pin PLDampDB4pin PCCampPC4qPC3qampPC2qampPC1qampPCOq 9 ABO AB4 PCOPC4 q DBO DB4 PCOPC4 q quot Output logic zero on upper 3bits of data bus DB5DB7 0 ABOAB4oe POA DBODB7oe POD PCOPC4ar ARS PCOPC4clk CLOCK END Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design Page 62 We are now ready to outline the steps needed to execute the JSR and RTS instructions First we realize there are two fundamental steps associated with performing a JSR a push the return address the value h the PC register onto the stack and b jump to the location indicated by the instruction s address eld Step a is accomplished in a manner similar to the PSH instruction described in Section 294 during the rst execute cycle the stack pointer is decremented during the second execute cycle the new item here the PC is written to the location pointed to by the SP register Step b is accomplished the same way as the unconditional jump instruction JMP described in Section 293 the location at which execution of the subroutine is to commence is simply transferred from the IR to the PC via the address bus Adding it all up we nd that a total of three execute states are needed to perform a JSR instruction By way of contrast execution of an RTS instruction requires only a single fundamental step pop the return address off the stack and place it into the PC register This is really not much different than the basic pop instruction POP described in Section 294 except here the destination is the PC rather than the A register Also because RTS is merely a pop PC operation it can be performed in a single execute cycle just like the pop A POP instruction Table 224 System control table modi cations for subroutine linkage instructions Dec Instr Lu State Mnem aquot o E E Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design Page 63 Table 225 IDMS modi cations for subroutine linkage instructions quot System control equations MSL RUNqampSO ll SlampLDA ll STA ll ADD ll SU39B ll AND RTS S2ampJSR MOE S0 SlampLDA ADD SUB AND RTS MWE S1ampSTA SZampJSR ARS START PCC RUNqampS0 POA S0 PLA S3ampJSR POD S2ampJSR PLD S1ampRTS IRL RUNqampS0 IRA SlampLDA STA ADD SUB AND AOE S1ampSTA S2ampJSR ALE RUNqampSlampLDA ADD SUB AND RTS ALX SlampLDA AND RTS ALY S1ampSUB AND SPI S1ampRTS SPD S1ampJSR SPA SlampRTS SZampJSR RST SlampLDA STA ADD SUB AND RTS S3ampJSR END The system control table modi ed to include the new JSR and RTS instructions is shown in Table 224 An ABEL le for the modi ed IDMS is given in Table 2 25 Note that since the JSR consumes all three execute cycles available it technically doesn t matter whether or not the RST signal is asserted during 83 since the 2 bit state counter will automatically wrap around to 80 when the next clock edge occurs It s probably a good idea though to show RTS as being asserted on 83 just in case future extensions to the instruction set require a state counter with additional bits 296 Other Possibilities Having established the basic modern conveniences needed to implement a very simple computer our imaginations could go wild thinking up new instructions and architectural extensions We could accommodate additional instructions opcodes by simply increasing the number of opcode bits an 8bit opcode would give us 256 Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Introduction to Digital System Design Page 64 possibilities And we could incorporate a more reasonablysized memory by simply increasing the number of address bits We could add new registers such as an additional accumulator or an index register as well as new addressing modes An index register could be used as a pointer to memory and facilitate implementation of a variety of new addressing modes The possibilities for improvements are endless 210 Summary and References In this chapter we have introduced the design and implementation of a simple computer and progressively embellished it with a number of extensions In addition to reviewing a topdown bottomup strategy for designing digital systems we have also provided a bridge between the basic digital logic design topics and the microcontroller oriented topics that follow in the curriculum There are a number of texts that delve into the myriad of topics associated with computer architecture and design written at a variety of levels One of the best and most widely used introductory texts is Patterson and Hennessey s Computer Architecture The Hardware Software Interface Morgan Kaufmann Their earlier text Computer Architecture A Quantitative Approach Morgan Kaufmann is an authoritative advanced text on the subject used in numerous graduate programs Other highly regarded texts on computer architecture include Mano s Computer Engineering Hardware Design PrenticeHall Stalling s Computer Organization and Architecture Macmillan Haye s Computer Architecture and Organization and Hamacher s Computer Organization One of the best sources for unbiased reviews of the latest and greatest microprocessors is Microprocessor Report a subscriber supported periodical published by Cahners Electronics Group Another excellent source of information on recent developments in microprocessor architecture is IEEE Micro a publication of the IEEE Computer Society For information on embedded microcontrollers and applications Circuit Cellar Inc magazine is the source of choice Web sites of the major manufacturers lntel Motorola Texas Instruments Hitatchi etc continue to be the best sources for detailed information concerning speci c microprocessors and microcontrollers Little Bits of Digital Wisdom 7 Supplemental Text 2001 by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 11 zuunul G Meyer Introduction to Digital System Design Module 1 Static and Dynamic Behavior of Digital Circuits Module 1 o Desired Outcome An ability to analyze static and dynamic behavior of digital circuits Part A Review of Basic Electronic Components Part B Logic Signals and Gates Part C Steady State Electrical Behavior of CMOS Circuits Part D Dynamic Behavior of CMOS Circuits Part E Other CMOS InputOutput Structures and Logic Families Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page l2 zuunul G Meyer Introduction to Digital System Design Module 1A Review of Basic Electronic Components Basic Electronic Concepts 0 VOLTAGE difference in electrical potential expressed in 0 CURRENT the flow of charge in a conductor between two points having a difference in potential expressed in amps o Waterfall analogy voltage is proportional to of waterfall current is proportional to of waterfall 0 POWER amount of energy expressed in typically calculated as the product of the drop across a device and the flowing through it Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 13 Basic Electronic Concepts o RESISTOR a device that limits the amount of current flowing through a circuit measured in Q o Resistance is also referred to as o The inverse of impedance is o Fundamental relationship the voltage drop VR across a resistor is equal to the product of the current flowing through it IR and the value of the resistance R 2 called D Basic Electronic Concepts o CAPACITOR a device that stores an electric charge measured in o Fundamental relationships a resistorcapacitor RC network charges and discharges exponentially the voltage across a capacitor cannot change instantaneously the product of R and C is called the Vc VIN X 1 39 e39tRC i V39quot LV Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 14 Basic Electronic Concepts o DIODE a device that restricts the flow of current to a single direction from its t quots H o Fundamental relationships a diode through which current is flowing because the voltage at the anode is greater than at the cathode is if current is not flowing through a diode because the voltage at the cathode is greater than at the anode the diode is Basic Electronic Concepts o LIGHT EMITTING DIODE LED a diode that emits visible redyellowgreenlblue or invisible infrared light when forwarded biased E I U Fundamental relationships gt the brightness of an LED is proportional to the amount of current flowing through it called the a is placed in series with an LED to limit the amount of current flowing through it the voltage drop across an LED when it is forward biased is called the Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 15 Basic Electronic Concepts 0 FIELD EFFECT TRANSISTOR FET a 3terminal device gate source drain that provides a controlled impedance 0 Two basic types Nchannel potential on gate causes transistor to turn on low impedance between source and drain Pchannel potential on gate causes transistor to turn on Nchannlsl Pchannel l Gala G Ag 5 s Basic Electronic Concepts 0 FET acts as a controlled switch VCC Voltagecontrolled resistance R increase VGS a decrease RDS 39 Note normall V 20 Nchannel D V GS G I As RDS decreases power S delivered to load RL increases FETs are used to construct Complementary Metal Oxide Semiconductor CMOS logic circuits and can also be used to switch DC loads Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 16 Basic Electronic Concepts 0 BIPOLAR JUNCTION TRANSISTOR BJT a 3terminal device base emitter collector that provides a controed impedance 0 Two basic types Nchannel current flowing into base through emitter causes large current to flow from collector to emi Pchannel current flowing out of base through emitter causes large current to flow from emitter to collector Ncha nel Pchannel C C B B E E Basic Electronic Concepts 0 BJT acts like a currentcontrolled switch all B gtE current BJTs are used to construct TransistorTransistor Logic TTL and can also be used to switch high DC loads Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 17 Basic Electronic Concepts 0 INTEGRATED CIRCUIT IC a collection of logic gates andor other electronic circuits fabricated on a single silicon chip 0 PROGRAMMABLE LOGIC DEVICE PLD an integrated circuit onto which a generic logic circuit can be programmed and be subsequently erased and reprogrammed o COMPUTER a digital device that sequentially executes a stored program 0 MICROPROCESSOR a singlechip embodiment of the major functional blocks of a computer Basic Electronic Concepts 0 MICROCONTROLLER a complete computer on a chip including integrated peripherals memory analogtodigital conversion serial communications pulse width modulation timers network interface 0 SOCIALLY REDEEMING something that has inherent value like studying digital systems design 0 DIGIJOCKETTE a person who enjoys learning about digital systems Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 18 zuunul G Meyer Introduction to Digital System Design Module lB Logic Signals and Gates Reading Assignment 3rd Ed pp 7995 4th Ed pp 7996 Instructional Objectives 0 To learn a definition of Boolean algebra c To learn about the three major operators in Boolean algebra and the symbols used to represent them 0 To learn about the basic logic gates that are used to implement digital circuits 0 To learn about the circuits that are used to implement logic gates Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 19 Outline 0 Definition of Boolean Algebra 0 Logic signals and assertion levels 0 Combinational digital logic circuits 0 Boolean s big three operators 0 Logic families 0 CMOS logic 0 Switch analogies and implementations Boolean Algebra 0 Definition A Boolean Algebra is a triplet K 0 consisting of a finite set of elements K subject to an equivalence relationship and two binary operators denoted OR and 0 AND such that for every element X and Y contained in K the operations X Y and X 0 Y are uniquely defined and described later are satisfied Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 110 Boolean Algebra 0 Definition An equivalence relation is some relation R defined on a set K which satisfies the following three basic properties for every X in the set K the relationship XRX holds for every X and Y in the set K the relationship YRX holds whenever the relationship XRY holds for every X Y and Z in the set K if the relationships XRY and YRZ hold then the relationship XRZ holds Boolean Algebra 0 Definition A binary variable X is a two valued quantity such that ifX 1thenX0 ifX 0 thenX1 oK01 Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 111 Boolean Algebra 0 Huntington s Postulates P1 The operations are closed For all X and Y e K a X Y e K b X Y e K P2 For each operation there exists an identity element a There exists an element 0 e K such thatforallXe KX 0X b There exists an element 1 e K such thatforallXe KX1X Boolean Algebra 0 Huntington s Postulates P3 The operations are commutative For all X and Y e K a X Y Y X b X Y Y o X P4 The operations are distributive For all X Y and Z 6 K aXY ZXY XZ bX0YZXoYXoZ Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 112 Boolean Algebra 0 Huntington s Postulates P5 For every element X e K there exists an element X e K called the complement of X such that a X X 1 b X o X 0 P6 There exist at least two elements X and Y e K such that X at Y Logic Signals o A logic value 0 or 1 is often referred to as a ginary digit or o The words LOW and HIGH are often used in place of 0 and 1 to refer to LOW a signal in the range of lower voltages eg for CMOS logic which is interpreted as a logic 0 HIGH a signal in the range of higher voltages eg for CMOS logic which is interpreted as a logic 1 Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 113 Logic Signals 0 Note The assignment of 0 and 1 to LOW and HIGH respectively is referred to as a or simply positive logic a positive logic signal that is is in the HIGH state and is therefore referred to as an active high signal a positive logic signal that is is in the LOW state Logic Signals o The opposite assignment 1 to LOW and 0 to HIGH is referred to as a logic convention or negative logic a negative logic signal that is asserted is in the LOW state and is therefore referred to as an signal a negative logic signal that is negated is in the HIGH state Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 114 Logic Signals o A logic circuit can be represented as simply a black box with a certain number of inputs and outputs f fuel2 V m KM o Since the inputs of a digital logic circuit can be viewed as discrete 0 and 1 values the circuit s logical operation can be described using a table that lists discrete 0 and 1 Combinational Circuits o A logic circuit whose outputs depend only on its current inputs is called a o A can be used to fully describe the operation of a combinational logic circuit a Three basic logic functions AND OR and NOT can be used to build digital combinational logic circuit idea of Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 115 Boolean s Big Three 0 An gate produces a1 output if and only if all of its inputs are An ate produces a 1 output if one or more of its inputs are 0 A gate usually called an inverter produces an output value that is the ve oppos e of Its Input value bubble m M m m l u u l D l CC 77 Another 10 Two 0 A gate produces the opposite of an AND gate s output 0 gate produces the opposite of an OR gate s output X m X 4 o i XNANDY v XNORY 1 x v o u o 1 x a 1 l Aaax n l l o l o n o l o Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 116 Time Matters 0 Logic gates require a certain amount of think time to produce a new output in response to changing inputs referred to as the of the gate The propagation delay of a logic circuit may vary depending on whether its output signal is transitioning from lowtohigh rise propagation delay or from hightolow fall propagation delay A 0 can be used to show how a logic circuit responds to timevarying input signals Time Matters 0 Time response ofa combinational circuit XVvX Y J 1 Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior ofDigilal Circuits Lecture Workbook 7 Page 1717 Logic Families 0 There are m ys to design a digital logic ansIs ors ccessful bipolar logic family is TransistorTransisto 39 o Complementary MetalOxide Semiconductor circuits now accou tfor the vast majority of the worldwide Integrated Circuit market o CMOS logic is both the most capable and the easiest to understand commercial logic technology al CMOS Logic 0 CMOS logic levels unda nerl ligmisvei MOS c c t voltages e or n the voltage range 5 Little 5m 3nger Modern 2006707 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 118 CMOS Logic 0 MOS transistor Modeled as a 3terminal device that acts 39ke a In digital logic applications a MOS transistor is operated so that its resistance is either transistor Is veryhightransistors or verylow u n CMOS Logic 0 There are two types of MOS transistors Nchannel MOS NMOS D a Voltagecontrolled resistance ante G VGs a W Note normlly v65 2 o S Pchannel MOS PMOS S Voltagecontrolled resistance G 7 some GS a a dram Note normally v65 5 o Littlz 31L ofngxtal VWsdom 200507 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 119 Basic CMOS Inverter Circuit quot 5uv m g mumm V n i Q mmmah VD 4 u v quuv ma DH ow H quotwH D fwd 1 i i E 1 h m g gunman R 3 w m L Vnw 21 mm H L wh A a Q a Q m 2 H L L off on aquot H L H cquot an an equot H 2 H L on oquot c on H H H an aquot on aquot L V W nzH Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior ofDigital Circuits Lecture Workbook 7 Page 120 Basic CMOS NOR Gate Vim m 39E Ixrr rxr rrr N wiiiiimiooih hem m io Diqm newquot nmieoieeimoeiee i e Exercise Transform this 2input NOR gate into a 3input NOR gate nu LZZZIE Bu Uszgztal Wlsdum 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 121 zuunul G Meyer Introduction to Digital System Design l Module 1C Steady State Electrical Behavior of CMOS Circuits Reading Assignment 3rd Ed pp 96113 4th Ed pp 96114 Instructional Objectives 0 To be able to read and understand device data sheets and specifications in order to create reliable and robust realworld circuits and systems 0 To be able to use data on logic levels to calculate the DC noise margin of a circuit 0 To be able to use data on sourcing and sinking currents to calculate fanout c To learn about the deleterious side effects of excessive output loading unused inputs noise spikes and electrostatic discharge Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 122 Outline 0 Overview 0 Data sheets 0 Noise 0 Logic levels and noise margins o Sourcing and sinking current 0 Nonideal inputs 0 Fanin and Fanout 0 Effects of loading 0 Unused inputs 0 Current spikes and decoupling o Electrostatic discharge Overview o Obiective To be able to design real circuits using CMOS or other logic families need to ensure that the is valid for a given circuit need to provide adequate engineering to ensure that a circuit will work properly under a variety of conditions need to be able to read and understand data sheets and specifications in order to create reliable and robust realworld circuits and systems Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuim Lecture Workbook 7 Page 123 Data Sheet for a T CMOS Device Pummzler 0 Yes Cnndltions Noise 0 The main reason for providing engineering design margins is to ensure proper operation in the presence of 0 Examples of noise sources cosmic rays magnetic fields generated by machinery ower supply disturbances the of the logic circuits themselves Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 124 Logic Levels and Noise Margins 0 Typical inputoutput transfer characteristic of a CMOS inverter Problem Typ T guaranteed HlGH VD ed HlGH Logic Levels and Noise Margins 0 Factors that cause the transfer characteristic to vary power supply voltage temperature output loading conditions under which a device was fabricated 0 Sound engineering practice dictates that we use more specifications for LOW and HIGH Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior ofDigital Circuits Lecture Workbook 7 Page 125 Logic Levels and Noise Margins 0 Definitions VOHmm the minimum voltage in the s lem the minimum voltage guaranteed to be recognized as a VLmax the maximum voltage guaranteed to be recognized as a V0Lmax the maximum voltage in the state Logic Levels and Noise Margins I CMOS levels are typically a function of the power supply rails V VOHmm Vcc 01V VHmm 70 of Vcc VLmax 30 of Vcc l W V0Lmax GND 01V u u 7 v V DC noise margin is a measure of how much n0Ise it takes to we rst case output voltage into a value that may not be recognized properly by an input Little 5m ofDngtal Wzsdom 2005 07 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 126 Logic Levels and Noise Margins 0 Calculation of DC noise margin or the noise immunity margin DCNM min VOHmin Vlein VILmalx VOLmalx 0 Example HCseries CMOS DCNM Sourcing and Sinking Current a CMOS gate inputs have a very high impedance and consume very little current from the circuits that drive them IL the maximum that flows into the in the state IH the maximum that flows into the in the state For CMOS logic the input current is very small it takes very little power to maintain a CMOS input in either the HIGH or LOW state Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 127 Sourcing and Sinking Current o Often times gate outputs need to drive devices that require a nontrivial amount of current to operate called a load or load When driving a resistive load the output of a CMOS circuit is not nearly as as described previously In either output state the CMOS output transistor that is on has a nonzero resistance and a load connected to its output terminal will cause a voltage drop across this resistance Sourcing and Sinking Current o lC manufacturers specify a maximum load for the output in each state HIGH or LOW and guarantee a worstcase output voltage for that load OLmax the maximum that the can sink in the state while still maintaining an output voltage no greater than VOLmax OHmax the maximum that can source in the state while still maintaining an output voltage no less than VOHmin Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 128 Sourcing and Sinking Current 0 Circuit definitions of IOL and IOH max max al k Hi I v t Sourcing mam cmos iiwauer x l gtlMD l 39m m J m m y m m v sislive quot im current arrow mm mm v NOTE Convention is for the inputoutput current arrows to in Sourcing and Sinking Current 0 Most CMOS devices have two sets of loading specifications device output connected to other CMOS inputs which consume very little current device output connected to resistive loads devices that consume significant current Note With DC loads the output voltage swing of a CMOS circuit may significantly Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 129 Nonideal Inputs o If the inputs to a CMOS circuit are not close to the Vcc I GND rails the on transistor may not be on and the of transistor may not be off causing power dissipation of the device to cw v v m v m lt lt Z mun Z l m Iquothli39W vanguw deivr vmwuv lt lt 3 23m 3 mm 3 i Fanin 0 Definition The number of inputs a gate can have in a particular logic family is called the logic family s o CMOS gates with more than two inputs can be obtained by extending the series parallel circuit designs eg for NAND and NOR gates illustrated in the previous lecture o In practice the additive on resistance of series transistors limits the fanin of CMOS gates to a relatively small number 0 Gates with a large number of inputs can be made faster and smaller by cascading gates with fewer inputs Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuim Lecture Workbook 7 Page 130 Fanout 0 Definition The number of gate inputs that a gate output can drive its worstcase loading specifications depends on characteristics of both the output device and the inputs being driven must be examined for both the sourcing and sinking cases practical limitations due to capacitive loading AC vs DC fanout Fanout min IOHmaXI IIH IOLmaXIIIL Data Sheet for a T CMOS Device rm Candllions Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 131 Fanout o Example HCseries CMOS Fanout min IOHmax IIH IOLmalx IIL Note DC fanout is considerably greater in this case if the output voltage swing is degraded but DCNM is lower and signal transitions times are longer causing speed degradation Practical Fanout o In a practical application a gate output may drive a mixture of loads a HIGHstate fanout The sum of the Ileax values of all the driven inputs must be less than or equal to the IOHmax of the driving output a LOWstate fanout The sum of the Ileax values of all the driven inputs must be less than or equal to the IOLmax of the driving output The practical fanout is the of the HIGH and LOWstate fanouts Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dwamic Behavior of Digital Circuits Lecture Workbook 7 Page 132 Effects of Loading 0 Loading a gate output beyond its rated fanout can have several deleterious effectS39 in the LOW state the output voltage VOL may increase beyond VOLmax in the HIGH state the output voltage VOH may fall below VOHmin output rise and fall times may increase beyond their specifications the operating temperature of the device may increase thereb t e of the device and eventually causing device Unused Inputs 0 Unused spare CMOS inputs should never be left unconnected o A small amount of circuit noise can temporarily make a floating input look HIGH 0 Instead unused inputs should be tied to another input of the same gate tied HIGH for AND and NAND gates tied LOW for OR and NOR gates lhl m x Z 2 W X z ml K Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 133 Current Spikes and Decoupling a When a CMOS gate output changes state the p and nchannel transistors are both partially on simultaneously causing a a Current spikes often show up as on the power supply and ground connections a between Vcc and GND must be distributed throughout a printed circuit board PCB to supply extra current during transitions to CMOS le VERY IMPORTANT FOR SENIOR DESIGN PROJECTS Electrostatic Discharge a CMOS device inputs are subject to damage from electrostatic discharge ESD o Apply these precautions in lab before handling a CMOS device touch a source of transport CMOS devices in or tubes handle circuit boards containing CMOS devices by the touch a ground terminal on the board to earth ground before poking around with it Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 134 zuunul G Meyer Introduction to Digital System Design l Module 1D Dynamic Behavior of CMOS Circuits Reading Assignment 3rd Ed pp 113122 4th Ed 114128 Instructional Objectives 0 To learn what factors influence the performance of a CMOS circuit 0 To learn the definition of transition time and how to measure it c To learn how to analyze and estimate the transition times of a CMOS circuit 0 To learn about the effects of capacitive loading on a CMOS circuit 0 To learn the definition of propagation delay and how to measure it c To learn about the sources of power dissipation in a CMOS circuit Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 135 Outline 0 Overview 0 Transition time o Capacitive loading 0 Propagation delay 0 Power consumption Overview o The and of a CMOS device depend on the dynamic AC characteristics of the device and its load a Logic designers must carefully examine the effects of output loading and redesign where the loading is too high a Speed performance depends on two characteristics Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 1 as Transition Time n mount of time that the outpu fa logic circuit takes to change from one state to ano rise time tr OrtTLH the an output signal takes to from lowtohigh fall time tf OrtTHL the an output signal takes to from hightolow 0 Gate outputs can change state ith a transition time of zero because they need to of the wires and other components they drive Transition Time l il l i if Little Bit Ongxtal VWsdom 200507 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 137 Transition Time a To avoid difficulties in defining the endpoints are normally measured one of two different ways at the boundaries of the valid logic levels ie VIHmin and Vleax at the 10 and 90 points of the output waveform Using the first convention above the rise and fall times indicate how long it takes for an output signal to pass through the undefined between LOW and HIGH Transition Time a The transition times of a CMOS circuit depend mainly on two factors o called an arises from at least three different sources output circuits including transistors internal wiring and packaging wiring that connects a gate output to other gate inputs input circuits including transistors internal wiring and packaging Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior ofDigital Circuits Lecture Workbookr Page 133 Transition Time 0 A gate output39s load can be modeled by an equivalent load circuit with 3 components RL and VL represent the they determine the steady state voltages and currents present and do not have m c effect on transition 39 load ges and currents present thlet e output is changing as ow long it takes to change from one state to Equivalent Circuit for Transition Time Analysis of a CMOS Output Equivni n mu m unneilmnrluna mwiysis mw l W Little 3m afngxtal Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 139 Model of a CMOS LOWtoHIGH Transition with Negligible DC L ad CH HT lAH 4 h lJH V Egg L HA I 2 2 I Mi 2 1000 AC load AC ble lb D Vnm V lt 1U 11 3 1mm mapl Model of a CMOS HIGHtoLOW Transition with Negligible DC Load m cmV M Vinuv L E 1000 ltquot gt15 AL m AL load le m 2va 71 v Hqu um g gt I Mn quotHri in lam 3 I lUllpF lUDpF V Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 140 Example 0 Given that a CMOS inverter s Pchannel MOSFET has an ON resistance of 2000 that its Nchannel MOSFET has an ON resistance of 1000 and that the capacitive or AC load CL 200 pF calculate the fall time ll nun l mm u m 1 mv 7 1 u Inn H gt i Ml 2mm 4 nixmt ngx lt5 4i E t 4 DAV 4 Example 0 Fall time calculation t RnquotCL39ln VowVon t 1012tln Vnut I 50 2010399n vnut I 50 t35 2010399n l50 713 ns t15 2010399n l50 2408 ns fall time ns Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 141 Transition Time a Conclusion An increase in load capacitance causes an increase in the RC time constant and a corresponding increase in the output transition risefall times a Load capacitance must be to obtain high circuit performance this can be achieved by minimizing the number of inputs driven by a given signal creating multiple copies of the signal using buffers careful of the circuit Transition Time a Rule of Thumb In practical circuits the transition time can be using the RC time constant of the charging or discharging circuit a Final note Calculated transition times are to the choice of logic levels ie VIHmin and Vleax Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 142 Example 0 Given that a CMOS inverter s Pchannel MOSFET has an ON resistance of 2009 that its Nchannel MOSFET has an ON resistance of 1009 and that the capacitive or AC load CL 200 pF estimate the fall time and rise time Fall time estimate Rise time estimate RN X CL X RP X CL X ns ns Propagation Delay o Definition The electrical path from a particular input signal of a logic element to its output signal is called a o Definition The amount of it takes for a change in an input signal to cause a corresponding change in a gate s output signal is called the tp o The propagation delay for an output signal going from to tPLH may be different than the propagation delay of that signal going from to tPHL Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior ofDigital Circuits mm Workbook 7 Page 143 Propagation Delay um hw chnqirm2nnuw m m m m W Design rimMam mum Propagation Delay multistage devices eg noninverting gates may require several intemal transistors to change state before the output can change state Little 3m afngxtal Wisdom 200507 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 144 Example Find each of the x following e nearest 12 ns assume each division is 1 ns Rise propagation delay tPLH ns Fall propagation delay tPHL ns Rise time tTLH based on Wakerly s de nition ns 30 70 Rise time tTLH based on standard 1090 definition ns Fall time tTHL based on Wakerly s de nition ns 70GO Fall time tTHL based on standard 90 10 definition ns Power Consumption 0 Definition The power consumption dissipation of a CMOS circuit whose output is not changing is called quiescent power dissipation 0 Most CMOS circuits have static power dissipation o CMOS circuits only dissipate a significant amount of power during this is called dynamic power dissipation Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 145 Power Consumption o Sources of dynamic power dissipation the partial shortcircuiting of the CMOS output structure eg when the input voltage is not close to one of the power supply rails called PT power due to output the capacitive load on the output power is dissipated in the on resistance of the active transistor to chargedischarge the capacitive load called PL power due to chargingdischarging Power Consumption a Total dynamic power dissipation PT PL is proportional to the of the power supply voltage times the transition frequency a Conclusions power dissipation increases as the frequency of operation increases reducing the power supply voltage results in a reduction of the power dissipation Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 146 Example o A microcontroller dissipates 100 mW of power when operated at a clock frequency of 10 MHz What will be the its power dissipation if the clock frequency is reduced to 2 MHz Answer X 100 mW mW Example o A microcontroller dissipates 100 mW of power when operated at a supply voltage of 5 VDC What will be the its power dissipation if the supply voltage is reduced to 3 VDC Answer X 100 mW mW Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 147 zuunul G Meyer Introduction to Digital System Design l Module lE Other CMOS InputOutput Structures and Logic Families Reading Assignment 3 Ed pp 123142 149154 166171 4th Ed pp 129154 158170 Instructional Objectives 0 To learn about specialized CMOS circuit structures including Schmitttrigger inputs threestate outputs open drain outputs 0 To learn what wired logic is and how it works 0 To lean how to interface TTL and CMOS gates Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 148 Outline 0 Overview 0 Schmitttrigger inputs 0 Tristate outputs 0 Open drain outputs 0 Driving LEDs 0 Wired logic 0 TTLICMOS interfacing Overview o The basic CMOS circuit has been tailored in many ways to produce gates for specific applications a This circuit tailoring has been motivated by the need for higher performance than can be achieved with standard NANDNOR gates conditioning noisy slowly changing logic signals allowing logic elements to communicate via buses Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 149 SchmittTrigger Inputs 0 Definition A is a special circuit that shifts the switching threshold depending on whether the input is changing from LOWtoHIGH or from HIGHtoLOW o The difference between the two thresholds is called im r Symbol r v quot used to denote hysteresis Comparison of an Ordinary Inverter to a Schmitt Trigger for a Noisy Slowly Changing Input Signal L W U ml Inverter Low Schmitt trigger Low little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 150 Schmitt Trigger Inputs o Observations Schmitttrigger inputs have margin than ordinary gates for Distorted logic signals of this type typically occur in such as NO buses and computer interface cables Rule of Logiclevel signals can be sent reliably over a cable for only a ThreeState Logic o Definition A gate output that has a third electrical state is called a output or output a This third electrical state is called the high impedance or state In the high impedance state the gate output effectively appears to be from the rest of the circuit Threestate devices have an extra input typically called the OE for enabling data to flow through the device when asserted or placing the output in the high impedance state when negated Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dwiamic Behavior of Digital Circuits Lecture Workbook 7 Page 151 CMOS ThreeState Buffer AECD QIQZOUT LHHL oquot QWHVZ HHHL aquot DWHl39Z LLHH oliL HLLL aquot on H The most common use of these devices is to create data buses collection of signal lines overwhich computational subsystems can 54 quot send and receive data OpenDrain Outputs 0 Definition A CMOS output structure that does not include a pchannel transistor is called an 0 An opendrain output is in one of two states LOW or open ie disconnected An is used to indicate that an output is open drain 0 An opendrain output requires an external pullup resistor to pull it high in the open state since the output structure does NOT include a pchannel Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 152 OpenDrain CMOS NAND Gate u in A E 9 Q 2 Z L L 0 aquot open L H all on open H L Dr of open A D 9 H H on B u 422 Symbol that denotes an opendrain output Open Drain Gate DriVin g a Load Wu m rimming Fi mum u Vien39ia Em L Wu Note Rise time of an open drain output is quot C 1mm standard gate i39am s m Jim Jim time Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 153 Driving LEDs 0 One application for opendrain outputs is driving lightemitting diodes LEDs Driving LEDs 0 Standard CMOS gate outputs can also be used to drive LEDs either by sinking current LOW or sourcing current HIGH v Z LED Question Which method is preferred Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 154 Example Based on the data provided in Table 33 on page 98 of the course text calculate the value of the LED current limiting resistor for the worst case current sinking configuration Also calculate the amount of power dissipated by the current limiting resistor Assume VLED is 19 volts ZLED Table 33 from DDPP 1 rest conditions Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 155 SOLUTION VR 50 VLED 50 19 V NOTE Here use value indicated for of V R VRIIOL n R x IOL2 x 00042 milliwatts NOTE Can also calculate power dissipation of resistor using VR x IOL or VR1lR Example Based on the data provided in Table 33 on page 98 of the course text calculate the value of the LED current limiting resistor for the worst case current sourcing configuration Also calculate the amount of power dissipated by the current limiting resistor Assume VED is 19 volts it a 7 zLED Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 156 SOLUTION VR VLED 19V NOTE Here use value 40 mA indicated for V R an39ou 9 384 VDC PR R x It 2 x 00042 milliwatts NOTE Can also calculate power dissipation of resistor using VR x 0H or VR1lR Z LED Wired Logic 0 Definition Wired logic is performed if the outputs of several opendrain gates are tied together with a single pullup resistor Va Caution i Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 157 Illustration of Fighting Illustration of what happens if two ordinary m CMOS gate outputs are tied together don t try this at home HlGH HlGH Pullup Resistors o In opendrain applications two calculations bracket the allowable values of the pullup resistor R LOW The sum of the current through R plus the LOW state input currents of the gate inputs driven the IOLmax of the active device HIGH The voltage drop across R in the HIGH state the output voltage below the VIHmin of the driven gate inputs Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 158 Pullup Resistor Calculation Here the pullup resistor must be no more than the i value Rmax such that the W7 39 g quot voltage drop across it does i i not exceed 50 24 26 v 2 i when 60 uA of current is WW 9 l flowing through it i39 ll i v DW V J iv Applying Ohm s Lawwe vv is 7 find that Rmax is 26000006 137Do w 43333 ohms Pullup Resistor Calculation LOW State Here the constraint is that the pullup resistor must be chosen such that the HI i f voltage drop across it 1 must be at least 50 04 ll 46 then 32 mA is i 1AM flowing through it l Applying Ohm s Law we 7D find that Rmin is 4600032 131711 3 1438 ohms 1438 S R 5 43333 l mu 2 NW 7 a T l Low 7 iiw 7 Vi Little Bits ofDigital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 159 Example Given the following circuit with all of its inputs connected to a LOW logic level If the offstate leakage current of each of the 74x03 opendrain NAND gate outputs is 5 M and the lIH required by the 74x04 inverter is 90 uA determine the value of the pullup resistor R to obtain a VIH of 49 V at the 74x04 input Solution Current through R R Voltage drop across R VR R VRlR Q Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 160 CMOSTTL Interfacing o A typical system design may contain a mixture of CMOS andor TTL families due to o It is important for a designer to understand the implications of connecting TTL outputs to CMOS inputs and vice versa o Factors to consider CMOSTTL Interfacing o All of the CMOS and TTL devices that we will discuss have part numbers of the form 74FAMnn where FAM is an alphabetic mnemonic and nn is a numeric function designator o Devices in different families with the same nn perform the same function a The prefix 74 has no social significance it was made popular by Texas Instruments o The prefix 54 is used to signify milspec parts wider temperature range Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook 7 Page 161 TTLCMOS InputOutput Levels OUTPUTS 5 0 lNPUTS Ii llmm l iiium HIGH Him 39ilmm HC HCT 384 385 HC VHC VHC VHCT 380 J Highrslaie DC noise margin LS S ALS AS F 27 20 LS 5 ALS As F HCT VHCT FCT Hal drawn 0 C iE ABNORMAL i i 35 HQ IHC 08 LS 5 ALS AS F FCT 055 HCTVHCTFCT LSSALSASF 05 VHCVHCT 044 39 LOWSFJIF HC HCT 0337 Low 0 DCl lUlellldfgl Review Quiz Digital Jeopardy 1 The maximum input current for any value of input voltage The maximum capacitance of an input The maximum voltage that an input is guaranteed to recognize as LOW The minimum voltage that an input is guaranteed to recognize as HIGH Little Bits of Digital Wisdom 200607 Edition by D G Meyer Static and Dynamic Behavior of Digital Circuits Lecture Workbook Page 162 ReVIeW Qulz Digital Jeopardy 2 The maximum current that an output can supply in the LOW state while driving a CMOS load The maximum current that an output can supply in the LOW state while driving a TTL load The maximum voltage that a LOW output is guaranteed to produce driving a CMOS load The maximum voltage that a LOW output is guaranteed to produce driving a TTL load ReVIeW Qulz Digital Jeopardy 3 The maximum current that an output can supply in the HIGH state while driving a CMOS load The maximum current that an output can supply in the HIGH state while driving a TTL load The minimum voltage that a HIGH output is guaranteed to produce driving a CMOS load The minimum voltage that a HIGH output is guaranteed to produce driving a CMOS load Little Bits of Digital Wisdom 200607 Edition by D G Meyer
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