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Computer Architecture

by: Nick Rowe

Computer Architecture CS 25000

Nick Rowe
GPA 3.68

Dongyan Xu

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Dongyan Xu
Class Notes
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This 29 page Class Notes was uploaded by Nick Rowe on Saturday September 19, 2015. The Class Notes belongs to CS 25000 at Purdue University taught by Dongyan Xu in Fall. Since its upload, it has received 107 views. For similar materials see /class/208067/cs-25000-purdue-university in ComputerScienence at Purdue University.

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Date Created: 09/19/15
C8250 x86 Assembly Programming Examples Compiled by Trishabh Chadda Description C code Assembly Code int i0 movl 0 eax long j1 movq 1 rdi Using b l and q char c39A39 movb 41 cl suffixes i incl eax j incq rdi c incb cl movl 10 ecx s r string d n int i1039 text Using printf printf d n i movl str edi movl ecx esi movq 0 rax call printf char greater int a int b greater movl rdi ecx movl rsi edx 0 0 cmpl oecx oedx A simple function I agt b jg gtr return 1 greater else movb 0 al ret return 0 gtr movb 1 al ret whileloop while ilt10 cmpl 10 ecx jge endwhileloop Whquote 39 p CODE CODE jmp whileloop endwhileloop Description C code Assembly Code for loop for i0ilt5i HCODEH movl 0 ecx forloop cmpl 5 ecx jge endforloop CODE incl ecx jmp forloop endforloop ifese statement if i2 CODE1 else HCODEZ cmpl 2 ecx jne elsetrue CODE1 jmp endif elsetrue CODE2 endif Using leaq long rcxrdi4rsi long rcxrdi8 leaq rdi rsi 4 rcx long rcxrdi8 Physical memory We39ll briefly explore The connecTion beTween main memory and The hard disk by Thinking abouT some siTuaTions IT is possible for programs or daTa To be Too large To fiT inTo memory EnTire movies games and Their daTa files large corporaTe daTabases In The old days programmers were responsible for making Things fiT by loading The appropriaTe daTa from disk To memory when iT was needed in oTher words managing The cache explicile There are several complicaTions when a compuTer can mulTiTask or run several programs aT The same Time Programs may be loaded inTo differenT addresses Memory mighT become fragmenTed Programs should have Their own privaTe area of memory safe from oTher processes LeT39s look aT These nexT Addresses and programs When we wriTe a MIPS program we may specify some absoluTe addresses such as J 20000 BuT ThaT 20000 assumes The program is always loaded inTo The same block of memory WhaT if There are Two programs ThaT boTh conTain a j 20000 insTrucTion They can39T boTh be placed in The same memory region wiThouT requiring a loT of swapping or reloading from The disk whenever The operaTing sysTem swiTches beTween The Two programs IT39s more convenienT To place each program in a differenT memory locaTion buT Then how do we figure ouT which real memory address corresponds To The 20000 in The program Memory fragmentation 39 A related problem is that if several programs are loaded into different areas of memory and are deleted when they exit free memory could become fragmented or split into many smaller chunks Program Free Program Free 1 space A 2 space B 39 If we try to load another program it might be too big to fit into either Fr39ee space A or Free space B but maybe it would fit if all of that free space was contiguous Program Free Free Program 1 space A space B 2 Program 3 Memory protection 39 Finally if would be greaT if we could make sure ThaT Program 1 can39T access any of Program 239s daTa PrevenT buggy programs from affecTing oTher ones PrevenT viruses from spreading PrevenT programs from sTealing daTa from oTher processes Program Free Program Free 1 space A 2 space B VirTual memory WiTh virTual memory each program fhhks iT has access To some large range of memory buT iT doesn39T really This is jusT an illusion presenTed by The operaTing sysTem and CPU TogeTher A program has access To a virTual address space eg from 0 To 2321 in MIPS buT The acTual daTa could eiTher be aT some oTher locaTion in The real physical memory or on The hard disk This is preTTy cool because Using The hard disk is slow buT iT makes The compuTer seem To have more physical memory Than iT really does More and larger programs can be run even wiTh limiTed amounTs of memory VirTual addresses can be mapped To almosT any physical address so programs don39T have To be sTored in conTiguous memory locaTions and fragmenTaTion is noT a problem The virTual address space for each process is managed by The CPU and 05 so iT39s hard for programs To inTerfere wiTh each oTher The basic seTup Physical memory is logically divided inTo chunks called pages which are Typically a few kilobyTes lar39ge 4KB64KB The oper39aTing sysTem gives each process a page Table which maps vir39Tual addr39esses To eiTher39 r39eal addresses or39 secTor39s on The disk Vir39Tual Address I Vir39Tual pa e I Page off5eT I 1 20 biTs 12 biTs Page Table 0 5 2 2261 1 Hard disk le 0 225 1 An example memory system 39 This example shows 32biT vir39Tual addresses 4KB 212 pages A 64MB 226 memory A 256MB 228swapfie Vir rual Address I Vir rual pa e I Page offSe r I 1 20 bi rs 12 bi rs Page Table 0 2 226 1 1 V Hard disk Ie 0 225 1 Accessing virTual memory To access memory a program firsT supplies a virTual address The OS and CPU look up The virTual page number in ThaT process39 page Table The Table specifies wheTher The daTa is in physical memory or on disk The daTa can Then be loaded and reTurned To The program VirTuaI Address I VirTuaI pa e I Page off5eT I 1 20 biTs 12 biTs Page Table 0 2 2261 1 V Hard disk Ie 0 225 1 VirTual memory noTes The 05 plays a viTal role in virTual memory IT assigns page Tables To processes and helps look up The page Table for each memory access IT deTermines when pages should be loaded inTo physical memory or sTored in The swap file In oTher words iT manages The physical memory like The CPU manages The cache Where does The CPU come in The page Table in The previous example was big 1000000 enTries If The page Table is sTored in main memory iT would be slow and iT would Take up already scarce memory space Modern CPUs help The 05 OUT by including a special onchip page Table cache called a TranslaTion lookaside buffer or TLB Working wiTh all The differenT memory hierarchy levels TogeTher is Tricky CS 333 and CS 323 operaTing sysTems give more informaTion C5250 Computer Architecture Spring 2009 Part 2 Instructions Language of the Computer Acknowledgment for Lecture Notes Authorship Prof Craig Zilles Mr Howard Huang Both with the Department of Computer Science at UIUC Part 2 Machine Instructions Processor undertheHood View Clock Generator Computer architecture the Big Picture Computer architecture is about building and analyzing computer systems January 27 2009 4 Instruction Set Architecture Processor Memory InputOutput The Instruction Set Architecture ISA is the bridge between the hardware and the software We ll learn the MIPS ISA in detail We ll get a brief introduction to the x86 ISA We ll learn how HLL program constructs are represented to the machine We won t learn how compilers work but we ll learn what they do January 27 2009 5 MIPS In this class we ll use the MIPS instruction set architecture ISA to illustrate concepts in assembly language and machine organization Of course the concepts are not MIPSspecific MIPS is just convenient because it is real yet simple unlike x86 The MIPS ISA is still used in many places today Primarily in embedded systems like Various routers from M Game machines like the Nintendo 64 and Sony Playstation 2 January 27 2009 What you will need to learn You must become fluent in MIPS assembly Translate from C to MIPS and MIPS to C Example problem from a previous midterm Question 3 Write a recursive function 30 points Here is a function pow that takes two arguments n and m both 32bit numbers and returns nm ie n raised to the mth power int powint n int m if m return n return n pown m1 Translate this into a MIPS assembly language function January 27 2009 MIPS registertoregister three address MIPS is a registertoregister or loadstore architecture The destination and sources must all be registers except Special instructions which we ll see later today are needed to access main memory MIPS uses threeaddress instructions for data manipulation Each ALU instruction contains a destination and two sources For example an addition instruction a b c has the form operation operands add a b c destination sources January 27 2009 8 Register file review Here is a block symbol for a general 2k x n register file If Write 1 then D data is stored into D address You can read from two registers at once by supplying the A address and B address inputs The outputs appear as A data and B data Registers are clocked sequential devices We can read from the register file at any time Data is written only on the positive edge of the clock if D data gt Write k D address 2quot x n Register File k k A address B address A data B data if if January 27 2009 MIPS register file MIPS processors have 32 registers each of which holds a 32bit value Register addresses are 5 bits long The data inputs and outputs are 32bits wide More registers might seem better but there is a limit to the goodness It s more expensive because of both the registers themselves as well as the decoders and muxes needed to select individual registers Instruction lengths may be affected as we ll see in the future a D data gt Write 5 D address 32 x 32 Register File 5 5 A address B address A data B data a a January 27 2009 10 MIPS register names MIPS register names begin with a There are two naming conventions By number 0 1 2 31 By mostly twocharacter names such as aOa3 5057 tOt9 sp ra Not all of the registers are equivalent Eg register 0 or zero always contains the value 0 go ahead try to change it Other registers have special uses by convention Eg register sp is used to hold the stack pointer You have to be a little careful in picking registers for your programs January 27 2009 11 Basic arithmetic and logic operations The basic integer arithmetic operations include the following add sub mul div And here are a few logical operations and or xor Remember that these all require three register operands for example add t0 t1 t2 t0 t1 t2 mul s1 s1 a0 s1 s1 x a0 Note a full MIPS ISA reference can be found in Appendix A linked from website January 27 2009 12 Larger expressions More complex arithmetic expressions may require multiple operations at the instruction set level to t1 t2 gtlt t3 t4 t0 contains t1 t2 add t0 t1 t2 sub s0 t3 t4 Temporary value s0 t3 t4 mul t0 t0 s0 t0 contains the final product Temporary registers may be necessary since each MIPS instructions can access only two source registers and one destination In this example we could reuse t3 instead of introducing sO But be careful not to modify registers that are needed again later January272009 Immediate operands The ALU instructions we ve seen so far expect register operands How do you get data into registers in the first place Some MIPS instructions allow you to specify a signed constant or immediate value for the second source instead of a register For example here is the immediate add instruction addi addi t0 t1 4 t0 t1 4 Immediate operands can be used in conjunction with the zero register to write constants into registers addi t0 0 4 t0 4 MIPS is still considered a loadstore architecture because arithmetic operands cannot be from arbitrary memory locations They must either be registers or constants that are embedded in the instruction January 27 2009 14 We need more space Registers are fast and convenient but we have only 32 of them and each one is just 32bits wide That s not enough to hold data structures like large arrays We also can t access data elements that are wider than 32 bits We need to add some main memory to the system RAM is cheaper and denser than registers so we can add lots of it But memory is also significantly slower so registers should be used whenever possible In the past using registers wisely was the programmer s job For example C has a keyword register that marks commonlyused variables which should be kept in the register file if possible However modern compilers do a pretty good job of using registers intelligently and minimizing RAM accesses January 27 2009 15 Memory review Memory sizes are specified much like register files here is a 2k x n RAM 2k X quot memory CS WR Operation kgt ADRS OUT itquotgt 0 x None nquot DATA 1 0 Read selected address gt CS WR 1 1 Write selected address A chip select input CS enables or disables the RAM ADRS specifies the memory location to access WR selects between reading from or writing to the memory To read from memory WR should be set to 0 OUT will be the nbit value stored at ADRS To write to memory we set WR 1 DATA is the nbit value to store in memory January 27 2009 16 MIPS memory 232 x 8 memory 9 ADRS OUT 8gt CS gt WR MIPS memory is byteaddressable which means that each memory address references an 8bit quantity The MIPS architecture can support up to 32 address lines This results in a 232 x 8 RAM which would be 4 GB of memory Not all actual MIPS machines will have this much Address 01234567891011 8bitdatallllllllllll January 27 2009 17


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