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Microprocessor Systems

by: Karolann Wiegand

Microprocessor Systems ECE 4436

Karolann Wiegand
GPA 3.51

John Glover

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John Glover
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This 40 page Class Notes was uploaded by Karolann Wiegand on Saturday September 19, 2015. The Class Notes belongs to ECE 4436 at University of Houston taught by John Glover in Fall. Since its upload, it has received 57 views. For similar materials see /class/208297/ece-4436-university-of-houston in Electrical Engineering at University of Houston.

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Date Created: 09/19/15
ECE 4436 Chap 7 HCSl2 Instruction Set Dept of Electrical amp Computer Engineering University of Houston TABLE 71 H0812 Instruction Categories Instruction Category Move Data Modify Data Decision Making Flow Control Other Instruction Type Load Register Store Register Transfer Register Move Mcmoiy DeclenientIncrement ear et ShiftRotate Arithmetic Logic Condition Code Data Test Conditional Brunch Loop Primiiives Branch Bit Set or Clear Ju mp B ranch Interrupt Fuzzy 0 Miscellaneous ECE 4436 Reference Table Table 775 Table 776 Table 77 Table 78 Table 79 Table 7 l I Table 711 Table 739 2 Table 7 3 Table 7714 Table 7 5 Tables 7714 and 7717 Table 8 Table 77 7 Table 7719 Table 7720 Table 772 Table 7722 Examples Section 75 Sccxion 75 Section 76 Section 77 Section 78 Section 79 Section 7 IO Section 71 I Section 712 Section 717 Section 71 Section 714 Section 715 Section 714 Section 716 Section 718 Section 719 Section 720 ECE 4436 Load Register Instructions TABLE 7 5 Load Register Instructions Addressing Modes Condikian Codes I n E I I I Symbolic M I X D D N Function Oncode Operation M R 139 x n H N 2 v Loud AchIIIIleIIoI A LDAA IMI 7gtA x x x x t i 0 Load AchIIIII lmor B LDAB IMI gt B x x x x t t II Lo ILliKlm D LDD IM 39 M I I D I x x x x 1 U Load Slack Pomtcr LDS M M HgtSF I A x x t i 0 Lou L LDX thMllgtX x x x x i I o Loml Index R LDY IM V M H gt Y K x x x x I 1 U anI SP Ef LEAS EA s x 7 7 7 Loa LbAX A gt x x 7 7 7 anl Y Elf LEAY EA 7 Y x 7 7 7 PuII A Iu m Slack PULA ISPI A x 7 7 I II B I I PULB I I x 7 7 7 Pull LCR Imm BULL PULC SP CR K t t 1 Pull D from Slack PULD I5 5 I 7 D x 7 7 7 ECE 4436 Load Register Instructions TABLE 75 Continued Addressing Mudesa Condition Codes Symbolic M I X D D N Funclinn Opcode Operaliun M R T X R H N Z V C Pull X from Slack PULX SF SF i gt X x i i i Puquot Y from Sklck PULY SstP I Y x i i i quotli indexed uddressmg IDR indexedinditcct addressing quotOnly the candllinn and C 39stcr blls nf inlclcs m the programme are Shnwn in these tables Th 5 Mic STOP and imm39rum glmlp insn39uciimi and ammugh hc H bl ttmtitt icd by llmny insu uclions i oiinwittg nttmtttttt IS ust U mutt cliangus in His CWILKHIOI code I cgilcr 7 N0 Chillth and bis arc ICIMCd to i is of no concern to us The win it be I r rcmnln Clctllcd May he dame t 139 remain at May h L Mngetl but hm state unkimwu 4 eat ECE 4436 Store Register Instructions TABLE 76 Store Register Instructions Addressing Modes Condimon Codes I n E I I I Symbolic M I x n D N Funcliun Opcode Operation M a T x R H N z v Slur AtcuInululIIrA STAA A7 M x x x l t 0 3mm AchIIIIIIlaxor B B gt M x lt x x l i I smug AcquIIuIAIIII D D 7 M M II x x x x i 1 II Store Slack Poimcr SP gt M M 7 I x x x t t t 0 Sum Index Regislcr x MM V M I x x x x t t n More HAM Regisch39Y Y M M l x x x l i 7 Push A m Stuck A 7 SP x 7 7 7 Push B La qusk B 7gt SF x PIqu CCR m Smck CR 7 SP x 7 7 7 Push I lo smut D MSI Sl II x 7 7 7 Push x m mm x a SP x 7 7 Push YIo Slack Y gt SP 7 SP H x 7 7 7 ECE 4436 16 Bit Load and Store Instructions Store Registei Insimclion sid 1234 saws Figure 71 Sixteen bit load and store instructions 1234 1235 Memory MS Data LS Data Load Register instruction Idd 1234 Example 71 Load and Store Register Instructions Source line 11 12 13 14 15 16 17 18 19 000000 000002 000005 000007 000009 00000C 00000F 000012 000015 000017 decrement 20 21 22 000019 00001B E6E0 6B40 A63E EEEF A6E3 02 34 34 00 17 0100 Immediate addressing 1daa 64 Decimal 64 gt A 1ds 0902 0902 gt SP Direct addressing 1dab 64 0064 gt B staa 65 A gt 0065 Extended addressing 1daa 1234 1234 gt A 1dx 1234 12341235 gt stx 0800 X gt 0800 Indexed addressing 1dab 23X X23 gt B stab y B gt Y 1daa 2X X gt A X 2 gt X Auto Indexed indirect addressing 1dx dy DY gt X 1daa 100x X0100 gt A ECE 4436 Stack Instructions Stack Pointer SP 16bit address register that points to the value on top of the stack Stack grows toward lower addresses Push operation puts new value on top of stack Decrement SP Store value where SP points Pull pop operation take value off top of stack Load value from where SP points Increment SP Lower Memory Addresses Stack Pointer gt Higher Memory Addresses Unused Unused Unused DATA DATA DATA before a FULL Stack Pointer New Data 2 Figure 73 Stack operations rm h I duel push New Data 7 Stack Pointer PUSH Unused New Data 2 New Daia 1 afteruupull Unused Unused New Data 1 a erbpush New Data 3 Stack Pointer PUSH New Data 2 Stack Unused Po39mer New Daka 2 New Data 1 PUSH DATA DATA DATA after 2 push C Unused New Bake 3 New Data 1 DATA DATA DATA after 33 push e we a u a Stack pointer before stack operations b Stack pointer after a due a miru ECE 4436 Uses for the Stack Temporarily saving a few bytes of data from registers then restoring later Allocating data space for temporary variables such as automatic variables in C Saving the return address when the program calls a subroutine This is done automatically by the jumpto subroutine instruction J SR or BSR Similarly saving the return address when an interrupt occurs Normally stack operations must be balanced push Vperations matched by pullpop operations ECE 4436 Simple Stack Example Example 710 What does the following program sequence do pshx DUlV Solution It copies the contents of the X register into the Y register The condition cade rcgislcr is not modi ed An equivalent and Embably hotter instruction is TFR X Y Example 78 What is wrong with the following cude segmcnl Metrowerks HC1 Zriissemb er C COPYRIGHT METROWERKS 19872003 Rel Loc Obj code Source line 4 0000 0008 8 7 5 6 000000 C508 ldab COUNT Counter 7 8 loop 9 10 000002 36 psha 11 i 12 000003 0431 EC dbne b oop l3 14 000006 32 pula 15 Loop counLeL initialize loop Temp save A reg Decremen t B register and branch if zero Solution There is also unbalanced slack usage There is a push wiih no corresponding pull inside the loop ECE 4436 Calling Subroutines T 0 call a subroutine J SR subr Jump to subroutine many addressing modes BSR subr Branch to subroutine 9bit relative 1 Pushes PC return address of next instruction onto stack 2 Starts execution at target address subr Last instruction in subroutine RTS Return from subroutine Pops address off stack into PC thus resuming execution following the original J SRBSR ECE 4436 Calling Subroutines jsr printf call print function ltnext ins truction Address of this next instruction PC is pushed by j s r instruction printf ltdo printinggt rts return Top of the stack is popped into the PC by the rts instruction returning execution to the instruction following the j s r Example 77 What is wrong with the following code segment Mettowerks HCl2iAssembler C COPYRIGHT METROWERKS 19872003 Rel Loc 4 5 6 000000 7 000001 8 9 0 000002 12 000003 13 000004 14 000005 obj 30 3D Source line pshx psha pshb pula pulx rts Save the registers Temp save some data ResLore Lhc LeglsLets Solution The stack Operations are unbalanced That39e is Una more push than pull The subrou tine will not return to the proper place in he calling program ECE 4436 Load Effective Address Instructions Example 7 11 Load Effective Adda ess Instructions Assume X 1234 Y 1000 and SP 0A00 Give the contents of each affected reg ister alter the t oliuwing instructions are executed Instruction Result leax 1X X X i 10 51234 5000 123E ieax i0 X Y 10 1000 50010 S39iOiO leas lUSP SP SP 10M UAOO SUUUA Stng ECE 4436 Clear and Set Instructions TABLE 710 Ciear and Set Instructions Addressing Modes Condition Codes D E I I I symbolic M i x D D N Funciion 0pcode Operaiion M R T x R H N 2 v c Clear Memory CLR 0 a Mi x x x 0 i 0 0 lcurA CLRA OaA x n i n 0 Clem B CLRB u a B x u l o o lcar Bits in Mcmnry BCLR x x x 3 1 7 5m Bils in Memory BSET x x x 3 0 e ECE 4436 Bit Clear and Set Instructions VDD Current Limiting Resistors LEDS Port A Output Port Figure 74 BCLR and BSET used for turning on and off LEDs llllllllllllllll llllllll ill l l Multiplexed AddressData Figure 41 MCBS1ZC family block diagram PADO 16K 32K 64K 96K 128K byte Flash Ana 09 323 Digital Convener PADS ModuleATD Egg 1K 2K 4K byte RAM PADS PAD7 Background T Ioc lt p pTo 9 9 H0812 Ime 0C1 lt gt pT1 MODC ModuleBUM CPU Module Iocz lt MUX p F pTz TIM 003 gt L t PT3 PLL COP Watchdog 004 lt gt o 1 F T4 CI k dR 005 m 0 PTS cc 339 3 Clock Monitor loce I I PTG Generation Module IOC I P17 RG Perlodlc Interrupt I mugm lefLL System odulator pm 539 ppz IROJ IntegralionModuIe Mo ue E 35 EL PPS m m LST BiLTAGLoiL 5quot p pw5 i E E Egg E gt11 FPS MODAIIPIPEO MODEIPIPE1 NOACCIXCLKSL DH D D D D D RXCAN PMO MSCAN TXCAN E MISC m 1 EMS gt11 0339 PM5 H1 lSCK 1 DH MC9SIZC 0000 03FF 0800 0FFF 8000 FFOO FFFF ECE 4436 Hardware Memory Map for 98 12C32 1K byte Register Space IO registers appear Control registers for quot0 at these addresses lt RAM used for variable data storage and the stack 32K byte Flash EEPROM Program code and constant data storage Vectors Interrupt vectors Figure 6392 Memory map for MC9812032 microcontroller coqmmhwlonI 0 000000 000003 000006 000009 00000C 00000F 000012 000015 000018 00001B 00001E Example 720 LED Program Using BCLR and BSET 0000 0000 4C02 4C00 4D00 4D00 4D00 4D00 4D00 4D00 4D00 4D00 20E3 code Source line 0002 DDRA 0000 PTA FF FF I loop XDEF Entry main EQU EQU bset bset bclr bclr bclr bclr bclr bclr bclr bclr 0002 0000 DDRA11111111 PTA11111111 PTA00000001 PTA00000010 PTA00000100 PTA00001000 PTA00010000 PTA00100000 PTA01000000 PTA10000000 loop I I Port A register Data direction register Make all lines output Set all bits LEDs off Clear LED on Clear Clear Clear Clear Clear Clear Clear Do it bit 0 bit bit bit bit bit bit bit 7 forever 0301bme ECE 4436 Shift and Rotate Instructions TABLE 711 Shift and Rotate instructions Addressing Modes Condition Cudes D E I I Symbolic M I X D D N Funclion 0pcode Operation M R T x R H N 2 v Arilhmcti Shift Left Mammy ASL Figuic 775 X X x Arilhnlcti Shilt c l ASLA x Ai39illtm Shirt Left I4 ASLB x Arilimlciic Shirt Lu D i i rbit ASLD x Al39itlinicti Shift Right Memory ASR Vigil 776 X x x Arithmetic Shllt Right A ASRA x Arithmcric Shift Right B ASRB x Arithmetic Shift Right D t I rbin ASRD x ngicai Shift Left Memory LSL Figuic 777 x x x LUgiLai Shift Loft LSLA x Logical Shift Lc LSLB x Logicai SiiiliLci39t Di1 bil LSLD X Lugwui snitt Right Mcmmy LSR Figuic 78 x x 0 Logical Shift Right A LSRA x 0 L0 1 Shift Ri Yhi B LSRB X 0 Logical Siiili Right libriil LSKD x Rnlalc Lcl39t Mcmnl39y ROL Figiiic 779 x x x Rnli tlc Lmli ROLA x Rotate Lcl l B ROLB x Rotate Right Memory ROR Figure 7710 x x x Rolttlc Right A RORA x Rolatc Right B RORB x ECE 4436 Shift and Rotate Instructions lt Dm 0 Figure 75 Arithmetic shift left ASL BO instructions C B7 gt LG W Figure 76 Arithmetic shift right ASFi C B7 B0 instructions ECE 4436 Shift and Rotate Instructions m 0 Figure 77 Logical shift left LSL C B7 B0 instructions gt LEI 0 m Figure 78 Logical shift right LSR C B7 BO instructions ECE 4436 Shift and Rotate Instructions LDW Figure 79 Rotate left ROL C B7 BO instructions gt 1 W Figure 710 Rotate right ROR C B7 BO instructions ECE 4436 Example 723 Assume the A value is A8 What is the result of each of the fn1lnwing instructions ASLA ASRA LSLA LSRA ROLAt RORA Solution The easiest way to 100k at these instructions is to show the values in binary Before each instruction is executed A contains 701010 1000 After each instmction then we nd the fol Iowi ng Before Am 10101000 1010 I000 10101000 10101000 10101000 1010 I000 noxxxxlo Instruction m AM 01010000 11010100 01010000 01010100 010 000C C101 0100 Comments Zero shifted into bit 0 Sign bit is preserved Same rcsu1t as ASLA Diffcrcnt from the ASRA Carry bit is rotated into hit 0 Carry hit is rotated into bit 7 ECE 4436 An39thmetic Instructions TABLE 712 Continued Addressing Modes Condiliun Codes I Sym olic M I x D D N Function Opcode Operalian M R T x R H N 2 v c 39I wn s Coinplcineni A NEGA 7 A 7 A x I I I I wo39s Complemcnl B NEGB 7B 7 B x I I I I Unsigned min Mulliply A i B MUL is 7 D i 7 7 7 7 Unsigned min Mniiiniy EMUL D Y7 y D i I I 7 I signed 16bit Mnlliply FM ULS r i Y 7 Y D x I I I Unsigned 32l67hii Division EDIV Y ms 7 YD x I I I I Signed Sll rhii Division EDIVS mx 7 VJ x I I I I Unsigned ieIbhiz Di siun IDIV nx 7 XII 7 I 0 I Signed 1616 i Division DlVS x 7 XD x I I I I Fineiinnni Division I DIV DX 7 xii x I I I mummwaH H H H H w M H O 0 000000 000003 000006 000000 000002 Example 726 Multibyte Addition with D Register Obj code Source line XDEF Entry main Entry main Load 16 bits from Data1Data11 FCxx xx ldd Data1 Add 16 bits from Data2zData21 F3xx xx addd Data2 Save the result 7Cxx xx std Data3 Stores 16 bits Data SECTION Data1 dsw 1 Data2 dsw 1 Data3 dsw 1 H b 000004 Example 725 Multibyte Addition with Carry Bit Add the least significant bytes first Get least sig byte of 16 bit Datal ldab Data11 Add in the least sig byte of Data2 addb Data21 The sum is in B and the carry bit now has the carry out that must be added into the most significant byte addition Get most sig byte ldaa does not change the carry ldaa Datal Add most significant plus carry adca Data2 std Data3 Stores 16 bits Data SECTION Datal dsw 1 Data2 dsw 1 Data3 dsw 1 ECE 4436 Logic Instructions TABLE 713 Logic Inslruchons Addressing Modes Condition Codes I D E I I I Symbolic M I x D D N Function Opcode Operation M R T x R H N 2 v AND A viIII Memory ANDA A AND MI A x x x 1 1 0 AND B wile McInnr AND M a B x x x x x 1 1 0 AND CCR wuh Mammy ANDCC CCR AND dum gt CCR x 1 1 1 5ch A wIIh Mammy ORA A EOR M gt A x x x x x 1 1 0 ch R B wim Mammy EORR B EOR M gtB x x A x 1 1 0 Inclusive OR A wuh Mammy ORAA A UR MI 9 A x x x x x 1 1 o Inclusive on B wim Mzmury ORAB B on AM gt B x x x x x 1 1 n Inclmivc OR CCR wiIII Cnnslam ORCC CCR 0R dalaa CCR x T 1 1 Onc39srComplcmcm Memory COM M H gt x x x 1 1 0 0n plcmcnl A OMA lt gt A x 1 1 0 0m 3 Cmnplcmcnl R COMB B r B k 1 1 0 Example 738 Logic Operations 1139 memory location 0010 contains 133 and A contains 64 what is the result 011110 following instructions anda 10 anda 310 oraa 10 Grad 310 area 10 coma com 10 Treat each instruction as an indepcndcnt scpax alc instruction not a sequence 0139 instructionst Solution anda 10 A 0110 0100 0010 1011 0011 0010 0000 anda 11810 A 0110 0100 10 0001 0000 0000 0000 oraa 10 A 0110 0100 0010 1011 0011 1111 0111 oraa 1310 A 0110 0100 s10 0001 0000 0111 0100 eora S10 A 0110 0100 0010 1011 0011 1101 0111 ECE 4436 Data Test Instructions TABLE 7 15 Data Test Instructions Addressing Modes Condition Codes I D E l Symbulic M x D n Funclinn Opcode Operation M R T x n N 2 v c Tcltt Bils in A mm A AND M x x x x x I I n s Tact Bits n BITB B AND M x x x x I I 0 7 minimc A n B CBA r B I I I I CIillpm e A In Memory CMPA A 7 Mi x x x x x I I I I Compare B m Munory CMI B B 7 Mi x x x x I I I I Compare D lo Memory 164m CPD D 1M M 1i x x x x x I I I I mm x m Mmuoryll rhil CPX x 7 1M M Ii x x x x x I I I I ompnic Y m Mammy i llbIU CPY Y 7 AM M 1i x x x x x I I I I Com me 5 lo Memo y 164m CPS s s M M ii 1 x x x x I I I I Tesi Memory ior Zen or Ncgulivc TST M 0 x x x I I o 0 Tesl A im 2m or Negalive TSTA A s o I I 0 0 Tax B in Zcmm Negative TSTB B r I I I 0 0 ECE 4436 Conditional Branch Instructions TABLE 726 Conditional Branch Instructions for Signed and Unsigned Data Signed Data Tests Universal Tests BM wmmwwmw Drorltlt1 c m lnml m 11 Q BNI M inns Plus Two x39rcnmpicmcm over ow No vo srcomplcmcnl over ow Lu llmn Greater ihan or equal Lash than or cqual Giealsr ilmn quail N01 equal wmwu r zrn won cow in o cigncdowr ow recs Cm rysct o ovcr ow scc Can y clear BEQ uHI BNE Nui Equal ECE 4436 Signed vs Unsigned Comparisons Consider two 8bit quantities FE and 01 If they are being used as unsigned numbers FE is 254 254 gt 1 FE gt 01 bhi blo bhs bls will give correct sense If they are being used as signed numbers FE is 2 2 lt 1 FE lt 01 bgt blt bge ble will give correct sense Example 741 Conditional Branches Assume the A FF and memory location DATA 00 A cmpa data instruction in exc cuted followed by a conditional branch For each of the conditional branch instructions in the table indicate by yes or no if you expect the branch to be taken and why BGE BLE BGT BLT BEQ BNE BHS BLS BHl BLO Solution Branch Taken Reason BGE No FF 1 Not greater than or equal to 00 BLE Yes FF i I Is less than or equal to 00 BUT NO FF I Is not greater than 00 BLT Yes FF i l S less than 00 BEQ No FF is not equal to 00 BNE Yes FF is not equal to 00 BHS Yes FF 255 Is higher than 00 BLS N0 FF 255 ls not lower or the same as 00 BHI Yes FF 255 Is higher than 00 BLO No FF 255 Is not lowcr than 00 Example 742 BRSET and BRCLR Instructions code Source line 11 12 13 14 15 000000 000004 000005 000009 0000 0000 0000 1F02 FB 1E02 EB 0080 0040 0240 4080 4040 XDEF Entry Entry main BIT7 EQU BIT6 EQU PORTT EQU WHILE Bit7 become one waitfor7 brclr WHILE Bit6 become zero waitfor6 brset main 10000000 Mask for 01000000 Mask for 240 Address for Port T is zero wait for it to PORTTBIT7waitfor7 wait for it to is one PORTTBIT6waitfor6 ECE 4436 Loop Primitive Instructions TABLE 718 Loop Primitive Instructions Addressing Condition Modes Codes R Symbolic E Function 0pcode Operation L N Z V Dch and Branch 0 DBEQ Reg gt Reg Branch il39ZcrO x Dccr and Branch ltgt 0 DBNE Reg 7 l gt ch Branch if not Zcro x incr and Branch 0 BBQ Reg i gt Reg Branch il39Zcro x Incr and Branch ltgt 0 YBNE Rc I v gt ch Branch if not Zero x i i Test and Branch 0 TBEQ m x i i Test and Branch 0 0 TBNE Test Reg Branch ifnot Zero x i i Example 743 Loop Primitive Instruction code Source line 000000 000003 000006 000008 000009 0000 0000 CE03 0435 C6FF 53 26FD 03E8 COUNTl I u I Comparing loop primitive and quotnormalquot decrement and branch instructions EQU 00FF COUNTZ EQU E8 FD I u I u I u I u I loop ldx Here is the dbne Demonstrate ldab loop2 I u I Here is the decb bne 1000 Counter value 255 Max 8 bit counter COUNTl Initialize counter repetitive code xloop Using dbne instr 8 bit decr then branch COUNTZ Initialize counter repetitive code loop2 TABLE 719 Unconditional Jump and Branch Instructicns ECE 4436 Unconditional Jump and Branch Addressing Mades Condition Cudes n D E I I I Symbolic E l x u D N Function cpcode Operation L R T x F H 2 v Jump mAdmm IMP ISA r PC x x x 7 7 ump m Suhmulinu ISR FA 77 PC x x x x 7 7 Branch m Subruulinc BSR EA a PC x 7 7 Call Suhroulinc CALL x x x 7 7 Relum from Submutine RTS EA 9 PC x Rcmm rrom Call TC x 7 7 Blanch Always RA x 7 7 LBRA x 7 7 Brunch chl BRN x 7 7 LBRN x 7 7 ECE 4436 721 Conclusion and Chapter Summary Points j


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