Microprocessor Systems ECE 4436
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This 19 page Class Notes was uploaded by Karolann Wiegand on Saturday September 19, 2015. The Class Notes belongs to ECE 4436 at University of Houston taught by Staff in Fall. Since its upload, it has received 26 views. For similar materials see /class/208305/ece-4436-university-of-houston in Electrical Engineering at University of Houston.
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Date Created: 09/19/15
DOCUMENT NUMBER S1ZSCIV2lD HCS12 Serial Communications Interface SCI Block Guide V0208 Original Release Date 29 Oct 2001 Revised 16 Apr 2004 816 Bit Division TSPG Motorola Inc Motorola reserves the right to make changes without further notice to any products herein rmre mia nn o 39 suitability of its n ran r disclaims including without limitation consequential or incidental damages Typical parameters which may be provided in Motorola data sheets andor speci cations can and do vary in different applications and actual performance may vary over time All operating parameters including quot I ypicals must be validated for each customer application by customer s L 39 l 39 39 39 39 39 intended 39 39 39 39 39 39 utuei 39 39 39 otuei 39 could create a situation where personal injury or death may occur should Buyer purchase or use an 39 39 39 n i l indemnify and hold Motorola and its of cers employees subsidiaries af liates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim ofpersona injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola and i it are registered trademarks of Motorola Inc Motorola Inc is an Equal OpportunityAf rmative Action Employer Motorola Inc 2001 m 1 Block Guide S1ZSCIV2lD V0208 Revision History Date Author Description of Changes 09011999 on change request 10221999 rupt signals from SCI 01252000 base reVIew 02012000 SCISR2 bit 1 04022001 rules 07192001 names Names and Variable definitions have been hidden 10102001 replace the STAR12 by H0812 03072002 Removed document order from Sheet source 06242002 error in section 43 USB 11152002 MHZ 041 62004 SCI Block Guide V0208 Table of Contents Section 1 Introduction 11 Overview 11 12 Features 11 13 Modes of Operation 12 Section 2 External Signal Description 21 Overview 13 22 Detailed Signal Descriptions 13 221 TXD SCI Transmit Pin 13 222 RXDSCI Receive Pin 13 Section 3 Memory MapRegister Definition 31 Overview 13 32 Module Memory Map 13 33 Register Descriptions 14 331 SCI Baud Rate Registers 14 332 SCI Control Register1 15 333 SCI Control Register2 17 334 SCI Status Register1 18 335 SCI Status Register 2 21 336 SCI Data Registers 21 Section 4 Functional Description 41 General 22 42 Data Format 23 43 Baud Rate Generation 24 44 Transmitter 26 441 Transmitter Character Length 26 442 Character Transmission 26 443 Break Characters 28 444 Idle Characters 28 45 Receiver 29 451 Receiver Character Length 30 uo ro ou 5 SCI Block Guide V0208 452 Character Reception 30 453 Data Sampling 30 454 Framing Errors 34 455 Baud Rate Tolerance 34 4551 Slow Data Tolerance 35 4552 Fast Data Tolerance 36 456 Receiver Wakeup 36 4561 Idle input line wakeup WAKE 0 37 4562 Address mark wakeup WAKE 1 37 46 SingleV re Operation 37 47 Loop Operation 38 Section 5 nitializationApplication Information 51 Reset Initialization 39 52 Modes of Operation 39 521 Run Mode 39 522 Wait Mode 39 523 Stop Mode 39 53 Interrupt Operation 39 531 System Level Interrupt Sources 39 532 Interrupt Descriptions 40 533 TDRE Description 40 534 TC Description 40 535 RDRF Description 40 536 OR Description 40 537 IDLE Description 41 538 Recovery from Wait Mode 41 6 MOTOROLA SCI Block Guide V0208 List of Figures Figure 11 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 410 Figure 411 Figure 412 Figure 413 SCI Block Diagram 11 SCI Register Quick Reference 14 SCI Baud Rate Registers SCI BDHL 15 SCI Control Register1 SCICR1 15 SCI Control Register2 SCICR2 17 SCI Status Register1 SCISR1 18 SCI Status Register 2 SCISR2 21 SCI Data Registers SCIDRHL 22 SCI Block Diagram 23 SCI Data Formats 24 Transmitter Block Diagram 26 SCI Receiver Block Diagram 29 Receiver Data Sampling 30 Start Bit Search Example 1 32 Start Bit Search Example 2 32 Start Bit Search Example 3 33 Start Bit Search Example 4 33 Start Bit Search Example 5 34 Start Bit Search Example 6 34 Slow Data 35 Fast Data 36 SCI Block Guide V0208 SCI Block Guide V0208 List of Tables Table 31 Module Memory Map 13 Table 32 Loop Functions 16 Table 42 Example of 9Bit Data Formats 24 Table 41 Example of 8bit Data Formats 24 Table 43 Baud Rates Example Module Clock 25MHz 25 Table 44 Start Bit Veri cation 31 Table 45 Data Bit Recovery 31 Table 46 Stop Bit Recovery 31 Table 51 SCI Interrupt Source 39 SCI Block Guide V0208 Block Guide S1ZSCIV2lD V0208 Preface The SCI allows full duplex asynchronous serial communication between the CPU and remote devices including other CPUs The SCI transmitter and receiver operate independently although they use the same baud rate generator The CPU monitors the status of the SCI writes the data to be transmitted and processes received data Terminology IRQ Interrupt Request LSB Least Signi cant Bit MSB Most Signi cant Bit NRZ NonRetumtoZero RZI RetumtoZeroInverted RXD Receive Pin SCI Serial Communication Interface TXD Transmit Pin Block Guide S1ZSCIV2lD V0208 Block Guide S1ZSCIV2lD V0208 Section 1 Introduction This block guide provide an overview of Serial Communication Interface SCI module Figure 11 is a high level block diagram of the SCI module showing the interaction of various function blocks SCI Data Register IDLE RX Data In IRQ RDRFOR Bus Clk IRQ D O m R U o I gt F BAUD g S Generator T TDRE IRQ Transmit Shift Register TC IRQ SCI Data Reg1ster gt TXData Out Figure 11 SCI Block Diagram 1 1 Overview The SCI allows asynchronous serial communications with peripheral devices and other CPUs 1 2 Features The SCI includes these distinctive features Fullduplex operation Standard marldspace nonretumtozero NRZ format Block Guide S1ZSCIV2lD V0208 13 13bit baud rate selection Programmable 8bit or 9bit data format Separately enabled transmitter and receiver Programmable transmitter output parity Two receiver wake up methods 7 Idle line walkup 7 Address mark walkup Interruptdriven operation with eight ags 7 Transmitter empty 7 Transmission complete 7 Receiver full 7 Idle receiver input 7 Receiver overrun 7 Noise error 7 Framing error 7 Parity error Receiver framing error detection Hardware parity checking 116 bittime noise detection Modes of Operation The SCI functions the same in normal special and emulation modes It has two low power modes wait ant stop modes Run Mode Wait Mode Stop Mode Section 2 External Signal Description Block Guide S1ZSCIV2ID V0208 21 Overview The SCI module has a total of 2 external pins 22 Detailed Signal Descriptions 221 TXD SCI Transmit Pin This pin serves as transmit data output of SCI 222 RXDSCI Receive Pin This pin serves as receive data input of the SCI Section 3 Memory MapRegister Definition 31 Overview This section provides a detailed description of all memory and registers 32 Module Memory Map The memory map for the SCI module is given below in Table 31 The Address listed for each register is the address offset The total address for each register is the sum of the base address for the SCI module and the address offset for each register Table 31 Module Memory Map Block Guide S1ZSCIV2lD V0208 Register Quick Reference Register name Bit 7 6 5 4 3 2 1 Bit 0 gs SCIBDH Reilde SBR12 I SBR11 I SBR10 I SBRQ I SBRS I 0 Write Read SCIBDL Write SBR7 I SBR6 I SBRS I SBR4 I SBR3 I SBR2 I SBR1 I SBRO I 1 Read SCICR1 Write LOOPS ISCISWAII RSRC I M I WAKE I ILT I PE I PT I 2 SCICRZ Reid TIE I TCIE I RIE I ILIE I TE I RE I vau I SBK I 3 Write smsm ReedI TDRE TC RDRF IDLE OR NF FE PF 4 erte SCISRZ Reilde 0 I 0 I 0 I 0 I 0 I BRK13 I TXDIR RAF 5 WriteI I I I I I Read R8 0 0 0 0 0 0 SCIDRH I I T8 6 ertei Readzl R7 R6 R5 R4 R3 R2 R1 R0 SC39DRL WriteI T7 T6 T5 T4 T3 T2 T1 T0 7 II Reserved or unimplemented Figure 31 SCI Register Quick Reference 33 Register Descriptions This section consists of register descriptions in address order Each description includes a standard register diagram with an associated gure number Writes to a reserved register location do not have any effect and reads of these locations return a zero Details of register bit and eld function follow the register diagrams in bit order 331 SCI Baud Rate Registers Register address 0 7 6 5 4 3 2 1 0 I it I 0 I 0 I 0 I SBR IZ I SBR I I I SBR IO I SBRQ I SBRS I RESET 0 0 0 0 0 0 0 0 II Unimplemented or Reserved Block Guide S1ZSCIV2lD V0208 Register address 1 7 6 5 4 3 2 1 0 SBR7 SBR6 l SBRS SBR4 l SBR3 SBRZ l SBR I SBRO l RESET 0 0 0 0 0 1 0 0 l Unimplemented or Reserved Figure 32 SCI Baud Rate Registers SCI BDHL The SCI Baud Rate Register is used by the counter to determine the baud rate of the SCI The formula for calculating the baud rate is SCI baud rate SCI module clock 16 X BR where BR is the content of the SCI baud rate registers bits SBR12 through SBRO The baud rate registers can contain a value from 1 to 8191 Read anytime If only SCIBDH is written to a read will not return the correct data until SCIBDL is written to as well following a write to SCIBDH Write anytime SBR12 SBRO SCI Baud Rate Bits The baud rate for the SCI is determined by these 13 bits NOTE The baud rate generator is disabled until the TE bit or theRE bit is set for the first time after reset The baud rate generator is disabled when BR 0 NOTE Writing to SCIBDH has no ef ect without writing to SCIBDL since writing to SCIBDH puts the data in a temporary location until SCIBDL is written to 332 SCI Control Register 1 Register address 2 7 6 5 4 3 2 1 0 5V LOOPS SCISWAI l RSRC M l WAKE ILT PE PT I RESET 0 0 0 0 0 0 0 0 l Unimplemented or Reserved Figure 33 SCI Control Register 1 SCICR1 Read anytime mnou 15 Block Guide S1ZSCIV2lD V0208 Write anytime LOOPS Loop Select Bit LOOPS enables loop operation In loop operation the RXD pin is disconnected from the SCI and the transmitter output is internally connected to the receiver input Both the transmitter and the receiver must be enabled to use the loop function 1 Loop operation enabled 0 Normal operation enabled The receiver input is determined by the RSRC bit SCISWAI 7 SCI Stop in Wait Mode Bit SCISWAI disables the SCI in wait mode 1 SCI disabled in wait mode 0 SCI enabled in wait mode RSRC 7 Receiver Source Bit When LOOPS l the RSRC bit determines the source for the receiver shift register input 1 Receiver input connected externally to transmitter 0 Receiver input internally connected to transmitter output Table 32 Loop Functions M 7 Data Format Mode Bit MODE determines whether data characters are eight or nine bits long 1 One start bit nine data bits one stop bit 0 One start bit eight data bits one stop bit WAKE 7 Wakeup Condition Bit WAKE determines which condition wakes up the SCI a logic 1 address mark in the most signi cant bit position of a received data character or an idle condition on the RXD l Address mark wakeup 0 Idle line wakeup ILT 7 Idle Line Type Bit ILT determines when the receiver starts counting logic ls as idle character bits The counting begins either after the start bit or after the stop bit If the count begins after the start bit then a string of logic ls preceding the stop bit may cause false recognition of an idle character Beginning the count after the stop bit avoids false idle character recognition but requires properly synchronized transmissions l Idle character bit count begins after stop bit 0 Idle character bit count begins after start bit Block Guide S1ZSCIV2lD V0208 PE 7 Parity Enable Bit PE enables the parity function When enabled the parity function inserts a parity bit in the most signi cant bit position 1 Parity function enabled 0 Parity function disabled PT 7 Parity Type Bit PT determines whether the SCI generates and checks for even parity or odd parity With even parity an even number of ls clears the parity bit and an odd number of ls sets the parity bit With odd parity an odd number of ls clears the parity bit and an even number of ls sets the parity bit 1 Odd parity 0 Even parity 333 SCI Control Register 2 Register address 3 7 6 5 4 3 2 1 0 5V TIE TCIE l RIE ILIE l TE RE I RWU SBK l RESET 0 0 0 0 0 0 0 0 l Unimplemented or Reserved Figure 34 SCI Control Register 2 SCICRZ Read anytime Write anytime TIE 7 Transmitter Interrupt Enable Bit TIE enables the transmit data register empty ag TDRE to generate interrupt requests 1 TDRE interrupt requests enabled 0 TDRE interrupt requests disabled TCIE 7 Transmission Complete Interrupt Enable Bit TCIE enables the transmission complete ag TC to generate interrupt requests 1 TC interrupt requests enabled 0 TC interrupt requests disabled RIE 7 Receiver Full Interrupt Enable Bit RIE enables the receive data register full ag RDRF or the overrun ag OR to generate interrupt requests 1 RDRF and OR interrupt requests enabled 0 RDRF and OR interrupt requests disabled ILIE 7 Idle Line Interrupt Enable Bit mnou l7 Block Guide S1ZSCIV2lD V0208 ILIE enables the idle line ag IDLE to generate interrupt requests 1 IDLE interrupt requests enabled 0 IDLE interrupt requests disabled TE 7 Transmitter Enable Bit TE enables the SCI transmitter and con gures the TXD pin as being controlled by the SCI The TE bit can be used to queue an idle preamble l Transmitter enabled 0 Transmitter disabled RE 7 Receiver Enable Bit RE enables the SCI receiver 1 Receiver enabled 0 Receiver disabled RWU 7 Receiver Wakeup Bit Standby state 1 RWU enables the wakeup function and inhibits further receiver interrupt requests Normally hardware wakes the receiver by automatically clearing RWU 0 Normal operation SBK 7 Send Break Bit Toggling SBK sends one break character 10 or 11 logic 0s respectively 13 or 14 logics 0s if BRKl3 is set Toggling implies clearing the SBK bit before the break character has nished transmitting As long as SBK is set the transmitter continues to send complete break characters 10 or 11 bits respectively 13 or 14 bits 1 Transmit break characters 0 No break characters 334 SCI Status Register 1 The SCISRl and SCISR2 registers provides inputs to the MCU for generation of SCI interrupts Also these registers can be polled by the MCU to check the status of these bits The agclearing procedures require that the status register be read followed by a read or write to the SCI Data Register It is permissible to execute other instructions between the two steps as long as it does not compromise the handling of IO but the order of operations is important for ag clearing Register address 4 7 6 5 4 3 2 1 0 R TDRE TC RDRF IDLE OR NF FE PF W RESET 1 1 0 0 0 0 0 0 I Unimplemented or Reserved Figure 35 SCI Status Register 1 SCISR1
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