### Create a StudySoup account

#### Be part of our community, it's free to join!

Already have a StudySoup account? Login here

# COMPUTER ARCHITECTURE CSC 4210

GSU

GPA 3.62

### View Full Document

## 5

## 0

## Popular in Course

## Popular in ComputerScienence

This 14 page Class Notes was uploaded by Mallie Crist on Monday September 21, 2015. The Class Notes belongs to CSC 4210 at Georgia State University taught by Staff in Fall. Since its upload, it has received 5 views. For similar materials see /class/209899/csc-4210-georgia-state-university in ComputerScienence at Georgia State University.

## Reviews for COMPUTER ARCHITECTURE

### What is Karma?

#### Karma is the currency of StudySoup.

#### You can buy or earn more Karma at anytime and redeem it for class notes, study guides, flashcards, and more!

Date Created: 09/21/15

Chapter 3 Data Representation Section 31 Data Types Registers contain either data or control information Control information is a bit or group of bits used to specify the sequence of command signals needed for data manipulation 0 Data are numbers and other binarycoded information that are operated on Possible data types in registers 0 Numbers used in computations 0 Letters of the alphabet used in data processing 0 Other discrete symbols used for specific purposes 0 All types of data except binary numbers are represented in binarycoded form 0 A number system of base or radix r is a system that uses distinct symbols for r digits 0 Numbers are represented by a string of digit symbols The string of digits 7245 represents the quantity 7x1022x1014x1005x10391 o The string of digits 101101 in the binary number system represents the quantity 1x250x24lx231x220x21lx2045 101101z 4510 We will also use the octal radix 8 and hexidecimal radix 16 number systems 73648 7 x 82 3 x 81 6 x 80 4 X 81 478510 F316 F x 161 3 x160 24310 0 Conversion from decimal to radix r system is carried out by separating the number into its integer and fraction parts and converting each part separately Divide the integer successively by r and accumulate the remainders Multiply the fraction successively by r until the fraction becomes zero Computer Architecture Chapter 3 Figure 31 Conversion of decimal 4116875 into binary Integer 4 Fraction 06875 4 06875 20 I 10 0 13750 5 0 x Z 2 1 07500 1 0 x 2 0 1 15000 x 2 10000 41 lOlOOl 0687510O1012 416875l l010010l I Each octal digit corresponds to three binary digits Each hexadecimal digit corresponds to four binary di 39ts Rather than specifying numbers in binary form refer to them in octal or hexadecimal and reduce the number of digits by 13 or lA respectively 010111101100011 Binary A F 6 3 FL 2 7 5 4 3 Octal Hexadecimal Figure 3L Binary Octal and hexadecimal conversion Computer Architecture pter 3 TABLE 31 Binary Coded Octal Numbers Octal Binarycoded Decimal number Octal equivalent 0 000 0 1 001 1 2 010 2 Code 3 011 3 for one 4 100 4 Octal 5 101 5 digit 6 110 6 7 111 7 1 10 001 000 8 11 001 001 9 12 001 010 10 24 010 100 20 62 110 010 50 143 001 100 011 99 370 011 111 000 248 Computer Architecture pter 3 TABLE 3 2 Binary Coded Hexadecimal Numbers Hexadecimal Binarycoded Decimal number hexadecimal equivalent 0 0000 0 1 0001 1 2 0010 2 3 0011 3 4 0100 4 5 0101 5 6 0110 6 Code 7 0111 7 8 1000 8 hexadecimal 9 1001 9 di t A 1010 10 B 1011 11 C 1100 12 D 1101 13 E 1110 14 F 1111 15 14 0001 0100 20 32 0011 0010 50 63 0110 0011 99 F8 1111 1000 248 A binary code is a group of n bits that assume up to 2quot distinct combinations A four bit code is necessary to represent the ten decimal digits 7 6 are unused The most popular decimal code is called binarycoded decimal BCD BCD is different from converting a decimal number to binary For example 99 when converted to binary is 1100011 99 when represented in BCD is 1001 1001 Computer Architecture pter 3 TABLE 3 Binary Coded Decimal BCD Numbers Decimal Binarycoded decimal number BCD number 0 0000 l 1 0001 l 2 0010 3 0011 Code 4 0100 for one 5 0101 decimal 6 0110 digit 7 0111 8 1000 i 9 1001 1 10 0001 0000 20 0010 0000 50 0101 0000 99 1001 1001 248 0010 0100 1000 The standard alphanumeric binary code is ASCII This uses seven bits to code 128 characters Binary codes are required since registers can hold binary information only Computer Architecture pter 3 TABLE 34 American Standard Code for Information Interchange ASCII Bi 3 Binary Character code Character code A 100 0001 0 011 0000 B 100 0010 1 011 0001 C 100 0011 2 011 0010 D 100 0100 3 011 0011 E 100 0101 4 011 0100 F 100 0110 5 011 0101 G 100 0111 6 011 0110 H 100 1000 7 011 0111 I 100 1001 8 011 1000 I 100 1010 9 011 1001 K 100 1011 L 100 1100 M 100 1101 space 010 0000 N 100 1110 010 1110 O 100 1111 010 1000 P 101 0000 010 1011 Q 101 0001 010 0100 R 101 0010 010 1010 S 101 0011 010 1001 T 101 0100 010 1101 U 101 0101 010 1111 V 101 0110 010 1100 W 101 0111 011 1101 X 101 1000 Y 101 1001 Z 101 1010 Section 32 Complements Complements are used in digital computers for simplifying subtraction and logical manipulation Two types of complements for each base r system r s complement and r 7 1 s complemen Given a number N in base r having n digits the r 7 1 s complement of N is de ned as rquot 7 1 7N For decimal the 9 s complement ofNis 10quot 7 1 7N o The 9 s complement of546700 is 999999 7 546700 453299 Computer Architecture 6 pter 3 The 9 s complement of 453299 is 999999 7 453299 546700 For binary the 1 s complement ofN is 2quot 7 1 7N The 1 s complement of 1011001 is 1111111 7 1011001 0100110 The 1 s complement is the true complement of the number 7 just toggle all bits The r s complement of an n digit numberNin base r is de ned as r 1 7N This is the same as adding 1 to the r 7 1 s complement The 10 s complement of2389 is 7610 1 7611 The 2 s complement of 101100 is 010011 1 010100 Subtraction of unsigned n digit numbers M 7N o AddM to the r s complement of N 7 this results in Mr l7NM7Nr 1 o IfM Z N the sum will produce an end carry I 1 which is discarded 0 If M lt N the sum does not produce an end carry and is equal to rquot 7 N 7M which is the r s complement of N 7M To obtain the answer in a familiar form take the r s complement of the sum and place a negative sign in front Example 72532 7 13250 59282 The 10 s complement of 13250 is 86750 M 10 s comp ofN Sum Discard end carry Answer 7 72352 86750 159282 100000 59282 Example for M lt N 13250 7 72532 59282 M 10 s comp ofN Sum No end carry Answer 13250 27468 40718 59282 10 s comp of 40718 Example for X 1010100 and Y 1000011 X 2 s comp on Sum Discard end carry Answer X 7 Y Y 2 s comp ofX Sum Computer Architecture Chapter 3 7 1010100 0111101 10010001 10000000 0010001 1000011 0101100 1101111 No end carry Answer 0010001 2 s comp of 1101111 Section 33 Fixed Point Representation Positive integers and zero can be represented by unsigned numbers Negative numbers must be represented by signed numbers since and 7 signs are not available only 1 s and 0 s are 0 Signed numbers have msb as 0 for positive and 1 for negative 7 msb is the sign bit 0 Two ways to designate binary point position in a register 0 Fixed point position 0 Floatingpoint representation 0 Fixed point position usually uses one of the two following positions 0 A binary point in the extreme left of the register to make it a fraction 0 A binary point in the extreme right of the register to make it an integer o In both cases a binary point is not actually present 0 The oatingpoint representations uses a second register to designate the position of the binary point in the first register 0 When an integer is positive the msb or sign bit is 0 and the remaining bits represent the magnitude 0 When an integer is negative the msb or sign bit is 1 but the rest of the number can be represented in one of three ways 0 Signedmagnitude representation 0 Signed1 s complement representation 0 Signed2 s complement representation 0 Consider an 8bit register and the number 14 0 The only way to represent it is 00001110 0 Consider an 8bit register and the number 714 o Signed magnitude 1 0001110 0 Signed 1 s complement 1 1110001 0 Signed 2 s complement 1 1110010 0 Typically use signed 2 s complement 0 Addition of two signedmagnitude numbers follow the normal rules 0 If same signs add the two magnitudes and use the common sign 0 Differing signs subtract the smaller from the larger and use the sign of the larger magnitude 0 Must compare the signs and magnitudes and then either add or subtract 0 Addition of two signed 2 s complement numbers does not require a comparison or subtraction 7 only addition and complementation 0 Add the two numbers including their sign bits 0 Discard any carry out of the sign bit position 0 All negative numbers must be in the 2 s complement form 0 If the sum obtained is negative then it is in 2 s complement form Computer Architecture 8 Chapter 3 6 00000110 6 11111010 13 00001101 13 00001101 19 00010011 7 00000111 6 00000110 6 11111010 13 11110011 13 11110011 7 11111001 19 11101101 0 Subtraction of two signed 2 s complement numbers is as follows 0 Take the 2 s complement form of the subtrahend including sign bit 0 Add it to the minuend including the sign bit 0 A carry out ofthe sign bit position is discarded 0 An over ow occurs when two numbers of 71 digits each are added and the sum occupies n 1 digits Over ows are problems since the width of a register is nite Therefore a ag is set if this occurs and can be checked by the user Detection of an over ow depends on if the numbers are signed or unsigned For unsigned numbers an over ow is detected from the end ca1ry out of the msb For addition of signed numbers an over ow cannot occur if one is positive and one is negative both have to have the same sign An over ow can be detected ifthe carry into the sign bit position and the carry out of the sign bit position are not equal 70 0 1000110 70 1 0111010 80 0 1010000 80 1 0110000 150 1 0010110 150 0 1101010 The representation of decimal numbers in registers is a function of the binary code used to represent a decimal digit A 4bit decimal code requires four ip ops for each decimal digit This takes much more space than the equivalent binary representation and the circuits required to perform decimal arithmetic are more complex Representation of signed decimal numbers in BCD is similar to the representation of signed numbers in binary Either signed magnitude or signed complement systems The sign of a number is represented with four bits 0 0000 for o 1001 for To obtain the 10 s complement of a BCD number first take the 9 s complement and then add one to the least significant digit Example 375 240 135 Computer Architecture 9 Chapter 3 0 375 9 760 0 135 0000 0011 0111 1010BCD 1001 0111 0110 0000an 0000 0001 0011 0101BCD Section 34 Floating Point Representation The oatingpoint representation of a number has two parts The rst part represents a signed xedpoint number 7 the mantissa The second part designates the position of the binary point 7 the exponent The mantissa may be a fraction or an integer Example the decimal number 6132789 is 0 Fraction 06123789 o Exponent 04 0 Equivalent to 06132789 x 104 0 A oatingpoint number is always interpreted to represent m x re 0 Example the binary number 100111 with 8bit fraction and 6bit exponent 0 Fraction 01001110 0 Exponent 000100 0 Equivalent to 10011102 x 24 0 A oatingpoint number is said to be normalized if the most signi cant digit of the mantissa is nonzero The decimal number 350 is normalized 00350 is not The 8bit number 00011010 is not normalized Normalize it by fraction 11010000 and exponent 3 Normalized numbers provide the maximum possible precision for the oating point number Section 35 Other Biliary Codes 0 Digital systems can process data in discrete form only 0 Continuous or analog information is converted into digital form by means of an analogtodigital converter 0 The re ected binary or Gray code is sometimes used for the converted digital data 0 The Gray code changes by only one bit as it sequences from one number to the next 0 Gray code counters are sometimes used to provide the timing sequences that control the operations in a digital system Computer Architecture Chapter 3 TABLE 3 5 4Bit Gray Code Binary Decimal Binary Decimal code equivalent code equivalent 0000 0 1100 8 0001 1 1101 9 0011 2 111 1 10 0010 3 1110 11 0110 4 1010 12 0111 S 1011 13 0101 6 1001 14 0100 7 1000 15 Binary codes for decimal digits require a minimum of four bits 0 Other codes besides BCD exist to represent decimal digits Computer Architecture pter 3 TABLE 3 6 Four Different Binary Codes for the Decimal Digit Decimal BCD Excess3 digit 8421 2421 Excess3 gray 0 0000 0000 0011 0010 1 0001 0001 0100 0110 2 0010 0010 0101 0111 3 0011 0011 0110 0101 4 0100 0100 0111 0100 5 0101 1011 1000 1100 6 0110 1100 1001 1101 7 0111 1101 1010 1111 8 1000 1110 1011 1110 9 1001 1111 1100 1010 1010 0101 0000 0000 Unused 1011 0110 0001 0001 hit 1100 0111 0010 0011 combi 1101 1000 1101 1000 nations 1110 1001 1110 1001 1111 1010 1111 1011 The 2421 code and the excess3 code are both selfcomplementing The 9 s complement of each digit is obtained by complementing each bit in the c ode The 2421 code is a weightedcode The bits are multiplied by indicated weights and the sum gives the decimal digit 0 The excess3 code is obtained from the corresponding BCD code added to 3 Section 36 Error Detection Codes Transmitted binary information is subject to noise that could change bits 1 to 0 and vice versa 0 An error detection code is a binary code that detects digital errors during transmiss1on The detected errors cannot be corrected but can prompt the data to be retransmltte The most common error detection code used is the parity bit Computer Architecture pter 3 o A parity bit is an extra bit included With a binary message to make the total number of l s either odd or even TABLE 3397 Parity Bit Generation Message xyz Podd Peven 000 1 0 001 O 1 010 0 1 011 1 0 100 0 1 101 1 0 110 1 O 111 0 1 The Podd bit is chosen to make the sum of 1 s in all four bits odd The evenparity scheme has the disadvantage of having a bit combination of all 0 s Procedure during transmission 0 At the sending end the message is applied to a parity generator 0 The message including the parity bit is transmitted 0 At the receiving end all the incoming bits are applied to a parity checker 0 Any odd number of errors are detected Parity generators and checkers are constructed With XOR gates odd function An odd function generates 1 iff an odd number if input variables are 1 Computer Architecture 13 pter 3 Figure 33 Error detection with odd parity bit Source Destination x Error indication Parin generator Parity checker Computer Architecture Chapter 3

### BOOM! Enjoy Your Free Notes!

We've added these Notes to your profile, click here to view them now.

### You're already Subscribed!

Looks like you've already subscribed to StudySoup, you won't need to purchase another subscription to get this material. To access this material simply click 'View Full Document'

## Why people love StudySoup

#### "There's no way I would have passed my Organic Chemistry class this semester without the notes and study guides I got from StudySoup."

#### "I used the money I made selling my notes & study guides to pay for spring break in Olympia, Washington...which was Sweet!"

#### "There's no way I would have passed my Organic Chemistry class this semester without the notes and study guides I got from StudySoup."

#### "It's a great way for students to improve their educational experience and it seemed like a product that everybody wants, so all the people participating are winning."

### Refund Policy

#### STUDYSOUP CANCELLATION POLICY

All subscriptions to StudySoup are paid in full at the time of subscribing. To change your credit card information or to cancel your subscription, go to "Edit Settings". All credit card information will be available there. If you should decide to cancel your subscription, it will continue to be valid until the next payment period, as all payments for the current period were made in advance. For special circumstances, please email support@studysoup.com

#### STUDYSOUP REFUND POLICY

StudySoup has more than 1 million course-specific study resources to help students study smarter. If you’re having trouble finding what you’re looking for, our customer support team can help you find what you need! Feel free to contact them here: support@studysoup.com

Recurring Subscriptions: If you have canceled your recurring subscription on the day of renewal and have not downloaded any documents, you may request a refund by submitting an email to support@studysoup.com

Satisfaction Guarantee: If you’re not satisfied with your subscription, you can contact us for further help. Contact must be made within 3 business days of your subscription purchase and your refund request will be subject for review.

Please Note: Refunds can never be provided more than 30 days after the initial purchase date regardless of your activity on the site.