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# Power Electronics I ECE 562

CSU

GPA 3.8

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This 238 page Class Notes was uploaded by Sarina Wintheiser on Tuesday September 22, 2015. The Class Notes belongs to ECE 562 at Colorado State University taught by George Collins in Fall. Since its upload, it has received 45 views. For similar materials see /class/210281/ece-562-colorado-state-university in ELECTRICAL AND COMPUTER ENGINEERING at Colorado State University.

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Date Created: 09/22/15

LECTURE 26 Losses in Magnetic Devices Achieving acceptable loss levels in magnetic devices is the primary goal A Overview of Magnetic Device Losses B Faraday s and Lenz s Law 1Bmax in Cores from Faradays Law 2 Lenz Law and Its Implications for Induced Current Losses aSkin Effects in Copper Wires bEddy Current Effects in Various Core Materials C Magnetic Media BH Curves and Losses 1 Basics of 8H Curves The Saturation Catastrophe 2 Losses in Magnetic Media a Hysteresis Loss fBACm Core Volume b Eddy Current Loss f2Bac Core Volume 0 High f Ferrite Loss f3 Core Volume dSummary of Losses versus B and f FOR HWS 4 and 5 do the following HW4 Erickson Chapter 12 problems 6 and 8 and in class questions as well as lecture questions Hw 5 Erickson Chapter 13 problem 3 and in class questions as well as lecture questions LECTURE 26 Losses in Magnetic Devices A Overview of Magnetic Device Losses 1 General Situation Magnetic devices are composed of copper wires and magnetic core material Losses in magnetic devices occur both in the copper windings and in the magnetic core materials One or the other loss mechanism can dominate depending on the particulars of the magnetic device operating conditions Properly designed magnetic devices should add up to no more than 15 of the total losses in a switch mode electronics circuit Solid state device losses will contribute a similar amount Overall energy conversion efficiency should be 90 to 98 2 Copper Wire Losses a Skin Effects on an Isolated Single Wire The wire losses are IZR losses and the DC IZR levels are a baseline for comparison to losses at any other operating frequency The ISOLATED SINGLE wire resistance increases above DC levels by factors of 210 through skin effects for high frequency currents The resistance of the wire is a function of the frequency of the applied currentf in the wire and chosen the wire diameterD The larger the wire diameter the bigger the skin effect Roughly RAcwire RDcwire f 2 D For now we intuitively plot the current density in a wire versus wire radius for the case of DC currents through some high frequency current to visually see the trends prior to detailed mathematical analysis Moe For dc conditions J is uniform over the wire diameter as we expect J6O Hz Even at mains ac J 60 Hz h as a small dip in J near r 0 of 13 Why This is well known to increase AC 3 transmission line losses JMHz For MHZ currents J flows only at or near the surface of the wire No flow of r current at r 0 This makes 3 wires look 2100 times smaller We will see later in more detail how eddy currents in the copper wires induced by the time varying H field encircling the wire will alter J profiles as shown above to minimize total energy at the expense of increasing l2 R losses b Proximity Effects on Multiple Turns of Wire ln multiple turns of wire as we find on all practical magnetic devices each wire turn will have unique additional losses via proximity effects due to net H fields from all nearby wires For proximity effects the cooperative effect of the net magnetic fields generated by multiple turns of wire changes the resistive power losses in a particular wire turn in a different way even from the nearby wire turns Losses depend on the stray magnetic field from the magnetic device that passes through that individual wire turn This field and associated MMF will depend on the wire turn s location in the device usually within the air core window and also on the chosen winding configuration As we will see below proximity effects at AC frequencies alone can increase wire resisitivity by factors of 101000 3 Magnetic Core Losses There will be two components to core losses Both losses arise due to time varying magnetic fields inside the core The physical mechanisms of the two core losses are quite unique even though both are caused by the same time varying magnetic fields One is due to hysteresis loss in the 8H curve and it varies linearly with the frequency of the magnetic field variation The second loss is due to eddy currents induced in the core material and it varies as the square of the frequency and inversely as the electrical resisitivity of the core material the loss processes for magnetic devices are covered in detail in this lecture except proximity effects on resistivity changes for stacked turns of wire which are given in detail in lecture 28 B Faraday s and Lenz s Law Bmax in Cores from Faradays Law Faraday s law gave the voltage induced in an open loop of wire immersed in a time varying magnetic field as Vinduced N M dt NA dBdt for harmonic time varying fields at w V NA W B We can see that Vinduced causes current flow such that current out of the wire coil is from the terminal labeled We can work this backwards to find the maximum B inside a core when we apply a voltage V across the coils that are wrapped around the core This allows one to determine Bmax and compare it to the value of B531 for the specific core material to avoid the saturation disaster when Bmax exceeds Bsat From Faraday s law we find 3m Li W Where K is 444 for Sine waves239 2x2n and 4 for squarewavesetc N is the number of wire turns A is the crosssectional area of the core material f is the applied frequency 5 BmaX is also employed to nd the hysteresis core losses which depend on peak B elds in the core rather than the RMS valve of B Design paths and compromises to lower Bmax Values are clear 2 Lenz s Law and Its Implications to Magnetic Device Losses a Cu ent Loop Placing a CLOSED loop of wire in a time varying magnetic eld will induce a current in the wire to oppose the applied B eld as shown below This is the basis of electric motor des39 Lenz s Law Loo of horted ire in a t magnetic l39his corresponds to the situation in an electrical mot induced cunenl ir Ign ux eld or Induced i ow in the closed loop ofwire at one moment of time is such as to oppose the applied ux at that same moment as seen by the right hand rule induced flux dill b H Field Surrounding An Isolated Single Wire Next cun iuer 39 39 39 39 39 quot 39 frequency f owing through itA sinusoidal currenti creates a 1 circular magnetic H eld enclosing it The eld is moving in the 9 direction both within the wire an outside the wire Note also that the induced magnetic eld can not distinguish the solid wire 39om the air surrounding it Why Is the permeability of copper different from air 1f Since the permeability of air is indistinguishable from copper uwire uoair Current out of page toward you creates counterclockwise H field Hiil1 From Ampere s Law at time t tx Current into the page creates a clockwise H field The spatial variation of the H field with radial position for a constant current density versus wireradius is plotted below X E HdlI FromAmpere s Lawattimetty Does this above surrounding H field from a DC current around the wire have any effect on the current in the wire Note also that the H field penetrates into the wire itself Stay tuned and you will see amazing interactions between the H field and the current density distributions when we make the current an AC rather than a DC one Magnetic effects on currents and current distributions as we will unfold them will explain many unusual phenomena encountered in power electronics both in wires and in core materials For wires both skin and proximity effects have their root cause in H field effects The eddy currents that are induced in core materials via Lentz s law cause heating of the core and loss of energy A overview of field and electrical interactions is on page 7 CircuitsFields Faradayirlaw vw lt gt WNW Relations from cIrcuIt I v to the materials B H fields Ienmnal car chamnnmics characrznluics 39 lt gtHt t m Mmis on C Skin Effects and Current Distributions Across Wire Crosssections The H fields surrounding the wire have little effect on the insulating air surrounding the wire However these same H fields when they penetrate the conducting wire itself will cause the following chain of events that alters the current density distribution in the wire from a uniform one versus radial position to a non uniform distribution that pushes currents to the outer surface One wire with ac current flowing causes a magnetic field enclosing the wire In turn the time varying H field inside the wire causes additional current flow loops within the wire whose directions are revealed best by Amperes Law IHdl H2nr l Flow of it causes H t fields H t in turn causes elliptical voltages to appear in the wire which drive longitudinal elliptical eddy currents to oppose He t The eddy currents act to cancel out the applied current in the center of the wire but ADD at 39 the wire surface The induced eddy currents in the Cu wire act to enhance current flow at the edge of the wire but to reduce current flow at the center of the wire Looking at a wire crosssection better explains the net effect on the Jr profile Current flows in the paths that result in eddy currean the lowest expenditure of energy At low frequency this is simply accomplished by minimizing IZR losses only At high frequency however current flow also occurs in paths that involve inductive energy Now energy transfer to and from the magnetic field generated by the AC current flow must also be minimized Conservation of both resistive and inductive components causes high frequency current to flow nearer the surface of a large diameter wire conductor even though this may result in much higher IZR losses lfthere are several available paths HF current will take the paths that minimize inductive energy flow The circuit below shows an inductor in series with an LR transmission line What happens when a dc current is put through this circuit Do you get a minimum resistance Skin E ecr Model What happens when a high frequency ac current is put through Does the effective resistance increase due to the large inductive impedances Note that in the parallel combination of resistors the far right hand side Ri resistance s which correspond to the center of the wire are blocked by high inductive impedance at high frequencies The far left Ri resistances which correspond to the outer surface of the wire are left unblocked by the inductive effects The net effect on high frequency current distributions at center of the wire as f increases is to get zero net current Thus in a wire of radius a the current density profile Jr in units of Am2 will vary from dc to a new profile at low f ac to a different profile at high f ac This is the skin effect for a single isolated wire only Groups of wires wound in turns around cores will behave differently as the H elds each wire sees will also vary In summary t dc or low frequency ac energytransfer back and forth to the wire inductance Ll over time is trivial com pared to w r uniform lythrough the wire from the surface to the center to minimize thel R loss But at high frequency over the short time spans involved IZR loss is less than the energy transfer to and from L Current flow then concentrates near the surface even m 343 is a movement ofJ to the em outside dimensions ofthe wire Jltl l the spatial decay pattern ofthe current density J in the wire from e outer surface to the center of the wire Calculation of5 is Jr in wire r5 rm a L lt d gt Using wire resistivity and wire permeability constants for Cu wire media we find a crude RULE OF THUMB for Cu wires 75 cm 5 cu 100 C J Freguency 50 5 kHz 20 kHz 500 kHz 5 106 mm 106 mm 12 mm 0106 mm At 500kHz wires bigger than 01 mm in diameter will show skin efffects ln generaif d wire 5 2 5 skin depth we will not appreciably alter Jr in the small diameter wire by the skin effect as shown below This is the case for AC transmission lines at 50 60 Hz J constant across d no skin effects d Side comment on Skin Effects in modern Microelectronics Chips Due to small wire size in microelectronics chips typically less than one micron wide wires the skin effect is not an issue Consider possible skin effects in a new Intel pProcessor operating 1 GHz with copper interconnect wires At this frequency the copper skin depth is 5 GHz 075 microns 11 Thus only for those chip wires bigger than 15 microns in diameter skin effects will play a role Note this means there is no real benefit going to thicker than 2p copper metallization lines in the uProcessor wiring as one might do especially for high AC currents in wires DC power busses will still benefit from wider dimension wires For copper interconnect with wires around 15 microns we see a break point Below this value no skin effect occurs Above this value of wire line width BIG skin effects occur d lt 15 uwide signal bus d gt 15 uwide wire Rdc Rac RacgtgtRdc This is counter intuitive for some people who expect less skin effect problems for thicker wires lt reality it is just the opposite As a consequence a bundle of thin wires is the way to make a effective large diameter wire in macroelectronics as practiced in power electronics This low AC loss type of wire is commercially available and is termed LlTZ wire 345 strands of 35 wire in parallel strands are woven together Each strand of Litz has a diameter 200 microns Copper wires come in specific wire sizes For Cu wires the 5 vs f plots can be compared to the standard AWG and associated wire diameter to better see when d gt 25 occurs and skin effects are LARGE With these wires we interconnect the converter circuits containing solid state devices and magnetic devices An informative plot of skin depth versus frequency benefits greatly with horizontal notations of where the various wire sizes lie We don t want to specify a larger diameter wire to handle large currents only to find out a smaller diameter wire would do the job just as well Page 12 plots of 5 versus fwith wire diameter as a horizontal bar when 5 hits wire diameter helps one keep this relative size relationship in mind 12 Wu 1mm WZUAWG plncmznbn 4th 8 m some 40ch mm C Magnetic Materials BH Curves and Losses 1 asics he role of an ideal magnetic core is to transfer energy from one 55 free way First T 39 winding to another wire winding in a lo brief review of BH curves that includes saturation effects B W BC 4 H 2 w slope 7 Nnnrsa ate s n sailquot ww h losing saturaunn slaps washquot ldt which says that h lthN a1 loinmumsquot From Faraday s Law V N Hence the B or yaxis corresponds to lth the integral ofthe am a 39 H or w 39 39 r current in the wire coil so that electrically BH corresponds to lth 13 vs I For a series of wire turns wound around a wooden or paper form no BH saturation occurs and we only see the uo slope at all values of the 8H curve Using the fact 1Llth i a small BH slope corresponds to a small value inductance If we wish to make a bigger L in the same volume or the same L in a smaller volume then we employ a core magnetic material with ur gtgt 1 By winding turns around a high ur core the 8H slope rises by a factor ur and so does the inductance of wires wound around that core to applied voltages V In short that s why big inductors in a small volume require a magnetic media or core to be employed The price we may have to pay is nonlinear saturation effects That is big ur occurs only below 1critical or Hcritical At Hcritical we have reached Bsat of the chosen core and the L value decreases slope in saturation is uo H 0 Hr Isat BsatImHN 1 S Mr E 104 Below we plot typical values of 8881 for various cores as well as their low loss 1 frequency operation range 5060 Hz Cores High Frequency Cores CrFeSi Ni Zn l Powered Mn Zn Fe Ferrite 8881 l l l in 10 12 14 Tesla 60600 Hz 150 kHz 0100 to 1 MHz Note that while Bsat varies with material choice for the core 14 unfortunately Bsat for various cores only varies over ONE ORDER OF MAGNITUDE The science of high permeability cores needs further work to catch up to the needs of technology Common Materials choices and Manufacturers are listed below Care Materials Core Material Ferritesl Manufacturer lt100 kHz lt1 MHz j Magnetics Inc FTP F K N TDK P7C4 P7C40 Ferroxcube 3C8 3C85 Siemens N27 39 N67 Next we list practical guides to the actual BSAT limits in cores versus the frequency of the current in the coils wound around the core Note that in practice the full BH cuwe cannot be employed at higher frequenciesabove 1MHz due to excessive losses Flux Density limits vs Frequency Maximum Operational hirequency Flux Density Bmaxl lt50 kHz 053salt lt100 kHz 043sat lt500 kHz 0258sat lt1 MHz 018sat Elevated core temperatures due to heating effects will lower BSAT L l ml i Mi l 25 C 100 C l l l l l l l llA fIV fl uwv GAUSS E 1 000 25 0 25 50 100 150 200 250 H Am 39 39100 Nm is 125 oersted degradation of B with core tern erat 39 shown Courtesy of Philips Components sat p me 308 materia 15 The last big breakthrough in magnetics came in the move from iron to ferrites FeSi Ferrite Bsat 2 T Bsat rmax 103 rmax 106 Please note that the transition from SiFe cores to ferrites loses only 4 8881 but gains 105 in the frequency range of operation of the core Recall that ZL wL so if ZL counts more than just L we gain a lot more inductive impedance by choosing Ferrite cores operating at high frequency over traditional FeSi operating at 50 60 Hz for both transformers and inductors assuming equal core losses at the very different frequencies Get rich and invent a core material with large values of 8881 and low losses at high frequencieslike at 1356 MHz We need a new breakthrough for achieving high 8881 materials for employing high I inductors without saturation fears FOR HW5 COME UP WITH SOME WAYS to do so A good term paper would involve New METGLASS material 80 iron 20 glass Bsat z 34 Tesla a Inductor Considerations lnductor ZL ferrite z 105 difference in size required due ZL iron Si to operating frequency change For fixed ZL we could have an inductor 105 smaller in size and weight by choosing the proper core material that operates at the same total loss but at 105 higher frequency b Transformer Considerations Transformers on Different Cores V Ndltgtdt Nwltgt V MHZ z105 due to operating frequency V 60Hz This means for the same size applied voltage to one set of wire coils we could employ 10 5 less flux 4 in the core by operating at 105 higher frequency In short we can shrink the area of the core size weight by this same factor and still reach Vout on a second set of coils wound on the same core This allows spatially small size transformers to control large powers The above change in the operating frequency of magnetic materials was crucial to the shrink in the size of magnetic components over the past 20 years and in conjunction with the advances in solid state switches made kW supplies go from four drawer file cabinet size to shoe box size Clearly the advancements in magnetics as well as those in solid state switches both pace and limit the progress in switched mode power supplies that we have seen over the past decade and into the future In 14 kWcu 6322 quotWalt V SI ze v I PEBB amp g V 39 TECHNOLOGY Cost V 1 a 36 kWcu ll 3005Nuawlcu n K v 50Wau 39 I lntegr aled Power m 3 Conversion Center 5 o cu H t 39 SDGIWaH I V I y 19 10 Z I g 39 BJT 197Q s IGBT1990 NMC 100 39 3 39 i I gt 195018 I 20 k S witchi ng Frequency 70 kHz 2 Losses in Magnetic Cores a Overview Core loss is the second most important core limitation in most PWM converter applications after active switch losses Energy losses cause cores to heat up during operation Losses arise from both hysteresis effects and eddy currents ln metal alloy cores eddy current loss dominates above a few hundred Hertz but this is not the case for ferrites until much higher frequency For acceptable ferrite core losses flux density swing AB must be restricted to much less than Bsat which prevents the core from being utilized to its full capability At low frequencies ferrite core loss is almost entirely hysteresis loss For today s power ferrites operating at high frequency eddy current loss overtakes hysteresis loss at 200300kHz Core manufacturers usually provide curves showing core loss as a function of flux swing and frequency combining hysteresis and eddy current losses Core loss is usually expressed in mWcm3 sometimes in kWm3 actually equal 1mWcm3 1KWm3 Now lets discuss quantitatively two core losses hysteresis and eddy currents a Hysteresis Loss Here the fatness or thinness of the BH curve when excited by ac currents at frequency f is key This loss also depends on Bpeak not Baverage or BRMS Usually Loss varies as Bpeakm where m 23 B Power loss per volume PHfHdB area of 8H loop l H B H Large Hysteresis Loss Small HVStereSiS LOSS Notice also this loss occurs over each ac cycle so total loss is proportional to applied frequency f Total power Loss 2 lHB f Volume of Core energy loss per volume per cycle core material type and PlossHysteresis f core size Bac peak B peak is less if core area is bigger yet the total loss decreases as the core size gets smaller 80 optimum geometry s for cores that minimize total loss do exist These optimums will also have to include core cooling effects Circuit topology also effects the 8H curve For example how many quadrants of 8H are employed depends on whether the wire current that is wrapped around a core is unipolar or bipolar driven by the converter switches L in a forward converter for example is only in quadrant 1 of the 8H because the diode allows only unidirectional current Hence we expect higher B sat and losses may be bigger than for bipolar excitation where BSAT is lower B FonNard converter BH region limits Bacpeak H ipeak Clearly in a forward converter both the fSW and V9 choices also 19 effect the total loss via the E Alsec ramp time as set by choice of Tsvv This in turn sets the maximum current which effects lEdt Bpeak as shovm below We do not wish to exceed BEAT at any time a LuWEr rm or higher vv Higherfswurluvvervv t Note also it depends ifthere is a net dc current level that causes B to varyabout a quiescent BDc 39 n lLI mm in gem wiemthmmgiui m m W m lb ii m we LuWEr rm means a bigger 37H lump and more ieissesrreirh ysteresis unless eure size is ehahgeg as shown beluvv H Higherf srhaiier Eh lump Iszt E core and IN is the perimeter length of the chosen cor Lower V or Higher f means Smaller BaneASmaller Core Size 9 required for same total loss In summary we nd Physteresis K f Ba peak B gm Where N is the ofcopper wire turns around the Below we show data of loss versus Blpeak on a loglog scale so that an m value is a straight line Changing frequency changes the loss as shown In this case loss varies as f1 3 Physteresis loss is also limited by thermal heating which changes m to higher values at higher temperatures A rule of thumb is Tmax 100 200 C for the ferrite This uppertemperature is or similar to Tmax for safe semiconductor switch operation or for the wire insulation to remain undamaged Physteresis max is typicallyx 200 500 L3 cm 313 Farrquot 1N 21 Consider changing the operating ffrom 100 to 400 kHz on the wire current wound around 3F3 ferrite for use as an inductor core Start with 100 kHz and BEc 100 mT the power loss density in the core is P 60 mWcm3 By increasing operating f 600mW 01113 and not simply 4 times greater due to nonlinear core heating We repeat the warning that in Core Loss vs Flux Density curves the horizontal axis labeled Flux Density usually represents peak flux density ln applications peaktopeak flux swing AB is calculated from Faraday s Law where lEdt applied Voltseconds N turns and A0 core crosssectional area AB 1NAclV1dt The total flux swing AB is sometimes twice the peak flux swing referred to in the core loss curves as Flux Density if we choose unipolar versus bipolar core excitation Therefore use care to employ either AB2 or AB to enter into the core loss curves V to 400 KHz the power loss density is 10 greater P 1A 44 A high fsw low fSW AsideLater we will show that for transformers but not for inductors VA rating lt gt f BEc product transformer The fxBac product versus applied f peaks at a characteristic frequency unique to each magnetic material 3F4 Material is considered one of the best for high foperation as shown in the plot below where the productfxB peaks near1MHz One is reminded of the gain bandwidth product for electronic amplifiers This plot shows the fact that E3F4 material has 25 more Vl capability than 3010 n W mmquot M 4 l PM mm quotmm M All present ferrites have lowf B products above 2 MHZ MHZ is today s fswmax primarily due to magnetic materials limitations This is an area rIpe for a scientific breakthrough b Eddy Current Effects in Various Core Materials The eddy current core loss has entirely unique physical origins and acts in parallel with that associated with hysteresis loss 1 Overview By Faraday s law we induce a voltage loop in a core material with VNm This loop voltage induces a current via VRcore The electrical resistivity of the core material can vary adItional FeSi Ceramic Ferrite low p high p easy to induce bulk difficult to currents in the core induce eddy currents Which creates Mainly Only hysteresis eddy current loss I2R T loss occurs Most cores have both hysteresis and eddy current losses The resistivity of the core is crucial because magnetic fields that vary in time create an induced voltage in the core as shown below 23 This current owing in the core material causes losses as either VZR or IZR b The induced voltage in the core bulk by Faradays Law is V Nw for harmonic varying flux perpendicular to the core area The voltage is a circular potential causing circular currents to flow in the core as shown below Also loss goes as f for eddy currents ux Peddy current m iZR B W edd N 7 N 7 mini leddY N R R ir fZBZ cm Peddy loss R gt FeSI has bIg loss since Rcore is small Ferrite has low eddy current loss since Rferrite is arge Careful of ferrite resonance s lfyou put ferrite core on vector voltmeter to measure Zferrite you will find a Zmin at fresonance In general for ferrite p is large m So eddy current loss for a ferrite core is low except at ferroresonance One must know the resonant frequency for the ferrite core material you choose to work with Again low impedance means V R has a maximum At any rate at some applied frequency the eddy current loss which varies as f2 will exceed the hysteresis loss which varies as f This is shown on page 24 24 l R L l k i e Behavior 7 f At the material Ferro quot0 likequot resonance Z is reduced Behavior and eddy current losses increase from there expected form Zdc Ploss Physteresis Peddy current W Iowf high f hysteresis eddy current loss loss dominates foo fcrossover is typically 100 kHz At Iowf We can hysteresis dominates reduce eddy current by laminating the core to block eddy currents unless you use high p ferrite cores At very high fMHz Plossferrites f3 High Frequency Cores No high p ferrites exist with simultaneous high 8881 in the MHz 25 region 0 TDK H7C4 high fcores have 0 0 very small grain size 1 micron Erain boundary like an insulator Veddy f B ieddy At high frequency the If capacitance between grain boundaries cause displacement current flow notjust bulk resistivity R Then in a high frequency core to a first approximation if the C impedance between grains dominates Veddy Vinduced CV 23C 2 W W ieddy N 1 7 II R WC With V wB Peddy Veddy ieddy W3 In summary the total core loss from all magnetic effects will vary with both the ux density B and the applied frequency of the currents in the wires wound around the core as follows 26 1000 100 CORE LOSSmWcm3 10 10 100 500 1000 3000 FLUX DENSITY GAUSS 39 Recommended operating range for loss limited designs Flux density for bipolar excitation is B Flux density for unipolar excitation is Curves showing volumetric core loss vs frequency and Bmax 3C8 material shown Courtesy of Philips Components The small region in the power lossB curve with a star represents the suggested operation region to achieve the condition that the core losses are well below the 15 of the transmitted power through the core What is left for later lectures is what the lost energy does to the temperature of the core Later we will balance energy loss input to the core with energy lost to the environment by various cooling paths and end up with the equilibrium temperature of the core under operation conditions This temperature should never exceed 100 degrees Centigrade to preserve both the core and the wire insulation FOR HWS 4 and 5 do the following HW4 Erickson Chapter 12 problems 6 and 8 and in class questions as well as lecture questions 27 Hw 5 Erickson Chapter 13 problem 3 and in class questions as well as lecture questions I o V9 Iquot Cor Full Bridge CONVERTER crawl CONFIGURATION mum ilrrt tiz quot0 IDEAL 39 Mo N219n z TRANSFER VIN u 2N1Ts 2N1D FUNCTION 39 39 N AI PEAK 39 IDMAX JIRL 43 IMAG DRAIN CURRENT N1 2 time peak magnetizing current PEAK Vos VIN g DRAIN VOLTAGE 39 i I 1 AVERAGE CR5 RL moo cunnsms Icee f Int mans VOLTAGES tvnM VOLTAGE AND CURRENT WAVEFORMS ADVANTAGES DISADVANTAGES TYPICAL APPLICATIONS APPLICABLE HARRIS PRODUCTS at VCR52VIN 1VcntquotV1tl VRM VCR62VIN 1ZVCR2VIN 22 re L HLquot W W ii 7 Ii 1 m In 1 Iu I Good transformer utilization transistors rated at VIN isolation multiple outputs lD is reduced as a ratio oiN2N1 Zero voltage switching possibleLow output ripple High parts count Ci has high ripple current Re quires high side switch drive Cross conduction 0t 01 and 02 or 03 and 04 possible High input cur rent rippie 39 39 High power high input voltage 39 HiP408081 HIPBSOU tiVii0 I 39 Good transformer utilization Transistors rated at 39 ICR3 quot gL V lsolation multiple outputs to reduced as a ratio OrtizN1 High power output Zero voltage switch ing possible near D 1 Low output ripple 1 131 CR4 2 DISADVANTAGES Poor transient response high parts count Cl and 02 have high ripple current Requires high side switch drive Cross conduction 0in and 02 pos sible High input current ripple 39 A 39 m pron ml or HaliBridce VOLTAGES VRM CONVERT A I 39 VCRFVIN 39erttcurr 39 i 15 M 39 VRM conrrouu ou 0 vow le V m genlwmcm 08 1 r U quotquotquot m VOLTAGE 0 J to r i ca 8 vo AND cunnam m k I n i v WAVEl ORMS I H 19 39 HiiL39 A 39 v3 DRAIN curmm IDMAX N1 IR 2 1 17 rJ 391 r time peak magnetizing qurrent v 39 MAR Vos Vrn 39 wquot 39 39 Mu ADVANTAGES j AVERAGE DIODE CIIRRIN39I39S TYPICAL APPucAlnous High input voltage moderatetohrgh power APMICABLE HtP2500 HiP5500 uvroo HARRIS bananaquot TYPE 39 DE CONVERTER 39IRCUI39T DNI IGURATI39ON IDEAL TRANSFER FUNCTION amp CURRENT t PEAK DRAIN VOLTAGE quot39 GE CURRENTS TwoSwitch Forward M L1 Ijt 9 39 01 CHI M 1m quotVa 0 in gm 4 A mom 2531 Um do 5 H r 212512629 32 o VIN N1 T3 N1 IDMAX IRL U1MAG 1mg peak magnetizing current 01 or oz v05 Vm Vor IonrAVE ICR2AVE 4134589 D Ion3Avrs InLD Icn4AVE InLl1 43 moms vonnoas vnMi VOLTAGE AND CURRENT WAVEEDRMS ADVANTAGES DISADVANTAGES TYPICAL APPLICATIONS APPLICABLE HARRIS PRODUCTS VCR1PK VCR2PK VIN Vcna Vcn4 NN391ZVIN 3i Av Vi or r quotquot7 D l l M T Mia Not A 7 Drain currents reduced by turns ratio Lossless snubber recovers energy Drain voltage 12 that of conventional iorward converter Low output ripple Poor translormer utilization high parts count high side switch drive required Transtormer reset lim its duty ratio High input current ripple High input voltage moderate power Supports mul tiple outputs HIPZSOD HV400 PushPull 39 TYPE OF convent dIRCIIIT L courroummou IDEAL Mo Macao N2 TRANSFER I VIN 2 T5 2N1D ruucnou quot IuMAx IRL 5 iMAG 1mg peak magnetizing current REAK DRAIN CURRENT um Vos 2 VIN bum VOLTAGE 13L AVERAGE 39 39 Icn1 DIODE CURREN39IS 12 Icnz DIODE quot vomcss VRM VOLTAGE AND CURRENT WAVEFORMS ADVANTAGES 39 DISADVANTAGES 39 quotmm APPLICATIONS 39 APPlICABlE 39 HARms PRQMUQTS 39 W AI Good translormer utitlzatlon Drain current reduced as a lunctlon ol N2N1 Good at low values of VIN Low output ripple Cross conductionoi 01 and 02 possible high parts count Transformer design critical High voltage re quired ior 01 and 02 High input current ripple Low input voltage HlP5062 HIPSOGI PEAK DRAIN CURRENT PEAK DRAIN VOLTAGE ERAOE quot SYODE CURRENTS 1cm IRL Ftyback TYPE OF 39 car I Mr 39I anoint 1m CONFIGURATION m quotgm l M Vm 110 VI 74 quotWe 39 H J N D IDEAL Mo 2 TRANSFER VIN N1 TSquotton N1 1D TUNCTION IDMAXIRL 1jDAIL VnsV1mv0UTvgj moo vomoss VRM VOLTAGE ANO CURRENT WAVEFORMS ADVANTAGES j DISADVANTAGES TYPICAL APPLICATIONS APPLICABLE HARRIS PRODUCTS VRM VIN W t it I I quot7 f li l quotH5qu v39 n L Vowo Drain current reduced by turns ratio oi transior Low parts count Isolation Has no secondary put inductors Poor translormer utilization Transiormer st energy High output ripple CH1 needs last rel recovery Low output power Supports multiple outputs HIP5061 iCL7667 WOO quotP or A couvlnnn CIRCUIT CONFIGURATION IDEAL TRANSFER FUNCTION PEAK DRAIN CURRENT iMAG peak magnetizing current PEAK Vos VIN 1 DRAIN VOLTAGE I AVERAGE ICR11MABD DIODE CURRENTS 2 Icnz IRL D Iona IRL 1390 mons 39 r vomnorss VRM VOLTAGE AND CURRENT WAVEFORMS ADVANTAGES i DISADVANTAGES TYPICAL APPLICATIONS APPLICABLE Vi 1mquot M i K i quoti 39 lu iunriiv Drain current reduced by ratio of NzNr tow out put ripple Poor transiormer utilization Poor transient re sponse Translormer design is critical Transiormer reset limilsouly ratio High voltage required for 01 High input current ripple Lowtomoderale output power Supports multiple outputs 39 HIP5061 ICL7687 HV400 wquot b 39 quot 39 39 CUKiSilepUpDown comm m amour quot HW MHW quot CONFIGURATION 11 B 02 Hit lilo IDEAL o tor TRANSFER FUNCTION 1 T3 t0quot 1 D AK Sim comm TWA I I V05 2 VIN RAIN VOLTAGE AVERAGE quot Icm I1 Ig DIODE CURRENT 1 moo 39 VOLTAGES VRM I VOLTAGE AND CURRENT WAVEI ORMS ADVANTAGES j DISADVANTAGES TYPICAL APPLICATIONs APPLICABLE HARRIS PRODUCTS VRM 5 V0 VIN h 1 um 4 m I 39 Icarj 4 Simple low ripple input and output current capaci tive isolation protects against switch failure High drain current 31 has high ripple current re v quirement low ESR rngh voltage required for 01 Voltage inversion Low noise inverse ourtpul voltages HiP5060 HiPSOGi liiiP5062 HlP5063 TYPE OE CONVERTER CIRCUIT courrourumou IDEAL 1 runs summon pun 39 39 DRAIN CURRENT PEAK I quot DRAIN VOLTAGE AVERAGE atone cunttsms SEPIC Step DownUp is 39 113 quotL1 CI w T 29 or I 1 lies I 0 ma at V0 Jim 2 I l v rr fl 39 IDMAX 11IRL A1 A112 2 VDS V0 VIN VD Icnr Im moo VOLTAGES VRM VOLTAGE AND CURRENT WAVEFORMS ADVANTAGES 39 DISADVANTAGES TYPICAL APPLICATIONS APPLICABLE HARRIS PRODUCTS VRM Vo VIN Kr lr F in ow 397 F Low ripple input current stepup or stepdown with no inversion no transiormer Capacitive isolation protects against switch iaiiure unlike Buck No isolation between input and output Switch has 39 high peak and rms currents which limit output power Cl and 02 have high ripple current require ments low ESR continuous current mode makes loop stabilization ditiicuit potential instabilities with circuitmode control High output ripple Powertactor correction High reliability Wide in put voltage range HiP5060 HiP5061 HiP5062 HIP5063 DIODE quot nggg39m 39 BuckBOOSHStepDownUpl v VOLTAGES VRM VRMVOVIN truly a cal r I mch r CONFIGIIRMION quot1 vquot lul gnu c L V0 I VOLTAGE I AND cunnsm 0 H WAVEFORMS m rl K it o v 39 r l IDEAIg yQ t 1 Hr mean quot o ton I 139D 39 itsrui 7 quotAK I 1 1 AI I r DRAIN cunnam DMAX RLquottW 7 3quot VOLTAGE V03 z VI W V V39 ADVANTAGES Vquot 57 t i f AVERAGE 19m 1RL 39 shirif tiiiieileiicy 838380 a quot9 quot quot DIODE CURREN I39S H DISADVANTAGES No isolation between input and output Only one output is possible Regulator loop hard to stabilize Highside switch drive required High output ripple High input ripple current quotHem Appl39CA39 o s inverse output voltages APPLICABLE HARRIS pnonucrs m or convnmt otherquot connourumou ton runs FUNCTION I39lEAK39 DRAIN CURRENT PEAK DRAIN VOLTAGE AVERAGE DIODE CURRENT 1 V me quot139 Ci HI V0 Boost Step Up a 11 cm t M 1r JW v M V39 I I at to l l ll M0TS 1 VIN TS ton IoMAx IRLJ 9211 V03 V0 VD 1cm let moo VOLTAGES VRM VOLTAGE AND CURRENT WAVEFORMS ADVANTAGES nrshovmuaes TYPICAL APPLICATIONS 39 APPLICABLE HARRIS pnooucrs I VRM v0 quot39 iii 7 quotquot7 F i alu quot397 F High eltlctency simple no transformer Low input ripple current i No isolation between input and output High peak collector current Only one output is possible Regu lator loop hard to stabilize High output ripple Un able to control shortcircuit current Powerlactor correction Battery upconverters HiP5061 lCL7667 ill400 TYPE OF couwnun Buck Step Down M i 119 CONFIGURATION JD r h U A my it quot 11m iibm g at b v 4 IDEAL runs 04 ion 3 D FUNCTION Ill Ts quotAquot 39 I 1 AI DRAIN conum DMAt HL 2LJ PEAK i DRAIN VOLTAGE VDl VIN VD AVERAGE prone CURRENTS 1081 BL 1 0 moms voeerss warm VOLTAGE AND CURRENT WAVEFORMS ADVANTAGES 39 DISADVANTAGES TYPICAL APPLICATIONS Aliment HARRIS pnonucts VsM VIN to quot Ion quotl i i 39 l 7 it Alu Vt High efficiency slnple no transformer low switch stress Small outpu llller low ripple No isolation belwen input and output Potential oversvollage ll 01 Starts Only one output possible Highside switch dive required High input ripple current Small size imbeddrd systems HlP5600 wPlGBT ror oli line eras 3 GUIRWNl t LECTURE 35 TRANSFORMER DESIGN Transformer Design Preamble l 2 Overview of Design Complexity General Comments on Balancing Core and Winding Losses Transformer Design Constraints a Core Loss b Flux Density and Absolute Number of Wire Turns c Copper Wire Winding Loss d Total Transformer Loss Core plus Copper e Quanti ng BMax or Bopt f How to nd Bopt g De nition of Kgfe for the Transformer Core Erickson Six Step Procedure Kgfe Choice Bsat Constraint Absolute value for N primary Choose secondary turns Fractional Window Winding Area Allocation Copper Wire Area ChoiceAWG 7 Check if all is consistent C Two Illustrative Design Examples 1 Cuk Converter 2 Full Bridge Buck LECTURE 35 TRANSFORMER DESIGN A Transformer Design Preamble 1 Overview of Design Complexity We usually place a transformer in a PWM converter circuit where both the electrical drive waveforms and various loads are well known In the multipleoutput power supply the total current drawn in the transformer secondaries is Itotal output current sum of all secondary wire winding currents Ptotal of the supply is the sum of all load powers om each secondary winding For lossless operation we have a rough handle of the required primary current But we will require more primary current when we include both core and copper losses of the transformer We saw last time that the total power loss of a transformer can be minimized by operating at an optimum value of BOPTcore In this lecture we will feed this optimum B is into the total loss equations to obtain an expression for the total loss This relation for minimum loss then yields the transformer K parameter Kgfe We will employ this single parameter Kgfe as a guide to select the proper transformer core just as we employed Kg to nd the optimum inductor core Transformer losses can be put into three major categories core hysteresis losses core eddy current losses and wire winding losses Core hysteresis losses are a function of the maximum ux swing and equency of the current in the coils whereas both wire winding loss and core eddy current losses depend on RMS current and ux swings respectively Clearly current waveforms have a big effect on expected transformer losses This lecture emphasizes the losses of power transformers used in buckderived topologies forward converters bridge halfbridge and fullwave centertapped converters We will illustrate our arguments by looking rst at buckderived circuits under the constraint of constant output voltage and seeing the trends for core and copper losses In all buckderived circuits that include transformers with a turns ratio n under steadystate conditions VmD nVO Under fixed output operation as would occur with feedback input voltseconds and therefore the corresponding ux swing of the transformer are constant We will see below that hysteresis and eddy current losses behave differently Hysteresis loss is therefore constant regardless of changes in Vin or load current Core eddy current loss in buckderived operation with xed output on the other hand is 12R loss in the core material where I is induced by the changing ux versus time If Vin doubles Peak 12R loss in the core seems to quadruple but since D is halved to maintain constant output average 12R loss only doubles Thus core eddy current loss under these conditions is proportional to Vin Worst case for eddy current losses occurs at high Vin In most ferrite materials used in SMPS applications hysteresis losses dominate for equencies up to 200300 kHz At higher equencies eddy current losses take over because they tend to vary with equency squared for the same ux swing and current waveshape Once core eddy current losses become signi cant they rise rapidly with equency especially at high Vin Note that the increase in eddy current loss with high Vin and small D is not shown in core manufacturer s loss curves because they assume sinusoidal waveforms for the loss nomographs Transformer copper winding losses in buckderived circuits are considered next Primary transformer current 11 equals load or secondary current 15 divided by the transformer turns ratio n whether peak or RMS 1st IL and by transformer action lppk ILn Note that peak currents in the primary coil are independent of Vin At constant peak current constant load rms current squared and the copper wire 12R loss is then proportional to duty cycle D and inversely proportional to Vin We assume that with constant peak current assumed high order harmonics depend mostly on switching transitions and do not vary significantly with duty cycle D variations This meansin buckderived converters wire winding loss is always greatest at low VIN Thus at equencies up to 200300 kHz worst case is low Vin and a full load on the secondary because of high winding losses Winding losses also rise with equency especially at low Vin To maintain a reasonable RAcRDC Litz wire with more strands of ner wire must be used This choice may raise RDC because increased wire insulation and voids between many stranded wires reduce the effective copper area Thus at equencies where core eddy current losses dominate total core loss peaks at high Vin conditions and at full load Wire winding loss worst case always occurs at low Vin and full load Note the con icting loss variation with Vin depending on exact conditions The above assumed ferrite cores were employed The situation changes for laminated metal alloy and powdered metal cores where core eddy current losses always dominate hence worst case is at high Vin full load Winding losses are worst case at low Vin full load The trade017s between winding and eddy current losses involve design compromises in the transformer materials as well as transformer design of the wire windings This compromise is the subject of this lecture 2 General Comments on Balancing Core and Winding Areas as well as Wire Losses Normally at SMPS operating equencies when the core is usually loss limited not saturation limited total transformer losses are at a broad minimum when core losses are approximately equal to or a little less than winding losses Previously we stated that winding losses are well distributed between coils by making the rms current density approximately equal in all windings However the RMS currents will vary with the current waveforms in the individual wires Sometimes the primary and secondary current waveforms in transformers are different and as a consequence primary and secondary currents have different RMS levels See pages 1314 of this lecture for an example You may also recall that the winding area allotted to each winding depends on its RMS value With a fullbridge or halfbridge primary with centertapped secondary windings rms current densities will be approximately equalized when the primary conductor crosssection area is 40 and the secondaries 60 of the available area as we will see below in most other cases primary and secondary conductor areas should be 5050 These 5050n cases include forward converters singleended primarysecondary SESE Centertapped primaryCentertapped secondary transformers bridgehalf bridge primarybridge secondary The above wire winding allocations can be impossible to achieve because the number of turns in each winding must be an integral number of turns in extreme cases we find in a low voltage secondary 15 turns maybe required for optimum balance between core and winding losses With one turn the ux swing and core loss maybe much too large with two turns the winding loss becomes too great This kind of transformer design headache will also be addressed herein 3 Transformer Design Constraints There will be five constraints on transformer design that will result in the formation of a transformer core K factor Kgfe We will use the single factor Kg to guide the design process But we must realize that this is a guide in the first step of an iterative process that may require us to change our design as we go For example changing the number of wire turns from our first guess will also effect the core choice as would a different core choice effect the maximum number of allowed wire turns a Core Loss This is usually found by employing a graph of total core loss provided by the core manufacturer To use it we need to know the maximumB field imposed on the core material Core loss l5 Pfe KfeBmaxAclm Typical value of 3 for ferrite materials 26 or 27 Bmax is the peak value of the ac component of Bt So Increasmg Bmax causes core loss to Increase rapidly This is the first constraint b Flux Density and Absolute Number of Turns Flux density 30 is related to the VI applied winding voltage according area 7 to Faraday s Law Denote the volt seconds applied to the primary winding during the positive portion of vt as 7t r1 2 t39 2 in vtdt L 1 This causes the flux to change from its negative peak to its positive peak To attain a given flux density From Faraday s law the peak value the primary turns should be of the ac component of flux density is chosen according to max 2n1AC 1 ZBWAC c Copper Wire Winding Loss The key point here was made previously Due to the allocation of wire window area among the various windings we found the suprising result that the resistance of the k th winding varied as the square of the number of turns in the k th winding rather than NK This will be linked to the fact that nlB to give the trend that wire winding loss varies as lB2 This will combine with core loss going as B to some power set by core materials choice Hence an optimum Bcore exists that results in minimum overall copper and core losses Allocate window area between windings in optimum manner as described in previous section 0 Total copper loss is then equal to pMLTn I2 k n P tot 5 WAKu tot J nl j with Eliminate 11 using result of previous slide 2 Mil MLT 1 WAAE Bf P K Note that copper loss decreases rapidly as B is increased ll M quotNIX d Total Transformer Loss Core plus Copper We saw previously that Pcopper goes as N2 which is the same as lBz We also know Pcore goes as B so the total loss versus B has a broad minimum as shown below There is a value of B I max I that minimizes the total 01 power loss 0 a 0 PM 8 lt1 a a ProtPfgPCll Ugo Q b Pfe Clm 5 Optimum B max quotMIX p M150 MLT 1 P cu 2 2 K WAAC B max e Quantifying BMAX or BOPT To optimize any function we take the derivative and set it equal to zero taking care to insure the sign of the second derivative is positive for a maXimum This will give us an expression for BOPT in terms of all the transformer design parameters both for the windings and the core We then place this value of BOPT into the total power expression to nd the transformer K factor Kgfe Given that PmtPf6Pcu Then at the Bmm that minimizes PM we can write dPtol dee chu 0 dB dB dB max max max Note optimum does not necessarily occur where P3 Pm Rather it occurs where dPe dP CM dBmax dBmax f We outline below how you nd BMAX or BOPT This will be a simple mathematical exercise as shown below Pf KfeBmeAclm P p 1 20 1 39 I cu K Brznax d P fe 3 1 dBmaX BKfeBmax AClm dPCu 2 pkilfot B 3 d Bmax 4K WAAE dP Now substitute into dB 3 C and solve for Bmx max Biz Optimum Bum for a given core and application Milt MM 1 2Kquot WAAilm BKfe This expression is just the midpoint of the calculation We next plug BMax into the total power loss in the transformer including both copper and core losses as shown on page 8 and solve explicitly for the minimum total power loss including both core and copper losses B max Substitute optimum B into expressions for PCquot and Pfe The total loss is 5 max B 2 4 gt312 MLT BHFE B m 32 p 1 tot Prof lmeeF 4Ku 2 2 Rearrange as follows lift WA Acliz B 1 p p 637 pkflmeE 3 3 Mm It 2 4K Pl Left side terms depend on core Right side terms depend on geometry specifications of the application g Definition of Kgfe for the Transformer We are now equipped with our single transformer K factor 215 145 2 vr WT 9W la Define K 2 gfe Design procedure select a core that satisfies pkflfoK m 4K P0llBZlBl 9 Appendix 2 lists the values of Kgfe for common ferrite cores ltng is similar to the Kg geometrical constant used in Chapter 13 o Kg is used when BMW is specified KM is used when Bmax is to be chosen to minimize total loss Kgfe to go forth and follow a stepby step transformer design procedure as given below B Erickson Six Step Procedure to Transformer Design Step 1 Material Choice for the Corengfe We determine the required core size from the Kgfe constant of the chosen core material We need the wire current required by the circuit the required total power level and ux linkage values or primary voltsec speci cation from the input voltage to the transformer waveform To make sure the units are consistent in the Kgfe parameter we list below the major transformer quantities The following quantities are specified using the units noted Wire effective resistivity p Q cm Total rms winding current ref to pri Ito A Desired turns ratios nznl n3nl etc Applied pri volt sec K1 V sec Allowed total power dissipation Pm W Winding fill factor Kquot Core loss exponent B Core loss coefficient Kfe Wcm3Tl3 Other quantities and their dimensions Core crosssectional area AC cm2 Core window area WA cmz Mean length per turn MLT cm Magnetic path length lg cm Wire areas Awl cmz Peak ac flux density Bmax T Now we are on the same page for calculating Kgfe p A 1 Ki 4 Ku Ptot mzym The core data base spec s Kgfe for various generic sizes is in Appendix 2 of Erickson We use Kgfe to pick the appropriate core size and core material such that we meet this inequality We assume peff pcu Pdc If by different core materials choice Kfe i this allows us to employ a smaller core for the job and vice versa 108 Kgfe 2 Step 2 BSat Constraint due to core properties Evaluate peak ux density and compare to Bsat of the chosen core material that we decided to employ 1 7 8 p 1 Ifot NILT 1 2 2Ku WAAg e Kfe BmaX Bmax must be below Bsat For pure AC excitation Vpeak NpAcw Bsat 0r VpNAcw lt Bsat Note both Kgfe and Bmax both vary as the voltsec quantity kzl Be careful to note any DC core ux bias effects due to ampturn effects If at this point we exceed BSAT we need to either of two paths in an iterative approach 1 Choose a core with a BIGGER Kfe loss factor and repeat the first two steps 2 For HW1 YOU SUGGEST ANOTHER SOLUTION Step 3 Absolute Number of Turns Evaluate the absolute number of required primary turns om the previously calculated Bmax Note k1 lvdt when the fSW T then M i for a xed V fSWT what happens to core loss n1 A 104 239 Bmax AC Having speci ed the turns on the primary the secondary turns follow the voltage ratios of the various secondary voltages Step 4 Secondary Turns Choose the numbers of turns for other windings according to the desired turns ratios n2 n2 n1 n1 n3 1 13 1 11 i n1 Restrictions on Number of Turns Choices regarding the number of turns and turns ratios are often severely limited by low voltage secondaries because integral number of turns must be used For example in a 5 Volt output the alternatives might be a lturn or a 2turn secondary This change represents a 2 to 1 step in the number of turns in the primary For the same size core and this change doubles the current density in the windings and accordingly increases the loss Choices may be irther restricted when there are multiple low voltage secondaries For example a 25 to 1 turns ratio may be desirable between a 12 Volt and a 5 Volt output This is easily accomplished with a 2turn 5V secondary and a 5turn 12V winding But if the 5V secondary has only 1 turn the only choice for the 12V secondary is 3 turns which may result in excessive linear postregulator loss This problem could be handled by the use of actional turns but this has it s own hazards There are no hard and fast rules to follow in establishing the optimum turns for each winding but there is some general guidance First de ne the ideal turns ratios between windings that will achieve the desired output voltages with the normal VmD established earlier Later when a speci c core has been tentatively selected the turns ratios will translate into speci c turns but these are not likely to be the integral numbers required in practice It then becomes a juggling act testing several approaches before reaching the best compromise with integral turns The lowest voltage secondary usually dominates this process because with small numbers the jumps between integral turns are a larger percentage Especially if the lowest voltage output has the greatest load power which is often the case the lowest voltage secondary is rounded up or down to the integral Rounding down will increase core loss up will increase winding loss If the increase loss is unacceptable a different core must be used that will require less adjustment to reach an integral number of turns The low voltage output is usually regulated by the main control loop Higher voltage secondaries can be rounded up to the next integral with less dif culty because they have more turns However it is unlikely that accuracy or load regulation will be acceptable requiring linear or switched postregulation Since in practice the primary is usually higher voltage the primary turns can usually be set to achieve the desired turns ratio without dif culty Once the turns have been reestablished the initial calculations must be rede ned Don t forget this is iterative design proceedure Step 5 Allocation of Wire Winding Window Evaluate the fraction of window area allocated to each winding based upon the ratio of the mmFs or ampturns of each winding compared to the primary ampturns H111 061 7 Illltot nzIz 127 mlm nka ak Illltot A more quantitative example here would be useful and is given below Consider the Full Bridge PWM Converter Transformer Case of page 13 The three transformer windings each have unique current versus time waveforms due to the centertapped secondary and the circuit switches so that RMS values of the primary current i1 and secondary currents i2 and i3 are quite different This will effect the allocation of the wire areas in the wire winding windowWA in ways you might not anticipate This is most evident from the current versus time waveforms 13910 20 I in mm It mm t n mm if 0 1 quotx 1 I 0 0 l l 1391 1 l quotx 13930 I 05 l 05 I 0 I gm 39 I 05 l 05 I 0 0 D7 T TDT 27quot 3 Consider the primary Winding rst and its proper relative area of windings in the core Window N111 1 N1I1N212N313 1 N111 N111 1 N2 71m 1 11 N212 2N 5 J same for N313 N111 N1 7215 N111 N1 7 1 a 1 1D 1 D Primary Wiring area is a function of the expected DC operating choice for duty cycle f1D 1 1 0 2 0 3 5 D 1 1 D SecondaIy areas are equal and also depend on the chosen equilibrium duty cycle f2D Step 6 Wire AWG Assignments Evaluate and choose proper copper wire sizes to equalize sz losses in each winding 06 2 Ku WA Ill 06 2 Ku W A n2 Choose wire gauges to satisfy these criteria Awl E Aw2 E Step 7 CHECK OF RESULTS Need for Iteration Now we can check the transformer parameters calculated above The multiwinding transformer has one Lm as seen in the primary circuit and many winding resistance s Let s take the three winding transformer shown on the top of page 12 and calculate LM IMpeak and the resistance s in the various wire windings We will not attempt to calculate the leakage inductance s of the various windings For extra credit on HW1 try to outline the methodology to do so m A L 2 Ni 72 m McN AC R 16 2 s L if 1mltpeakgt 2 1 l2L ikr Lm m nk Rk Winding resistances p n1MLT R1 Awl MLT R2 pn2 Aw2 D TWO ILLUSTRATIVE DESIGN FLOW EXAMPLES 1 Illustrative Single output CuK Converter With Isolation Transformer Design We are given fSW 200 kHz Dop 05 Ku 05P100W a turns ratio n 5 and we allow only a total loss in the transformer of 025 W We seek a 5 V output from a 25 V input switched at 200 kHz The total circuit power is 100 W Ptotal causing Iin 4A and 10m 20 A I 8 v t v t I 4A 0 7 20A gt v m quot39 gt Xv i105 n 1 T20 This sets the quiescent duty cycle to D 05 for the given transformer turns ratio is E 5 I12 For the chosen core material spec s we have W Kfe 247 3 3 26 gt Ferrlte TB cm For the chosen wire to be used for windings we have The total ux linkage in the transformer core is given in Vus From the Appendix of rms values the 11rms from the 11 waveform given below is 11rms Di2 D Ig24A Wheren 5 1 1 1 12 A 1 I 1 n We also know that 12 rms n11rms 20A n11rms 20 A I nIg Now we sum the voltsec current and the load current in the primary to nd Itotal 11 12 n 8A rms Now we know Itotal Ptotal k1 Kfe 3 Kcu so that Kgfe may be estimated 1724 106625 1062 8 2 247226 Kgfe 3 4626 405025 Go to appendix 2 in Erickson on cores and match Kgfe to a standard core We choose 2213 to match Kgfe 0047 as close as possible The next smallest core is not su icient This exceeds the calculated Kgfe required 0003 and will provide lower core loss via lower Bmax Having chosen core 2213 we know om the core specs Accore WA and the mean length of wire turn MLT to encircle the core Thus we know Bmax B 2 1724 106625 1062 8 2 442 1 max 205 029706353315 26247 00858 Tesla 108 0003 14 Bmax is indeed lt Bsat for the chosen core material which is given 035 Testla In general BSAT for ferrites that operate around 100kHz is typically 01 Testla Knowing Bmax M and Ac we can calculate the number of turns N1 required to keep ltmax lt Bsat 21104 n1 57 turns we arbitrarily choose N1 5 and N2 2 BmaxAc 1 m E 10 This roundoff direction choice leads to slightly higher B and higher core loss which we judge is acceptable Fractional wiring windows Next we determine the action of the core wiring window that 2 7 8A each winding will occupyog1 05 of the available wire winding area l lt lt20A 062 05 of the available wire winding area 8A This allows us to then calculate the required copper wire sizes 05 05 0297 AW 1 W 2148 10393 cm2 For the primary or 5 turns of 16AWG copper wire AW 2 742 o 10393 cm2 For the secondary or again one turn of 9AWG copper wire which is not practical Some practical solutions are to use Litz wire or to use foil wires Note the trends for the core size for the Cuk converter given the core parameters as xed by our choice of core material as we change the switch frequency From 11 l vdt fsw T 11 l 3 Both Bmaxl and iml This changes required abcd core diameter as shown below for core size vs fsw 4226 BmaXJ faster due to core loss Po care she v x 39 Liz 7a mquot 25m sour room zoom zsouu 39 400m 500m moonu Switching frequency Fig 1412 Variation of transformer size bar chart with switching frequency Cuk converter example Optimum peak ux density data points is also plotted Below 025 MHZ Above 025 MHZ When fl then the When fl then core size l core size T Conclude fl allows smaller core UNTIL inherent core loss of the material system kicks in at higher f We thus can only reduce transformer size in this speci c case only over a limited f range by increasing fSW With different circuit waveforms and different transformer materials these core size trends would be altered or shifted 2 Illustrative Full Bridge Buck Transformer Design B0p 075 See Section 631 Pg 141 of Erickson s text for details of switch timing For a given switch equencyfs 150 kHz then T5 6 23 us 666 us However the transformer equency is not the switch equency Below we review design high lights 9 it n Interval Interval Interval Interval 1 2 diodes 3 4 diodes Q1Q4 D5D7 A11 D5D6 Q2Q3 D6D8 A11 D5D6 on on Q off D7Dg on on Q off D7Dg off off Bridge occurs operation in transformer secondary and due to center taping we nd ftrf f Consider the core choice as made with a core of known properties as summarized on the top of page 20 20 Ferrite At 75 kHz we find for the core material E 26 T3 cm3 We have chosen to utilize an EE type geometery core for this transformer Consider also that the wire choice was made so that Kufill factor 025 Litz wire Ptotal transformer loss is xed at 4W for both core and all Wire Winding by the temperature constraints and thermal equations Kgfe z 1 12 total Both of which are presently known Kfe We need to find M of the primary winding and Itotal in order to select a core from manufacturers tables with a GREATER Kgfe than our calculation gives The uxlinkage 7 N4 VAt VDTS is obtained from V1t waveforms shown belowas k1 O75666us 160V 800 Vusec v1 area A V ng o o F Q QM 034 429 o N Given the i1t waveform versus time we can calculate 11rms 11 1 12 1 11 Nll ldll lgl l3l 11 windingD This becomes Ilrms Ile2 from appendix Ilrms 57 We plot on page 20 the secondary current waveforms versus time and calculate the RMS values of the currents 12 21 it A quot21 L131 1 v V n 5 n 5 o i 12 quot3 I I l quot1 5v quot1 15v Given the i2t waveform we can calculate 12rms 12rms 1 5v2 mo 2 661 A i211 A 1 5V 051 1 0 Given the i3t waveform we can calculate I3 rms 13rms1 15V2 1D12 99 A f t A 3a 115V 05 1m L 0 L 4 0 157 2 T3DT3 22 Knowing all currents in all windings we can nd Itota1 ms 114r g 12 2 E 13 144A 1 11 1 11 5 5 Where n2n1 and n3n1 110 110 1 O 106 2 76226 8 Kgfe 2 40 2544626 10 OO94 From the appendix 2 of Erickson we select for the windings the EE40 core that just meets the Ptoml and 1mm spec s KgfeEE40 001 gt 009 gamble it will be too close a guess But lets see what happens 22 For this core geometry we nd the geometric factors 4 77 A0 127 WA 11 and MLT 85 B 108 1724103968001039621442 85 1 max 2025 11127377 2676 023 Tesla Bmax 023 is well below Bsat 035 for the core material We can specify n1 to insure no saturation occurs 1z gt8 4 m A 137 2BmaX AC Where we usedAc 127 and gtt18001lt106 5 7 137 062 2 110 15 7 137 187 3 110 Now round off to total of fractions in an artful way n1 22 n2 1 n3 3 Given the new n1 om the roundoff recalculate Bmax 11 014 Tesla 2 n1 Ac PlOSS Pcore BBmaX Pcu wire B max BmaX We take these terms one at a time Core volume Ac e Note also Kfc 76 Bm 0143 A0 124 and Z 77 so that Pcore Kfe BmaXAc e At 20 C pCu 171039611 80010396 ltotal 144 MLT 85 WA 11 and A 124 23 pl 1 MLT 108 Pcu 2 2 4 ku WA Ac Bmax For the fullbridge use of the core we nd that the total core loss is Pt0tal 047 54 6W Unfortunately the core is only speci ed for Ptotal 4W gt Lost our gamble of pg 20 We actually gt Need larger core to dissipate the high energy 54W Our next iterative choice EE50 has Kgfc 028 Bmax 014 with n 12 Keeping n1 22 n2 1 n3 3 Bmaxn1 22 08T Ptotal Pc0m08T Pcu Wim08T 023 39 now the core choice appears consistent ok Next we allocate areas for the individual windings One Primary Winding Area 061 h 0396 ofavailable 1T Two Secondary Winding Areas N2 a 711 021 2 N1 2 T N2 a 711 009 3 N1 2 T Next wire we specify the AWG s of the three windings A 1 2 a1 KuWA 2 0396025178 Z 8 W n1 22 gtAWG 19 for the primary 039103 cm2 24 a2 Ku WA 2 0209025l78 n2 1 AWG 8 for the 5 V secondary winding 13 KuWA Z 0094025l78 2 139 106 cm2 n3 3 AWG 16 for the 15 V secondary winding Of course we could also use Litz wire or foil for the secondary windings AWZ 930010393 cm2 Aw3 Summary of Inductor and Transformer Saturation Design Rules Rule Interpretation Ni lt BSNQRA Amptum limit for an inductor Wmall gBmZCCMAwmp Maximum energy that can be stored in a given core Wm 82uVyPpo Maximum energy is determined by air gap volume if the core has high pquot VoN lt waA Maximum volts per turn for a transformer at frequency a Iv d lt NBwA Maximum voltseconds for an inductor or transformer Start to read Chapter 5 of Erickson this week as we will nish power magnetics and transformers next lecture Lecture 37 will start discontinuous conduction mode 25 Lecture 43 State Variable Approach to AC Converter Models A State Space Averaging 1 General Concepts states v or u independent inputs Energy variables 3 Independent inputs v or u State equations Ki Asz BV Y Ci Ev Illustrative Circuit Example Methodology in state space for ltgtTS averaging a 51 for first interval de 522 for second interval d Ts b Time weighting over T8 of matrices 0 Small Signal Excursions 1 3 Independent state equations 2 Dependent variable equations d Transform time domain gt S domain m gt gt2s fgt lt 819 96 9 9s fez a 9 Examples a DC Lossy BuckBoost b Erickson Problem 78 ocww Lecture 43 State Variable Approach to AC Converter Models A State Space Averaging o A formal method for deriving the smallsignal ac equations of a switching converter Equivalent to the modeling method of the previous sections Uses the statespace matrix description of linear circuits Often cited in the literature A general approach if the state equations of the converter can be written for each subintervai then the smallsignal averaged model can atways be derived Computer programs exist which utilize the state space averaging method The state equations of a system are employed and placed in matrix form A canonical form for writing the differential equations of a system If the system is linear then the derivatives of the state varables are expressed as linear combinations of the system independent inputs and state variables themselves The physical state variables of a system are usually associated with the storage of energy For a typical converter circuit the physical state variables are the inductor currents and capacitor voltages Other typical physical state variables position and velocity of a motor shaft 0 At a given point in time the values of the state variables depend on the previous history of the system rather than the present values of the system inputs To solve the differential equations of a system the initial values of the state variables must be specified 1 System variables are of several types state variables x independent system inputs u or v and y will be dependent variables Energy lt gt state variables use 3 X a Follow the energy momentum variables or state variables because both are conserved 1 For electrical systems the energy resides in a lnductor currents b Capacitor voltage 0 Resistor l V 2 For mechanical systems energy and momentum involve a Velocities angular speed b Positions b System independent inputs the u or v variables 1 For electrical systems a Drive voltage current b Duty cycles of switches 2 For mechanical systems the v variables a Forces Torques Independent inputs to electromechanical systems u u u u are given by u or v c United electromechanical models are possible by using a and b together using an agreed upon standard mathematical formalism 3amp0 is a vector with a state variables energy storage 7t or ut is a vector with a independent variables driving forces Ki Ai Bu 1 input vector of external sources Matrix Matrices with of L s constants of and C s proportionality of the circuit State Space analysis is very popular in modern control theory where the rule is the more variables you can sense the better off you are In fact one tries to feedback ALL STATE VARIABLES so you can tailor the system transfer function to better achieve the dynamical response you seek Later in chapter 11 we will employ two feedback loops one for current and one for voltage as an example We repeat the two loop currentvoltage control schematic below 1 Std Vo compared to Vref as an outer control loop 2 Inner current feedback loop on iL compared to icontrol buck converter i comparator atch 1 currentprogram med controller Vref convention39a39l39outp39ut voltages 39c39o39ritr39olr r Another example of feedback with dual loops would be the boost converter below with proportional integral control In simple proportional control the error signal can never be zero as we need a smaH errorsrgnat to onve ot creatron Tne error can be made smaH wrtn nrgn garn outtnrs creates otner prooterns Forexampte srnat a vanatrons couto cause otvanatrons ans doesn t create rnstaortrtv rn tne sense of a grovvmg orsturoance out org vanatrons ofdt cause orgger swrngs on tne wav to recoverv One sotutron rs to ernotov rntegratron to tne error stgnat e so tnat tne output wrtt cnange unm tne errorrs exac v zero andfe dt rs atso zero ans effect occurs even atverv tow stead state We can tnen use ootn oroportronat controt and rntegrat controt together grvrng a controt parameter Km Km tltr vets mot 44mG Vam eeneraHv Kr rs tow to avoro rntegrator over nuntrng mtegratorvvmdrup and t9 rs targe forfast targe srgnat orstur ances Betow tne ouat tooo boost converter ernotovs tne output vottage error as a vrrtuat current reference rs usuauv tnangutar sawtootn rn snaoe and acts atso as a stabmzmg rarno as we wrtt snow n on M 3253135 in KX MN BU In the state variable approach we begin with the state equations of a linear system which summarizes known relations in a specific system or circuit topology for independent inputs u or v and state variables x All other dependent variables in the circuit are given by the vector y or matrix Y Y C X E u l l l Output Matrices with proper constants of vector proportionality Note the mathematical completeness assumption that all y s are a linear combination ofonly x s and u s There is some ambiguity at first as to what actually constitutes independent inputs and what constitutes dependent variables eg ig input to converter is usually chosen as a dependent variable while vg is chosen as independent Summarize methodology Ki Ai Bu x states associated with Energy storage u inputs you specify and are the driving forces y Ci Eu y dependent variables that the driving forces u and the x states fully specify 2 Specific Circuit Model in State Space Matrix Formalism Let s get specific and see what all this talk means M L 7 W J iR1t ic1t ic2t R ltgt gt 2 ltgt i1t R1gt 01T V1t 2T V2t gt Voutt Independent Kwithout Independent state variables mutual coupling Inputs V1 C1 0 0 3iVz k 0C20 Uiin i 0 0 L Dependent variables V0 y 1R1 Then without much thinking we can combine these four into matrix form using state space matrix formalism k3quot AxBu Below we furtherjustify the specific choice of A amp B matrices based on the well known circuit node and loop equations dV1t 39 1 0 139 dt 39 C1 0 0 R1 V1 1 d t 0 C2 0 Z145 0 1 1 V2 0 iint 0 0 L R2R3 1a 0 dit 1 1 0 dt K m A xt B dt ut In the way of a check we find the following iC C1 imt E it ToprowoanndK 1 dt R icz C2 it L Second rows ofA and K dt R2R3 dKO VL L F V1 V2 gt ThIrd rows oannd K In summary The same equations ic1t Cl it 51551 it tam C2 diff i0 R33 dit VLU L V10 V20 dt Express in matrix form 12 7 0 1 Cl 0 0 dv t 39 V10 1 0 c2 0 dz o R 1R 1 v20 0 axquot0 0 0 L 2 3 e e dzt 1 1 O 1t V V VJ K A xt B ut Likewise we can combine 3 and a to form the dependent variables 2 R3 2 LG v0 v2 R2R3 1Rt R1 That is in the form y Cx Eu 0 R3 Vout R2 R3 V10 0 0 Z V20 0 iint 1 i 0 0 10 R1 l l l l l yt C xt E ut Simply stated we are doing nothing new We are simply agreeing to write all circuit loop node and dependent relations in an easy to visualize matrix form that we all agree on Once this is done then matrix math will easily be done via standard methods of perturbation theory to obtain small signal averaged models We do this in three major steps Averaging between the switch states during TS Calculate quiescent equations Calculate small signal equations This is similar in spirit to circuit averaging but the mathematical means are different 3 State Space Methodology for ltgtTs Averaging of switch states a Separate State space matrices for D1Ts D ZTs D3Ts interval interval lfitexists in DCM Forget for now the DCM of operation and consider only 21dTS and 22d39TS and consider only a Vd input We then get two separate state equations for the two switch intervals il 2 Ali B1Vd X2 Azi B2Vd Simplify VO terms of x only V0 C1X V0 CzX during de during d Ts During subinterval 1 we have K A1xt B1 ut yt C1 W E ut So the elements of Xt change with the slope dxt d t K A1xt B1ut Small ripple assumption the elements of Xt and ut do not change significantly during the subinterval Hence the slopes are essentially constant and are equal to d2 K I A1 ltxtgtn Bl new The change during the first interval is Xt Ar K A1ltxgtTSB1ltugtTs dflgo K 1 At ltxmgtn Bl ltultrgtgtn X0 Net change in state vector over first 0 df subinterval S KidTi 9 de KquotA1ltxtgtTSBlltutgtTs nal initial interval slope value value length We can do a similar step for the second interval as shown on page 11 That is Use similar arguments State vector now changes with the essentially constant slope d2 Kquot A2 ltxlttgtgtrs 32 ltultrgtgtn The value of the state vector at the end of the second subinterval is therefore xag 12 an K A2ltxtgtTSB2ltutgtTX V nal initial interval slope value value length We can now get the net change over the switching period We have xdTS x0 dT K Al ltxtn B ltutgtn xm xde d39TS K A2 ltxtgtTJ B2 new Eliminate xde to express xTS directly in terms of x0 xm x0 12K A mm B1 ltutgtT d39TxK Az mm B2 ltutgtTI Collect terms xm x0 TSK dtAl d39tA2 ltxtgtTS TSK 39dtB1 d39tB2 ltutgtTS b Average State Variable Over Ts by Time Weighting We next calculate an average by weighting each state variable matrix by the appropriate duty cycle it A1d Azd39 2 B1d Bzd39 Vd v0 c1d Czd39 2 Consider first a converter with two state variables iL and vc Also only consider CCM operation with only two time intervals D1 and 1D We find for external sources u or v X Alx Blu for switch period D1TS A2 Bzu for switch period Dsz 1D1 D2 If we are operating where the ripple is triangular fSW very high then all time derivatives are simply constants so that from t 0 to t D1TS xAt x0 XAt At D1TS xD1Ts x0 Alx Blu D1TS This x value is then the initial condition for the second switch period 1D So that at T8 xTS xD1TS AZX 132 u D2TS X0 A1X B111 D1Ts A2X B211 393sz Combining like terms xTs x0 D1A1 1D1A2xTS D1B1 1 D1BZUTs Notice the average matrices have been formed KTS average D1A1 1D1A2 X BTS average D1B1 1D1Bz B X X and E are the duty cycle weighted averages of the state space average xTS x0 Xx EuTS That is the averaged system equations over the switch period are dxdt xTS x0 X X TS averagex ETS averageu This is the continuous approximation to the original switching system To recap 1 Circuit equations are written for each switch state 2 A weighted average of A and B matrices are made via duty cycle weighting We We the state equatwons for L and c mmduetor deLdt or DJ tranSwStor on v D W V V For Dsz dwode on V W wapaenor L e mead dedt DMdmg 9 by L and VL byC We obtam 71 0 7 DVm 1 L1 W a Va 0 C RC A1A2 K forBuck B changea Wm swtcmng Vm 0 Dme T e L 0 0 0 Next Conswderthe boost converter be oW L L H y BM We write state equations for L and C vLinductor LdiLdt For D1TS transistor on vL Vin For D2TS diode on vL D1Vin Vc iccapacitor DziL VJR Cdvcdt 0 0 0 i 0 A 0 A L Ag CRC C RC i Vin NOWB1BzB 0 c General Quiescent Operation point and Small Signal Excursions valid only at that point x gtXx V0 gt V0 0d gtDd Look familiar except for the matrix bookkeeping Then expand neglect all higher order terms keeping only DC and AC terms For simplicity small signal variations d on W are assumed zero for now and vd E Vd Using 3 equation 1 s Ax BVd gt ltA 1A1A2X Bl32ml l l l i do terms ac terms dc terms Aaverage 2 AD A2D note time average on A1 A2 Baverage 2 BD BZD and the dc values x Vd Steady State 3 0 Ax Bvd x A391 Bvd AC Perturbation 2 Ad average 2 Next we use Vo C1d Czd 3i and perturbIinearize V0 90 CX t C139C2X d i dc term ac terms coefficient is time averaged C 2 CD CZD Steady State v0 cx c A B vd AC Perturbation co Cgt2 C1 C2X 31 d Transform time equations into transfer Laplace transforms and transfer functions gt2 e Sgt2 me AtA2X Bl139w 61s s 1 A391A1 A2X B1 B2Vdds i unity matrix ms Ctsl A391AtA2xBlBavctiae ctcmq LC IRS CSIA391A1A2XB1B2VdC1 In summary the time domain forms d t A A A K 73 Axa Bum AtA2X Bl32gtUdlttgt t Cgtt E t CI39C2X E139E2Ua t gtEs 1s calculated or any other transfer function of interest can easily be changed to Laplace form and 1 Lets try the fonNard converter with equivalent series resistance s for both C and L rc and rL x1 gt iL and xz gt Vc as shown below lt T Vd8V Vo5V gt R ltgt V0 5 rL20m ohms C L5uH T F rc10m ohms C2000uF R200m ohms 39 fs200kHz gt rc ltgt X2 During DTS switch on we obtain state loop equations 39Vd LX1 I39LX1 RX1 0 39X239CI CX2 RX1CX2 0 KVL 2 The simplified secondary circuit is shown below to aid understanding HAL Xi X1CX2 n L rc lt lt gt Vd 322 Rgt Vo 39 T F Now use the standard state space form X A1 X1 B1 Vd l l l l l chRrLrcrL R M LRrc LR rc x1 l L Vd R 1 x2 0 X2 CRrc CRrc During D TS switch off series diode on A2 A1 Bz 0 X X1 CX2 L j n rc gt Vd o i022 Rgt Vo X2 T f V0 for both DTS and D TS intervals is RX1 CX2 ch X1 R X2 R l rc R l rc ch R X1 V0 R rc R rc X2 During both DTS and D TS V0 2 C13 2 C23 Time Averaged Matrices over the switch period T8 are obtained as follows A A2 A1 from AD 1DA A B DB1 C C1 Cg Using the simplification Rgtgt rc rL we know from circuit values V0 2 RX1 39 CX2 L A gt C gt r0 1 B is the same no 1 CR OiH resistors Steady State or DC Conditions 0Ax BVd gtxA391BVd v0 Cx CA391 Bvd D E CA391B WhereCrc1 B I Vd 1 1 CR and A391 Multiplying 1 l m C L out we find for the DC case amp R re Vd R l rc l rL AC Small Signal Model was Am amps A1A2XB139B2Vd as sIAi391A1A2X B139B2Vdas ms Cgt2ltsgt clc2Xamps A139A2X 85 B1B2 Vd T sl A1 A139A2X sIA391 8s c1 c2x B1 39B2 Vd vos Z amps 1SrcC i RcrcrL LC d LCs2 s Please note that the forward converter transfer function has the following properties 1 single zero WZ 7 rec 1 2 double pole W0 E 3 Since rcC is usually very small gt wZ gt w0 The general shape of Vod versus frequency is then plotted below on page 20 o quot 10 a I 7quot 1quot p O unsl 7s in dB 0 o T 10 I 3 I 2o daldecade I l 9 20 l N I 30 I 40 l I I 103 1 105 39 105 u log scale ao 10 a 5 x 10 0 I I I 20 l 3 I 1 40 I 5 7 I quot 60 I l I I2 80 a 3quot I l I 100 l I 39 l o l 3 I E E 120 quot39 I l I 140 l l I I 103 10 105 105 u log scale Looking ahead to feedback conditions for avoiding oscillation we want 76 phase margin unity gain in the open loop part of the gain That is the actual phase angle of the minus 1800 should be 3 76 76 34 1800 20 2 Looking even further ahead to the flyback converter operating in CCM we will find VET S yd le 1SW2Z1139SWZ2 That is the flyback ds as bsc converter has a RHP zero w f R L f0 This makes for a very unstable situation as shown in the open loop 70 plots below in stark contrast the flyback operating DCM does not have right half plane zerol From ts WZ can you make the case that the output has an undesirably high phase lag at high f Flyback converter Open Loop Bode Plots have some oddities in that the low f gain is non linear This implies that the precise frequency range with 40 dbdecade drop depends on the low f gain H ll u 7355 and 10 quot2 444 x 10 r 50l I l l l I I 40 d deecade ain plot in dB G I E I 2 10 103 104 105 105 degrees Phase plot in 120 39 140 160 I l I lBO it I r y 2 3 5 105 D O H O H 0 on log scale Nottce m the phase ptot we do not have enough q m rgtn an the open toop system response teHs we come otose to tnstabthty at umty gam gt180 Thrs t5 undestra te 3 Summary of Phase Margin in Open Loop Plots Betow we show fourdtfferent openrtoop Bode ptots For HW 3 please tell which are stable and which are unstable c a 5 w o g 1100 i429 x I I I I I Im Y I II5 I In mu III I47I Mum WWW t may by mm m mquot s Mlmmtam mum E E quot5 Tx l m we It m m5 r n WWW albumen zqu a mm am What occurs m temperature oha prefera phase margtn of 60 to address these prootems We wm vtsttthts H I detart H I upcomtng teotures c for sm aH com ponent vanatrons nges component agtng Most destgners 4 Further Examples Lossy Switch a Buck Boost Erickson s text pages 212 217 D1 399 Q1 M at it N J vQt L C R vt Trans on gt Ron DC losses Diode on gt VD V V9 VD z DTs x D Ts v Y i9 igltt R t Igt vQt L CT R vt vQt L RM 0 392 10 V10 Lo d 39t 0 1 i0 0 1 V mm 04 lizgtlooHvot octatiwt39lL vow no vo V ttttttttttt A1 X02 B1 110 K E A t B dt dt 2 X0 2 23 39 l V jg 1 0 0 0 0 g V0 VD I I jg 0 0 41 0 0 vg V0 VD i i i i i i i i i i W C1 Xt E1 ut yt C2 Xt E2 ut Next we get the ltgtTS average matrices A B C E by time weighting by D and D quotRon 0 0 1 39DRon D 39 39 A DA1 DA2 D 0 i D 1i D 1 R R R D D39 BDB1D BZ 0 0 CDC1D CZ D 0 EDE1D E2 0 0 Ki 2 Aavi Bavv X X0 X y Y0 7 S Cavi Eavv d D0d 1 Steady State Solutions 3 0 39 DRon Dr 3 EH 39139 R 24 Vg Aale B VD Vg I 1g D0 0 0 V I gt 1g Cav V VD C A391B V9 9 av av VD dc solutions Equation for V output and Input g D 1 I 1 Vg 1 D39ZR DIR Vg Aav V D 020 9 1 VD DI V 1 D2D V9 1 CaVA VlB g g VD 1DRon DQRD39R VD D392R DC Model Circuit 25 2 AC Perturbed I Linear Solutions A139A2X Br Bzu C1C2X A E139 E2u for in front of d terms A139A2XB139BzU A K Afg B A yC ltE Vg39IRonVD Vg39V39IRon VD 0 I A in X C1CzXE1E2UI in y In standard state variable form the matrix math is A 39DRon Dr A A L or it it D D39 Vgt VgVIRonVDa 0 C 0 wt 39939 1 wt 0 0 out t 0 0 A0 0 A igm D 01 V L10 m 0 0 VDt 1 Hard to get a physical hold on matrix equations In fact we cannot easily get a complete circuit model of the whole converter for ac analysis We can only separate out each set of three equations and then get a partial model Equation L dit dt 0 l ma DRonia Boga vgV1R0nvDampt 26 sLis D fs DROHRS Dvgs VgVIRonVDds The circuit representing these equations A L DRon dtVgVVDRon L dimcit Equation dft ft A C7D t7Idt dt 1 R CS7s D39is 1amps Circuit 0 d0tdt 0tR D39t I3 011 0t R Equation iga Dit1ampt igsgt Diltsgt Ialtsgt Circuit igt 090 Q I30 Dit A Vs Later we will get to employ a in a complex feedback S loop so it s open loop form is good to know well at this point b Erickson Problem 78 Buck converter with Vg possessing a source impedance Rg Rg gt Q L mgp cFI R lt t ltr x gt iL energy terms V is Vc a state vector Vc U gt Vg independent inputs Vgt y gt ig dependent output DTS Qon w wg go L CTI ltR r 28 X w gt4 X m C e e e e e 6 Wm L w o a w I w e 0 9 I L W 69 TL ltamp w mauas slta lt e e e e lt 04 mg C 041003003 6 gt gt gt mo lt 0 AW W a a E o a g H A O 0 lt H IF 0 W e e e e X W gtm Wm au32 EH lt e e e lt ON mm Get time averaged A B C E R 1 DR 1 AD g D O l g 1 1R 1 1 1 1R i ii W B D D 0 0 0 C D10 D 0 0 0 0 E DO 0 D 0 0 0 DC Relations DRg 1 0 L L I 9 0A Bg J L vg 0 V l 1 o C RC yCEg Ig D 0 V 0 V9 gym 0DRgVDVg amp 0VR Eguivalent DC Circuit Model Vg gt AC Relations vg Rg A1 A2ltB1 Bzg 501 C2ltE1 E2g I gt I gt o lt Lm Q I r w gt t gt 2 A 4 2 6 r z w o o o mo 6 e e e e e an gt M w m 2gt1gtviewi 5ch I gt gt E E 2 of is 32 e e e e e e M o M m w ma ouximimwza P a 9 gt gt r A u Iow i lz vg a a gt gt a gt ammulelw Aw anal m cltm02 gt0 08 a Om m m Acdc transformer model R 1 R g g RDR g1 s L CRHDRg s2 LCR RDRg RDRg Lsis DRgis As Vgs1Rg 1s CsxAs Rs igsgt Disgt1 1ltsgt A S Solve for Y O mpu nl Wink many lyre nmpmnn mm m m erlym M 7 mulumlmmw Snmlhmuhlm mmmmmmun hnvrhmrcnpuwunws 7 mm m wmmk Ccmmkcum aumvml lylluv mllrvnumdlnncuu Mu pl39y m m lucx n m Mull Mmer mm much hmmlcr mug of tquclvucs Alluvmh31mxllymangmnlmvh mm u n upcmmuv mum many a m M pummm mmnulumungmpummm AmMuMunnthmmlrmxmumlmenlw39 4 Wm n mzm n Nmmme luw T A mxumkzu mm mm umulumelmmmc I mu m 1mm mmuuuuemmyu I 100nm kn n mm1um Mym mka an Gancmhud upaulcr gm 13 5 25 equlu lnl m carnllnr mm Wm mummwl mm Wm ham mn gum un Wm mas n man m m mum phlln ch MW man A mm m mummych by amquot up Manny wuumml A wamm ewnnwmdwun mum um w mum uch mam mm mm m umy mm M m umnuypmnlcnpac mn r Thttnmrukmkadshuudum m mm mdumncrkl J Ind npkmumu cm ALArgcr m ECMummammalwumlnIllulucmlaysrhuchuul1Kmpmmrplma w m pmulkl mu m mm m WNW 11 m mm mm quotMm Ihzmmlvcnnuu use a rmmnnccllln 1mm 14 J qmvnlcnl clrwh w mm m mm quotmm s lyymu 0 mull rmnwnrtd m m hqu mman M n maybe mm mummummmnm xmm mmquot inhrgzllmmmyhc chm wd nlnmnmmmlvh c np u In cl 4 wrws mmhuuxmm um um mauum me plum mwnre uml the n mllr mm m mndmcasxumcdmlhmszml leqmvnlzl mummy InIw39m W gt y wm u 572 7 wwi A 7 Fume I smmlmm Wm nan mun Again um bclvmur am gt39n mm Wm mrcuu ls dmcmumd by nxnmmlng W5 nymcunnmxmmwu n m rungs uf quumu ulLlnvpum anh kml mm M mum uhml umHl mummmmmwmmm m upuluhmm llmslhccupacmxrmdu Hm m quot11quot m manqumymumm m unpmmm mm xsdnmmalcd hymcxdmlwpammnw mm detlmms mumAxum mdungu mmmmm Wm m AK nyqu m mundane 5 may m1 m m mmulmlurcml x mmumc Tm minim an 1 msumm Irrlwzncy nl vrcwucunn mm Ewen by m r M WW quotmm Icyand w menmcr m mum mm mm with m mluclwnrnmlummmg m um quotmum nnpvahb mmuly 4 m muuumm mm I new m an my mmul my m maximum mm WWW mmm upml y mm mm mducmmz anhc melnrund Mm ind m Au cnplnlml Mm a mad Indu lanu at 95 m m39 V m vn m m39 m39 m ma n M Inn u use M mu mm m M ulmqucuuy nmrmcm mm nfuymvu uul mm In wuumm m A plnl nnhr mqu mm mmkm clwulh m mrwu anymm xmn m gun man u um r m m mummy w mm nme ma m Ilglrhyumu u n quota m mull15m mephmnmmmmm nmmmmmummmmu u mummu IE39VIMHLunHlWHIIII mummy nu mumm nvms of ml arm my mnalnm mm atlunl mm nr Alnkrmmnxlmnnm lmluslnrlmbcwmul mmulmmmuummlzmlm nnnmrnuhwlllnuunewp um lrnlr gt r nhywnl quottummy Mnuun mm mm my ullwl m nvlmmmnn mum alslumlmdksnmenolslmymgn x cmu um mm nkomun iusccvuhlr mamm memmlmym amthng Mm mum 91mm mwcmmmr 52x Super Capacitor Theory I Activated Carbon sheets immersed in electrolyte I Construction similar to battery 7 quotquot e h 30155 9 quotaE I Two electrodes Immersed In 8 electrolyte e I Difference is the electrolyte is not NW 0 used to store potential energy IIIin g quotquotquot quot F39 new I However since electrolytes do m have impunlles ii CheErrSti39R35i reactions leading to arrnmmb um I ii I Finite Lifetime 39 Super Capacitor Theory K vMucs I Instead of ratings such as micro fared milifarad or pico farad rated I as kiIifarag Large apacitanoe in small package 5000 Farad 27 Vnks in Coke bottle Ef ciency No chemical energy storage No die off like batted Increased Ef ciency resulting in longer life span 6 a M 19mm mo r39x C 39 T M 0m Scale 39 Supercapacitor Applications lt Ah 139 I Super capacrtors vs Batteries 1quot C Batteries absorb 60 A E 5 1quot wtquot Super capacrtors absorb 95 quot2 R losses Supercapacitors have a longer lifetime Operate over a larger voltage range Much larger Power Density Wlkg Limited Energy Density Whkg I Used together battery life increases by about 250 M3 VT I quotHL WW I Fig1 Batteryu rm r mu l isunuufu arrangement r Ca pqgnivg lt W A J Vmin Tmsch Fig 5 Discharge pro le of an ultracapacitor V L39 l v Ullracapacitors only Ultracapac ors Voltage 0 01mm and 21 boost converter 56 V 100 remains 40 V 55 45 energy used 87 remains energy used 22cell ultrarapacitor dlschcarge curve 20 V Dr 52 seconds 13 I to 4 MM quot5 so A at 90 ef clancy 23 seconds u t to 40 V with umacapacnors only as 1332 ms onvener ig n39 L electronic ECE 562 Week 10 Lecture 1 Fall 2008 Week 10 Lecture 1 Su m mary Slides Topic 36 Linear vs Switch mode converter 711 Regulator requirements and applications 1215 PWM 1635 Flyback converters 3643 Resonance and ringing 4448 Diode stresses 4951 Synchronous rectification 5255 Problem 65 5666 Lm in flyback converters 6777 Problem 62 7889 Snubbers Linear Regulators divider technology Loeey and linear MOSF operation Poor efficiency unless VO zV39N No way to increase voltag or to create negativ voltages NO electromagnetic interference as required for microwave power rails in cell phone transievere energy i 39 reactive ccmcnnte and lw loeedigital switching o High efficiency for any VQg vw 39Can increase decrease Well create negative voltage Cretee electrcmanetic interference as 39 39 quot VREF V Figure 319 Basic lineal voltage regulator W VN V sw IT M J V xv swuws OUT VOUT r v Finer 5 VlN V r v my I T V ON CK D v 1 RLOAD T FigUre 320 Swilching regulator principle u 4 Chapter 1 Introduction 839 Vccwa Vuo W 2 VTT Vccmo V HE C K Vccvno VlO V L MfM Vvo VTT E Vi VNBRIDGE CLK Pentium VAGP u Motherboard v Pentium II 39 3mg Motherboard Pentium III Motherboard Figure 13 Nexr generation motherboards require a higher number of specialized regulators g I Small Electronics and Bucks Devices El MP3 Player Cell Phones Cameras Require Buck for logic control El Extend Battery Life El Smaller packages Very Low Power G 15 Volts 1 mA to a few Amps of Current 7 Power Range R 439 D Driver 39 Package Wireiess 39 lt 5 V 200 mA 13 s I I 070 5075 LLPMLP CSPIBGA lt 12 V 81 A T0268 T0252 sow T880 DFNEP lt 30 V 38 A QSOP TSSOP MBQFPH 4860 V 10010 A T0268 T0252 sow 75509 DFN 600800Vlt10A g DiP SOIC T0220 Firgum 241 Package options versus target systems oftenthe narrow bot eneck through which heat has to escape from the die and hence its thermai resistance has to be minimai like in he T0220 pack age iliusxrated in the iower righi comer of gure 2 1 1 In between we nd a siew of package shapes and forms hat t the intended applicaiion deliv egi hg proper p wer o age cumgm or size charaegeristies 39 v V v 53 Applications LCD Displays Handheld Devices Portable Applications Cellular Phones Digital Cameras Typical Applications I Microprocessor Power supplies B Low vollage 15 B High Current 100A B Low Noise Low Ripple I l Today39s Sewers Contain Several Microprocessors l Businesses May Have Several Servers I Uninterruptible Power Supplies UPS Importance of PWM Swilchm0de converters quot employ a onaff power my swnches so power mm dissipation is low w y PWM Duly cycle D is 9quot used to control the switch output power mm Inq power conversion 1 ef ciencies exceeding 90 are common mm about twice that of a linear regulator Figure 3 24 Analog modulator N 39 0c vm TON Figure 3 26 Switching regulator block diagram quotwhich 39 V D Su gkquotquot5 Q 07quot a L Y k ha g39n Wf f 1min m1 A10 A1 um rubs Lulure u m a Inlmdununn on or l u n39Tnnslalmals coupled lnduclun In PWM Convenzn W or Tlanslurmws to PM Cnnverler Circuits 39 7 9mm Couplnd ln ucwr ranslumlar mm A Origin onna yback mm m hucmmosl mm Model or COM and DOM 09mm 0 Encksan Pmmm s 4 1m Transismr FIWR unmamenuuon m ncM Operath m Flyback Con ve er Mode Tuanslomm Mm 551 LN m m IM unmw m a Man mum mm us In mu 1 mime m mum mm x 69mm m mum mums u mm mm win on m m mm mm mmquot mammarymm munnamnmrm a umtmmuqmchm lmugun 53 I MImlmlmdmu I E m wwwmmu a mmmw ml Lrc an mm mnmwmu mm anl wmmwi l yvl hmlm nLWMI Mor 39 4 1 GiAtwbm an m 93 a iwguww Ricky ta x r i u h m 9 may K G waoo wEmMVBj l u V 8 Mm 1 H 9 EN 1 119 TIHMII lt nM Hp th39b 9 A 5 If 95 93 ion 399 1b V Subintervall quot 39 nV wme CCM39 5MB rippl quot V appmximamn leads In Q Q L vv a v i l a all 39 39 31 32 Knife 4L AM V39M 2 D mnm 1 3239 quots iuu h v My no 11 l a on D on G a on Dy Snow n7 M M m Wm Vl1 3437 CCM small riPWB appmx ma on leads lo radii e m immumquot be Loft wikk Lh 5A9 41p e M l HUNKm S w Lhquot gawk Th39e Kffback transformerquot 7 8L5 I a Mama we Err k quot v A MOWln i g inductor Symbol 15 same as lranslormer DUI 1 m v i mlonner39l Em I amtmin 4 magnauzing Indudanca Magnallzing inducmnca Is a39 5tquot l relatively smsu un m does not simulxamgum ow in primary and secondary winuvngs DI lnslanraneouswi in v I i 1quot 5 Av 11 lns39anlanaous and nus 1quot 339 Q Modem sma magnenzmg lnductanoeln parallelwilhldaallranslpnner randuuwulmam wky rmpmmwmm v er 439 m H39Lul CCM Flyback wavefnrms and solution 3 t 139 91quot vanm halana M nru Converswn vauo ls 11quot quot m m um 1 g I T Charge balance v04 017 WH S U 9 Dr component annurce cumnl Is It Wan um I u ampm Emma numb 6 ms 79 M Equivalent circuit model CCM Flyback quot 39 n ma Mu na 1 u rummm nmeu xmmks Mmr5 39mll39murlmuh Bwk onquot J V m I D NV Id w 39 um S mu 7 Flyback con guratio a In 339quot I l C1 5quot I VNg I tonkc n1 V vaanxmz t 439 L quot y w 1 0 LC 4 meme 1W Lm 5w0 1 Sana 0 V 7 3 95 The quot yback transformerquot 1 39 I u 1 A Iwoltwindlng induclor Symbolls ameae l lranslnrmor but lunguan di ers swnwunuy rem ideal lransformal Energy la ored In magne zlng lnducanue 33quot 39WWW M m n 7 l l 1 s Ins39anlaneous winding Instantaneous and rm Mode as small magnahzlng VW u r 39o J I A induclanea n parallal WHh Ideal Lranslormsr nnmmnnnrn m mm Discussion Flyback converter 39 39 igh wva deelx ugad in law power andor high vo aga apElicag ons 5 Low pans mum Munipra umEuB are easily Dblalned mm nunznnnn addilkmal pans o envea isoxamd mnverlars 39 E 3 a ous oonducuon mod DCM analysis DCM hucHwosl with lums rauo rummm y quot5 amply Comanwmuh LMsono vhack convenar ISVSSV M mm MT wT 1m quot 39VMI min In IF LMSOOO 0 80 V power MOSFET transistor 2 Ape 39 Highvoltage start up regulator 39 Programmable output voltage 39 Thermal shutdown quot 39 Programmable current limit 3k quot6 30 Line undervoltage lockout 3 39i 39 bowpower shutdown mode 39 quot 39 Con gurable as yback boost or forward regulator 39 Programmable control loop compensation Pinselectable frequencies 0 30t607l2539MHz 39 Available in TSSOPl and LLP16 packages w o nlon L A Vouuulvuu Vlwvmmf ml w HIM b5ww 3 17 m A l UM l u no I p4 15 m 39 r i m ww o m quot xv v my V 6 V nvunlm Avnul 39cI39XM mumum nuluuluu m SK 1 men M New m mumou me AIM mmm m mm Duouni 4 Wutunzw 15190 Mmfv u 1 D fth do 42w 2 7 iErVAiSA 5 P 4239 21 r r 93x ha no 3 a f Hair ha a n both if h E 1 Q shes V 11 I F7 174 125 7 u c M4 am 5 a vvl 39 I e Vw IVTLn Yn1nr39119 h x V 9 Jim Vvlnqg 7 Wax 91 V359 nglwa39g M6 39 Md 5 L d1 w WM 1 an 1 CuLM i a m s Vvk mm m Irlyluuk mumm rlmmulic HMA LM LWWWM mm g um g 3 ma 11 51 H L 1 552 5er Tum h 71 w vulva 531545 i5 munquot N 655 LA l3v W 3191732 Dc a L 1 M Lllmwnaihi may E 9 Nut km 0 W vaLm I m quotquotM 7 v 1 R V L 1 4 t iv I AUDIO POWER V 39 39 nuance stunanl zquendts m gum by Eqs I an I quotLquot In LMycw rm u h e quah the nwnanl frequznq39 an 0 e my m1 3 mduaanct rm qunb m resonanl thuenq39 due m mm mm 1mg mdmmn he Hans 1 up 5 me Knnsfnrmur mm maumm mull m mmhmu magnruzing andmm and c mulls he umrnnmr mmm npmum 391 3 30 n 0 09339 03 a Lh E h r13 up w u xx 8 52 a 33 533 r C an 78 ha 33 l u gt 3210 nayw 3 AR 33 839 T8 2 I quot39Ve 35 Transistor stress m yback converter 1 is Vdspk It happens when 0 mm or D Iurns on only on inmml 3 andmmains m avemgc powex 1m P m 39 a 6 1 am anme TAMAMI Luquot W a M 39 1 a m M g l nFIC LPFWLJ MT V6 1 I M kc gtgtgtgt W Tmnsisxorvollagepeekv H 1 M VdpkVgNlN2VVdDD 1KRDIRVE which MkvV Nu 491 Ll C an M an M m The oicilhlion Enquency ram uvnr vollage U dummch by 1L and Cd native ammo I 53 of Alex Sin 1 1920 Avrbnxpcnznu ta lt 320 w s D A r 05 inan a 73 we main Flair 35 035 23 Ear N 031M h ap 4 u 35 do 123N 035 am set 336 3 lt01 JAKE 9ka of shes va f p an CAioAA t quot I n a a v V 39 v L lt9 E n a D ween V VO b haubnn V5 711 Ta lnu39 wt 1340 san M bans n1 N vs 5V m4 d n 9amp7 Wm 6 l 12 M L1 a 6304 m ghbw 415a anuses 110136 Emo um sw 1m Eng N 5w awn h cn h n c if ranTh 111 E quot mukc zguqmc quot1 an 11 15 Hunk ujhv EMS 2 l d H1311 1m a wu y Tm n32 Wm 9 win 14 fm wu This 39 L r54 quot L l on r 4 h kw u 1 Co flsmlms v l Auk on 0 o Vamgcon dichan I Vano av M 160 I JV VD w Q mmyr nunautumn no t f 1311 um mm m ta W 1 A 54 w Rays 9 w Nt Lula Diode stress in yback converter h Voltage nnglng n hippem duh m I t M mar revcne maven on x bw i d I quot quot5 n v Dump wing peak Vdpk is Vdspk NZN NVNW V v gal n 137quot gwlmzNuvm 2NlVng39 Eu v1 L a c lylt2QltvN2NxVgL m m osclllnlian frequency for the ovalvolugn is t dammm by LL and ca 4 mmm GM7 1 is um fmr m M I m rauud riv 1 my Lg co 1 tub um Ev V uni MW 1 1 awoan 5414 1 ANN 1 gag N 5quot ansquot ligJJnmullybatkKvmquot ugwduur mae vcdlram WIDgeKuuthesrnmmmar an I wwwallugrgmicroson L Sgw v o 41 u Ede Features of Magnetic and Benefits High Currem 0W FuIy Integrated and almmedgolmm Smal Patkage Sile UlrmIow Power Loss Low Re nance 3930 PW Very Low Thermal BM 9 ErmaAccuracy r Two sues w 6m V650 Lithr D Swum him v 5 247 1471 u WW3 byukranavs F21 quot I SMPS RECI39IFICATION Fin 3 91 Maw H rt E g 39 9 IE arr EL n Md pk PI 4 1 e W 5 La xii 3 2 h mL P w bl HE mt n Ssh 3 LfZVufTKT z m vN l N FY rd 5 EENH Q3 4513 nzkxi m OFxfos 9 Ml V mg m e QUEonscmldjy V003 35km 29 mnmo BS rwlmginp W 63 003 W by La 55 rnhm Burger w xx N M W m h w on it 6L hi or f m w n gs w Equivalent Circuit model CCM Flyback 1 Fundamentals of Power Electronics 64 Chapter 6 Convert r circuits 1 oov Wis A 71 1 I w L 51Mquot 11 Nf 90w Fig 1 Typical fyback converter 3A 2 7 2m 77 v 5A 1 0m OIDFF Is 15 12mm 7511 39 lt 10p5 gt 105 I Fig1 Typical waveforms found in continuous mode opera ion function of the dutycycle COI39INO voltage nk sure ch k Cynic the 0 Mann L L 39 WM wryM a rd 2m gt thee amok Ts Non an a I on w f iuj LLM l 39 u 2 24 pm 4 4 m inma p W L 6m in F Iy bMk 7 ELQ39rL Frau Vii 7 eM k 5w 1 Saw qu eye I quotL a quot z Ln Lu 0 1 3 91 Ln 5 Lquot N L 3f gal Wk L a v a a lt 170 2 1 f 1 0 5 quot r a Lu 3 5 4 H 5quot Ln mun ll nu w L 5 p van mm m r 4 7 mum n w 3 39w L i 39 On an l m mme 190 Mm mm A uK a n a bf I b I 39 G I n 4 I EWI M 3901 WW W m 0quot I me wrlnl um I a 3 l w mmumm mu M1de w munm z 1 quot I a An dealle BH haremHm for m mnunmm mode Mam trauma Ln causes uiL V M mm oz ML 732 1 Dan M 39 cwquot cuquot 173 Gar 24 cier 3951quot Bom G aul D a RR0quot Q0 1 Ad394 Q 0 quotD a 3 93 Baa 344 W 9 I no ms porliun m lhE cycle and dc c Wed energy 0 llw mm on lhc ischurgx39 b h Irnnslmmcr is o cn describe lt c aseofu y g a coupled Inducmr Dm Hg 1 Dead llme Iota Ilyback random increases 15 the Ho39 agetapdaror appmarhu a fitmarge 0 Mlmhwmum 1 s V 11 mm 9 gt7 V3 blushv 1gt w 5 ShupLJHC Fquot L 4 h thaw nt46 a 0 l39 o Puquot 3 L mm Ewi d x 9w 69 V 1 Vquot 39VI R qt 13m Jab Wk tumVJ Y mVuo39nnxez Mutt brim 97m V5anvll n F 49 o m w vac L I A u rbog 5 fuacu No1 22 was E I I mar k 5 6 l o 5 r n r E a r w and lt 0 1mg mari METRE i m r nirfi wianz 23 HI 5111 crnm 91 3 5 2 E 11 Ea u 0 H31 quot a risesquot 36 u 1 L d ArriLJrTrJLdiL rL di r 2wa A1 1939 gt151 We Emma e 4251 C39 Z ILAI VGA 53633 3 33km gtugt I 15 mm hx me quad wall gt agtuxgt T I in p 3w 3 4 a r AIJH 33gt 9 v92 0 2 6 2c antWm do 49 I P v I 1 SIN n ma Taptflv 223 d 94H v5 u m t it cg n a a u g v v s M K A mm x h f mg W JIH as lurk Harpnwv r 604 st Yangon 06m I V N H 0 049an 910 W N in 1 K4 y A m Em fr 409 r we lt n u 5 NF mgr a 95c V H 9H 3915 A arm FM I ll aw 3 51mm dammst with M 1 oil o 4 Slowing down nu 3mm unnum Bans mm L m nln mm aw m1 memny Mm use mm sunwen VoHowa from VLulld Inmmmloamuonllvmnmmwuoduulmnw W I by may m In mm 7 bone wy m do mu 1 m umply Ikmnr uwl39ch emu molth a 11 muWimm quot mm m 1mm mull mm wiully m min plans mm mm Eulools um mm In Anmar mmquot wly In an chm in belles mm the nmup anlvtlawn ownmmmon noon my mum Melon snuhmn m A null as mqu lvom sum None lo Ground mm a mum m w m X 11nme 247 I A 39IIIF quot D KnownInnuan V I I W El mm W y W wownthIuAJ able1Hrmmlmimumy m w M Jv n human alum tum Nu1 um memw mmmmm rmmnn m 1 T 5 H i HZ I m m W w 1xm39 1x1 M Snu39muaf 2 a Lot lt Wu Lg 1w L a 1th v 3139 139 mail sw39nt Gm 9 quot quot3 quot3 G 11 5 4o w 1 34 quot1 39amp211 LVM 5A 0 5mmquot V v u m Min Vquot V a Ll quot VL 4 i VFil39 I5 50 La Figure 2quot mnm mnrrnrr 39 h primary KC nuhhrr Ringing qumfr u Milt quot t palion and damping Figurz 2b Flyback murm mimian o39Wmakn qua gdaw39mr a m 541 75uzLM7 6391 umhv 1me Sanka Tunu 0quotquot 1 3430 is n15 A saw4 l quot 5quot 3 10 121 Qquot hquot or hale 1 C00 swan whuex a 5 L1 ranahr 1 u R74 90 17 y 39 1 V V r 1 1 i 5 wth No Ad651401 It M 1 11 v 39 th Va gm 5n mmmm Iligzlu warp0nquot will uul nulrhvu Ringing rumm III f m r 5 1 J mum in m 1 mm rrlrudnry I unn an s wanurn will mull mr mulllry mom I u LECTURE 8 Fundamental Models of PulseWidth Modulated DCDC Converters fD l QuasiStatic Approximation A Linear Models Small Signals Quasistatic AV 2 dt AmpSecFarad AI Ldt VoltSecHenry 1 Switched Capacitor Network Dynamics and in SteadyState 2 Switched Inductor Network Dynamics and in SteadyState a General Issues of iLt b Buck Circuit Topology c Boost Circuit Topology d BuckBoost Circuit Topology B EXAMPLE OF BOOST DESIGN l QuasistaticApproximation Quasistatic Basic Review Signals in the quasistatic case V Usually in simple RC and LR circuits there is an k Eggsin rm exponential change of signals from 0 gt Vdc t ldc Linear slope for small AvAi A useful approximation is for 1 RC is that the exponential signal reaches a certain percent of final at various n1 ln10 1 gt 90 at 231 2ln10 1 gt 99 at 461 3ln10 1 gt 999 at 3 23 691 1 RC sec for V 1 LR sec for I But for times much less than 1 linear behavior occurs allowing great simplification ln switching rather than exponential circuits fSW and TSW are chosen such that they are much smaller than the RC and LR time constants A Small signal linear model In short since we usually have in dc dc converters ac changes that are small and switching times much faster than circuit time constants we can use simple linear relationships rather than differential equations For example the triangle wave ripple about a steady state DC level h L a We can linearize time behavior for AvAi ltlt Vl T ltlt RCLR Then capacitor voltage and inductor current signals vary linearly with time dt 2 Ave dt AiL 1 Switched Capacitor Network Assume a DC equilibrium exists Assume a series switch operating at fsw with on duty cycle D f5W has a time period Ts moreover the off time between pulses D TS is much less than the RC delay In short the switch is on for DTS and off for D TS Drive to RC network is J assumed to be a Norton Eq Current Source R 0 v0 Switch at f8 Switch Closed for DTS and RC charges due to supply current Switch Open for D TS and RC discharges due to load current demands a Consider the switch open Load discharge period D TS During discharge of C by lout VoutRsteady state we find the voltage drop across C during interval D TS is AVduring D Ts D39TS Clearly in a PWM dcdc converter in steady state during the next switch closed period must recharge C back to Vsteady state So a net current flows to C during the DTS So in equilibrium at the output we have a maximum a minimum and an equilibrium DC value as shown below DTs gtlt D39Ts DTs prior charge Discharge Recharge PeriOd t0 T S For steady state to occur over a switch cycle in a capacitor VTS E VO OthenNise Vc grows till dielectric breakdown of C occurs Discharge slope over D Ts VoRC lC appears linear if RC gtgt D TS or Av ltlt V Charge slope over DTS ISWDC componentC ISWDTSC must equal AV lost during discharge for steady state 2 Switched inductor in steady state We apply a square wave across VL and see iL vary as a triangle wave a General iL vs time over TS A VLlDl Su 5 I HTS L0 lt DTS D39Ts V ramp down ramp up Assume vL during DTs is positive and that vL during D Ts is negative In the most general case vLDTs i vLD Ts due to different switched topology of circuit during DTS and D Ts 1 AI EIVLdt E amperes We repeat that VLDTS i VLDTS due to different switched voltages We assumed that for steady state to occur in an inductor over one switching period iLTs E iL0 or suDTs sdD Ts Otherwise iL drifts upwards or downwards until i gt icritical causing inductor core saturation Note starting at iL0 going to LDC over a time DTS iLDTS iL0 sUDTS ILDC i Ai SuTs SuTs The proper D value is selfset for steady state to occur likewise starting at LDC DTS going back to iL0 at T8 takes D TS to accomplish iLTS iL0 iLDTS sdD39TS 0 sUDTS sdD39TS lt Voltsec balance in steady state D id 2 SU D39 That is for steady state to occur the smaller the off fraction D the larger the discharge slope sd must be and the bigger the on time D the smaller su must be b Buck Circuit Topology In the Buck the inductor position in the circuit topology of the dcdc converter varies but it always has the switch attached To avoid KVL violations we need to have an inductor to buffer the Vout and Vin which are temporarily connected by the switch network Here V0 DVin and V0 cannot exceed Vin The right side of L is fixed at V0 which for regulated of feedback supplies is often dead constant The left side of L is switched from V9 to ground Vg sometimes varies for raw or unfiltered DC but is usually considered constant as well Over the period T8 the switch goes up for a time DTS and down for a time D Ts L For switch up V9 T V For switch down sd A s a very fixed slope Buck example For Vg 20 and V0 15 we find D 075 for Buck topology The vL and iL output waveforms for the buck are shown below V In Voutt D g g ltVoutgt D 0 time 0 T 2T IL W O 50 1 00 1 50 V0 Dlout P0 Dvinlout 4 Voutrms J vin 5 What is loutrms A simple dc motor control is shown below Recall that Vg k wmotor rotation By setting VTDC via D we can determine motor speed f switch 39 20 kHz One can show for Ra small Vg should be the average value of Vt D1Vin hence we can control motor speed by varying either Vin or D wmotor DVink c Boost Circuit Topology The left side of L is fixed at V9 raw dc and the right side of L is switched from Vout to ground Again L keeps KVL violations from occurring during switching L For the switch to 0 ground m Vg A V9 Vow su T 5 For the switch to V0 V V 5d QLOA 5 Here VoVin11D1D This gives output greater than input Boost Example Vg20 Vout50 gt VVg 1D 104 D 06 T Unique fD for Boost topology Verify sdsu E DD 0604 15 3020 We can consider the l as transforming Vg into a current source input to the switch to achieve Vow Vin1D and lin lout1D Note Pin Pout both on average and instantaneously as we assumed zero losses in the converter switches as well as L C components Consider the boost circuit below L m Iout F l L T lt Vin 5V T Vin CT lt R Vo120V 7 l R 288E Goal Vin 5V but lin fixed 1 01 V0 120Vi 01 Pin P0 50W Hence for zero loss lin 10A and I0 042 fSW is fixed at 20 kHz or TSW 50 us Solution gt The off time of the switch transistor is D 5120 0042 Recall D D 80 the diode is on for 004250 21 us out of 50 us and the transistor is on for 479 us This makes sense as we need more time to build from 5V to 120V than to discharge the 120V For the lossless operation lin 505 10A and we specify Alin i 01 1A This Ai specification sets the L choice e L didton time of transistor 5 L 02 A479 us L3 12 mH to insure Alin lt 001 For lossless operation lout 50120 042 A Our AVout 120 001 1 12V this AVc sets the C choice i C dvdtoff time of the diode 042 C 2421 us C 3 833 uF for AVo 5 001 Finally prove to your self that a i 50 ns time jitter on the transistor switch time causes Vout to vary from 117 to 123 V or 25 d BuckBoost Circuit Topology Bottom of L is fixed at ground while the top side switches from V9 to V0 For the case of feedback in the circuit Vg could be crude rectified DC and V0 regulated DC Here VoVin DD and the output is opposite polarity to the input moreover we overcome the Vout lt Vin limitation of the buck and the Vout gt Vin limitation of the boost No KVL violations occur as each voltage supply only sees L which appears as a current source For analysis below we assume both do not vary over TS y o Switch at v9 Vg sU TA s V vout Switch at Vout sd A s sd very fixed for feedback case gt Vout i Vg D39 Now by inspection a buckboost has the simple slopes switched since no potential difference occurs in VL Upslope Vg sU TA s 5 Downslo e DTs gtlt D39Ts gt p V l l 5d 7EUHAs oBuckboost is easy because there are no complex differences to calculate for vL since one side of L is always grounded vL is either Vg or V0 oln contrast for buck and boost circuit topologies one finds for the voltage across L VL Vg V0 and both relative magnitudes affect Ai slopes BEXAMPLES OF BOOST DESIGN Below we will go through the flow of a boost design a flyback converter which is a subset of the boost topology The object is to see how much design you are already to do and how much you are not ready to do Also it puts into better perspective the filter design as part of the whole design process The input voltage of 18 36 volts is representative of the factor of 2 range of input voltage variation we must deal with The 12 multiple outputs at set current levels at each load is also typical Note in the figure below the single input and multiple output filters as well as the switch transistor 02 and its control circuits 28 W PWM Flyback Convener Application This power supply is to provide power for a piece of process control instrumentation The instrument receives its power from a 24V bulk power supply that also provides transformer isolation from the bus voltage to the unit Speci cations Vom 5 VDC at 2 A max current 05 A min 12 VDC at 05 A 12 VDC at 05 A 24 VDC at 025 A Vin 18 36 VDC required operational range 24 VDC nominal input line voltage ur 6 UC3545P 3 4s 2 8 Vin thamatir fnr dacinn nvnmnln Next we do a blackbox overview that allows us to find required power current and wire sizes 13 Pom go A 12 V05 A 12 VO5 A 24 V025 A Pm Pomef qest 28 W075 73 w inhigh PinVinuow 373 W18 v 207 A Iin p PinVinnom 4 373 W2394 v 155 A This indicates that a 18 AWG wire or equivalent should be used on the pnmary winding of the transformer pk 55PoutVinmin V 55A 39 Let us select the frequency of operation of the power supply to be 40klIz or Te on 125 15 LPquot min Tonpk 18 V125 lid855 A 263 uH We arbitrarily choose 40 KHz as the switch frequency to start the design process This set Lpri for the case of lowest input voltage at the peak current for D12 Next we consider the output DC filter but only consider the minimum required capacitor Cmin cmin I XdTminfswxvrippIe We assume a spec of 150mV for the ripple and for the time interval we assume the smallest time interval of about 03 TSW The rated load current is specified for each output See next page 14 The output lter section 39 The values for the output lter capacitors are determined using Coumin IourltmaX1 g 6 mm an39ppMpp C m5v LF at C14 and C15 Use two each 220 LF at 10 V tantalum capacitors in parallel to reduce height and to reduce the ESR Couqtlzv LF at C12 and C16 Use 150 uF 35 V tantalum capacitor Cout24V 60 LLF at 35 V 11 Use two each 47 uF at 35 Note that in practice a high frequency C should be place in parallel with the larger electrolytic capacitors because the big electrolytic s cannot absorb high frequency currents For this bypass C use a 005 ceramic capacitor Next we turn attention to the input filter section which is composed of o EMI filter 0 Startup current surge limiter 0 Bulk Input filter capacitor which is usually aluminum electrolytic as it is rugged to peak surges 15 It is this filter capacitor to which we turn our attention The less ripple desired on the input DC the larger the capacitor but this causes large surge currents on startup As a guide we state that ripple voltages of 05 to 2 Volts are tolerable Capacitors with low ESR are assumed here so only the C contributes to ripple voltages One can show that cin 2x Pinput average fswx vrirmle2 We Will assume Vrilople is 1 V0t The input lter section a 211 n fVripPepp Cm 237 W 40000H 186 F z1VW Place two each 100 pF 50 V aluminum electrol tic c 39 100 V ceramic in parallel y apacnors and a 04413 Ci Finally in the circuit diagram of page 12 the controller chip provides 0 The settings to make our desired first choice for fSW to be 40 KhZ 0 Current mode control circuits we will cover later 0 Driver circuits to turn on and off the switch transistor 16 The switchmode controller In attempting to select a controller IC one should make a list of the important features desired for the design Also make a nice but nonessen tial list Essential Nice but Low parts count Undervoltage lockout Currentmode control Low sense threshold MOSFET driver output totempole 50 percent duty cycle limiting Single output driver Low cost After reviewing the list of popular controller ICs the UC3845P appears to satisfy all the above requirements Referring to the data sheet in the Motorola Linear and Interface Integrated Circuits data book the basic schematic implementation is given in the application gures The designer need only determine the values for the timing resistor and capacitor and the currentsense resistor All of the other components are involved with the Vcc supply and the feedback compensation which will be designed later Looking at the Timing Resistor vs Oscillator Frequencyquot graph and wishing to operate the supply at a nominal 40 kHz one determines values of CT C8 R1 R4 10k0 This value will no doubt need to be adjusted during the breadboard stage Realization of switch using transistors and diodes Buck converter example A Switch A transistor Switch B diode 39B SPST switch aperaling points SW A Switch 5 Fumimurntnls n I39mw39r Eln39frnmrs I Omer 4 5mm rmliznlmu WA39IEHSISIDI fndlch a diode 14 6quot 5 39 I M G J L aim H hu1 l 00 M quotquotquot v Ink AVA A w Realization of buck converter using singlequadrant switches I I39umimuzvlmls n I39mmr Ekrlmmrs n Chartquot 4 Swmh rmlmlliml Realization of buck converter using singlevquadrant switches Fundamenuls afPuwz39r EmmiIa II Chapquot 4 5mm mlln un 9100 amp 95 db J SEET b0 d od 4quot gquot 39 Sm Mfg h WM 0r 71507r 3h 4quot TW A C 39939 mm 3 a v m 94mm 095 V 31 5 Power MOSFET Use 0 sxlema diodes dramcren39sn39cs lo prays1 conductan tam Va olbadydiode at L065 v wm malluuuu Fundamental draw Human395 F U A 6 nos 41216Currervtbidire gtiogal twoquadrant switches nos 4 1 5 01420191 n Usualyen active sm m commled by lamina C Normaly opealert as two quadrant switch 0 v I an Mdmgmve I v 39 0 whys an sbrs current can block Eilivs allstyle AE Lt quot ath A praydad Ina the intended on stale and off lafe operamg 39 ile i v BJTam z aaIel IIISEI39IIEHQGUS H m 5 399 57 WW diode realizeion characteristic m mquot quot m 5 ca be realized as sha wn Huidammrak anower Ekcmml I2 Cbzylar 4Z smm mllnunn MOSFET body diode Power MOSFEF Power MOSFET Use of external diodes characteristics and its integral Io pm ven canduclian body diode of body diode II Gupta 4 5n Two quadrant switches I m ML 0quot I Ilmnsismrcrmducls v quot397 Wm mm m I n on diode mnducti n ampm 4 5mm nllzxmnu g 11 75 46 Two quadrant switches 39 ahf39d a Y 51b Luz J Fundamlsdm iuum I 39 Chpta l wlm mm 412 Currentbidirectional twoquadrant switches Usually an active switch controlled by Ismu39nal C Normally operated as two quadran switch 0 can conduct positive or negalive onstale current nan block positive a sials vollage provided that the intended an BJTa 39 Isle inslantansous iv pomquot quot9 0quot quot 9 comm i 39 m characlerisfic cha ac39sn l39c39 m9quot sw39lcn can be realized as shown I39Imdmmnmls IvPruw lrclnvnu s I Elmrm 4 51mm mzhzulwquot A simple inverter Do zn nv 1u JV us ryPauw Etmrnnms I5 Clmplrr L 5mm rmhmlmn R H 9414 1 quot 9 1x a M Low rqowhg f A simple inverter 1 a no 1 3991 1 1 CRN quot19 1390quotquot quot 1 burn Mrc km 0 r3 c v v t o 53 6 Q 0 ID 1 V 01 o 0c 3 quot 19quot f0 5 quot 5 L a p7 mu fquotquot Fundaan um u Emmyts 5 no Chm 4 Swnd munm m Inverter sinusoidal modulation of D 11207 n V Wu to 1 quotn produce ac output W 1 V D 05 D sin mm 0 D The resulting inductor a5 current variation Is also sinusaidal 395 Hence currentbidirectional s 1 Iwcrquadrant switches are 5 required quot13quot Fundquotmural ql39um39r leckmmts In 0mm 4 5mm vcnlimliau F 5 M L 75 6 1 Inverter sinusoidal modulation of D vn20 IV39 Fundamamls arm Ekdmnks 14 45 Sinusoidal modulation to produce ac output nu 05 0 sin am The resulting inductor l Wm v V iLr quot T 2D ni39 Hence currentbidirectional Chewy c Switch mumm 95 YHO I mans 9w Salsth meant volta e source inverter V SI 47 n as a m LE Maw swq39hkcs are an yo 1 563 96 39 L mmquot 39 Fundaman aanwerElxtnuia Chap11 4 Swim mallzauan The dc 321ac voltage source inverter VSI Fumtmnnmls nf I39nwer mum 7 llama 4 Emir vmllznlimx e j munrl 115 L n I 1 030 willme 552qu 0 1 10 30 O E a lgisngi nsiia9l In 935551259 Eav i waegxn nagziiggu mii Blt iw lt slim galaxisi i giggiignig Eva mmmmmmrm m WW AA 95 52 f f 334 2 SON 5 mu W m f T a 1 gar4 39 in I 39 39 operation In stare arms 1H is dosed and 5 IL is open so that the in msnurces any to the nu ur and L 7 mm energy bl In stare I39WD 51L is closed and 51H is open so hm L Y sourses energy In the load rz d r nu currznrrhraugll me ampumpamam produce re I Ihesum annex rm may I hemmpaxhz ourputvolmyc nppte m llun un circuit Lecture 50 Changing Closed Loop Dynamic Response with Feedback and Compensation A Closed Loop Transient Response Waveforms 1 Standard Quadratic Ts Step Response 3 Q gt 12 Oscillatory decay to a step b Q lt 12 Exponential decay to a step c Q 12 Goldilocks solution critically damped B Feed back Review 1 2 3 2 zout varies withf Gvgclosed loop W Gvg Closed Loop Response Time At 12739L39fc Ts cross over fc iS at TS unity gain Limitations on Transient Overshoot a Vpklpk are fQ and Cause Damage b Approximating Q for the two nearby poles Ts Unity Gain Crossover case 0 m Tailoring via Gcs Zout closed loop C Compensation Networks To Tailor Ts 1 2 Overview of GC Alterations Tailoring Lead Compensator in Gcs PD Compensator

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