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Computer Organization and Architecture

by: Sarina Wintheiser

Computer Organization and Architecture ECE 452

Marketplace > Colorado State University > ELECTRICAL AND COMPUTER ENGINEERING > ECE 452 > Computer Organization and Architecture
Sarina Wintheiser
GPA 3.8


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Class Notes
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This 1 page Class Notes was uploaded by Sarina Wintheiser on Tuesday September 22, 2015. The Class Notes belongs to ECE 452 at Colorado State University taught by Staff in Fall. Since its upload, it has received 25 views. For similar materials see /class/210292/ece-452-colorado-state-university in ELECTRICAL AND COMPUTER ENGINEERING at Colorado State University.


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Date Created: 09/22/15
ECE 452 Computer Organization and Architecture Microprocessors a Understands basic structure ofa microprocessor Addressing Modes Understands different addressing modes for operands instructions Assemblv Lanquaqe a Able to program in assembly language Memory and IIO Understands basic microprocessor memory and IO syst organization Prerequisites a ECE251 As of 12908 Co n cepts Overview of computer organization Hardware technology CMOS clock timing Microarchitecture design for supporting the instruction set architecture datapath control path Pipelined processor design 0 Basic solutions for handling data structural and control hazards 0 Basic branch prediction techniques Memory System 0 Memory hierarchy 0 Cache memory design and performance 0 Secondary memory 0 Virtual memory paging swapping IO Systems 0 IO organization 0 Bus systems eg PCI Applications Case studies of processor core architecture Tools POC Ricky Kwok OUT Logiclevel Hardware Can evaluate logic level hardware characteristics that would affect system erformance Datapaths r Can design simple datapaths for common instructions Control Paths a Can desig1 control paths using hardwired logic 39 g or microprogrammin Parallelism and Pipelining Can exploit instruction level parallelism with pipelining to accelerate executions plus basic hazards handling and branch prediction techniques Memory Can determine e ective memory access latencies under a hierarchical memory system IIO Can analyze IO system performance Can design to latency and bandwidth c onstraints


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