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Design of Computers

by: Roel Green

Design of Computers ECE 438

Roel Green
GPA 3.99


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Class Notes
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This 19 page Class Notes was uploaded by Roel Green on Wednesday September 23, 2015. The Class Notes belongs to ECE 438 at University of New Mexico taught by Staff in Fall. Since its upload, it has received 47 views. For similar materials see /class/212160/ece-438-university-of-new-mexico in Engineering Electrical & Compu at University of New Mexico.

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Date Created: 09/23/15
Memory Hierarchy ELEETIIIIGMJ a nMPuTEn ENGINEERMG THE UNIVERSITWr EFF NEW quotEEKqu Memories Review SRAM value is stored on a pair of inverting gates very fast but takes up more space than DRAM 4 to 6 transistors DRAM value is stored as a charge on capacitor must be refreshed very small but slower than SRAM factor of 5 to 10 Word line Pass transistor A lgtD lgt AD 0 B B Capacitor V Bit line El fTRl M 5 IHMFIJTER ENHINEI ZRINH THE UNIVERSITY 0 NEW mama1 Exploiting Memory Hierarchy Users want large and fast memories 2004 SRAM access times are 5 5ns at cost of 4000 to 10000 per GB DRAM access times are 5070ns at cost of 100 to 200 per GB Disk access times are 5 to 20 million us at cost of 50 to 2 per GB Try and give it to them anyway CPU build a memory hierarchy Increasing distance A from the CPU in accesstime Levels inthe Leveln Size of the memor at each level ELECTRHIAI 15c IIDMFIJTER ENGINEERINH THE UNIVERSITY 1 NEW WEX CO Locality A principle that makes having a memory hierarchy a good idea If an item is referenced temporal locality it will tend to be referenced again soon spatial locality nearby items will tend to be referenced soon Why does code have locality Our initial focus two levels upper lower block minimum unit of data hit data requested is in the upper level miss data requested is not in the upper level El fTRl li 15c IIDMFIJTER ENGINEERINH THE UNIVERSITY 1 NEW WEX CO Cache Two issues How do we know if a data item is in the cache If it is how do we find it Our first example block size is one word of data quotdirect mappedquot For each item of data at the lower level there is exactly one location in the cache Where it might be eg lots of items at the lower level share locations in the upper level lilil il39j39l39ll l amp MPUTER ENEEHEERIHG THE UN WERE IT f 0F NEW wince Direct Mapped Cache Mapping address is modulo the number of blocks in the cache 00001 00101 01001 01101 10001 10101 11001 11101 Memory ELCELEI39RMZAI 5 IHMFIC TER ENGINEERINH n THE UNIFERSITY 1 NEW w a Direct MaEEed Cache For MIPS WWW39WW a1anaajg11ma1a 34 Hlt um Elll 39l39ll h amp MPUTER ENGINEERING THE UNIVEREITT 1 NEW HEXIQQ Direct MaEEed Cache Taking advantage of spatial locality um Win an mm ELECTRICAL amp MPUTER EN39EIHEERIHG THE UN WERE lT f 0F NEW MEXIQQ Hits vs Misses Read hits this is what we want Read misses stall the CPU fetch block from memory deliver to cache restart Write hits can replace data in cache and memory writethrough write the data only into the cache writeback the cache later Write misses read the entire block into the cache then write the word El fTRl li 15c IIDMFIJTER ENGINEERINH THE UNIVERSITY g Nrw wr x a II I Lquot Hardware Issues Make reading multiple words easier by using banks of memory It can get a lot more complicated amcrmcn a commran maximizka Performance Increasing the block size tends to decrease miss rate Miss 5 ran 1 4 as I 1quot i i 258K 15 32 as 123 255 Ebeksizs Use split caches because there is more spatial locality in code ELECTRICAL amp MPUTER EN39EIHEERIHG THE UN WERE IT i39 0F NEW MEX The processor Datapath and Control m Review THE Performance Equation s Om hasm Denovmance equamn sthen cpunme e wnsuucuououm x cm x cxocuyme cpunme wnsvmuuon um x cm cbcmaue These equauons sepavauemeumee key teams that swam penovmance 7 Can messue 0m cpu execuan we w mnmng We mm 7 Tnecmmce s usua WgNEn mm umumen 7 Can messue ms tmdm loEx caan n mum w usmg pmMErsswuhmrs Weuu anng aH m pememaum ueeus We mp emgmahon ueeus 7 cm mm m ms tmcmn WDE and SA ND EmEmahon mum we musu mow o a 2 Q 36 3 E a 3 a mauon 7 use e pvogvam coumev PO to supph me msuucnon addvess andve c n W 7 decodeme nsuucuon and vead ve stevs r executeme mstmc on AH msvucuons excep j use me ALU aHer readmg me regws ers Clocking Methodologies mmmg methodobgy de nes men sgna s can he vead and when may ave wmten 7 Aquot was magma mummy Mon 7 TVDma Exam 7 madcantgntsms ama gmgms 7 sEndva uEs huughcumhma nna ham 7 Wm msuhsm m my mm 543 E ENEMS m Assumes 51am dements ave wvmen on every moo k eye 2 n no new when wmecomvo swgna 7 Wm Dawson Wm m m Wm DOM0 s assEnEd and m Dumas m m Fetching Instructions Fetcmrg msuucnons we ve 7 veadmg m ms1mctton new the mmmn Memory 7 updatmg the pc to m m addvessot the next mmquot 7 PC 5 mam every cyste so ndoes not new an axphmtwme conth stgnal 7 ns1mctton Memory 5 mad eveq cyste 90 u doesn t new an axphmt veadcomvotst quotat L Decoding Instructions 2 Decodmg nstrucuons nvo es 7 sendtrgtnetetcned mstmc on s opoode andmnc on He d btts tome cannot mm 7 veadmg two vames quotom me Regtstev We 7 Ragt ev We addvesses avecomamm m the mstmctton m m Executing R Format Operations Rvovmatopevanonuead sub 51 end or s uemom me OD and mm oueva on on va ues mm vs and n 7 51012 me vesmt m me me Ragmev me mic ocanon yd 7 me Ragmev He 5 not wvmen every owe e 9 SW so we need an axphmtwme conth swgna vonme Ragmev me x Lquot Execullrg Load and Store Operations e Load and someopeysmms memes e mmpme memory addmss W addmg me hese megscem mad mam He dummgaememm Shmsx 5mm Va uE mad mm quotM R we Ragxs gv gmea exemaea mmmgh m we msuudmn 23mm Hie dunng dgmg men came Data emery 7 bad va uEm meaamm me Data MEMDN men came Regsem Hie m Executing Branch Operations Branch opevanons worves 7 comuavethe operands read mm the Ragr ev rue dunng decodevov squamy zeroALU ompm 7 compmeme branch avget address by addmg the warm PC to mats m srgnm mendw onsemdd mmems Executing Jump Operations Jump operauon mvorves 7 veprace vme PO wnn me owev 26 bus or me me owev 28 n Vetcned mstmcnon snmed th by 2 bus Creating a Sirgle Dalapalh from the Pans Assemmemeda aua h sagmems and add conth hnes and mump axovs as neww Smg ecyc e desng 4am decode and EXEmAE each msmcuons m one mockcyme 7 nuda39apa h Esuumcan m us dmum WW DEvms39tmctnmsummE mm m gamma 2 g sEpamm mamaquot Mgmury and Data mom 7 muww mrs quotEma mg npmmshamd 2mm Wu mmm hugs mdu mg mum Wm swab beam0 wmmg mm REQS39EVHE and Dam Memory we Mme s dawmm by ength ov me bnges1 path m m lt Adding the Control Selecting the operations to perform ALU Register File an Memory readwrite Controlling the flow of data multiplexer inputs 31 25 u is Observations in 5 u was m 7 Op lleld always in bits Si 26 e aoor ol reglsters to be ad ar always specrlreo by me rs lleld brls 252i and rt lleld reglsler bltS 204ml lorlw and sw rs ls the base 7 addr ol r ngler to be ertten ls ln one ol places 7 ln rt blls 204 6 lor lwl m rd blls l57l l lor Retype lnstructlons e oilset lor beq lw an sw ln blls lsro C cle Dataath with Control Unit


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