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by: Yasmine Kessler

STAdvancedAppDevelopment ECEC490

Yasmine Kessler
GPA 3.9


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Class Notes
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This 4 page Class Notes was uploaded by Yasmine Kessler on Wednesday September 23, 2015. The Class Notes belongs to ECEC490 at Drexel University taught by Staff in Fall. Since its upload, it has received 20 views. For similar materials see /class/212567/ecec490-drexel-university in Electronics and Computer Technology at Drexel University.

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Date Created: 09/23/15
VHDL Syntax Review Matthew Murach Basic code layout I De ne data types library declarations o lEEEistdilogic71163all de nes bit type 01UXHL o IEEEistdilogiciunsignedall de nes arithmetic for unsigned numbers I De ne user packages 0 Custom packages AlteraXi1inx or you come up with So Library ieee Use IEEE libraries note that the double Use ieeestdlogic1163all hyphen is used for commenting Use ieeestdlogicunsignedall Use workp1packall Your custom package can def39me types for example as well as constants I De ne the black box entity declaration o What are the inputs and outputs What should be the name of this component Example 1bit adder Needs three inputs one bit for operands a and b and the carry c Needs two outputs sum and the carry bit Clock and enable optional if you want to use synchronous design 00000 80 Entity oneibitiadd is Port A in stdilogic B in stdilogic Cin in stdilogic S out stdilogic Cout out stdilogic Clk in stdilogic En in stdilogic end oneibitiadd I Well what is in the box architecture section 0 Recall from logic design that the output can be computed as follows SA B Cm 11 Cour AB BCinACin o The two outputs can be solved independently two different trees of logic 0 So use two process directives o Declare the architecture section as follows Archtecture struct 0f 0nebitadd is start de ning the black box declare signals and subcomponents here Begin start processes Sum processcken clk for sync operation or use processabcin for async declare variables for this process Begin If clk 1 and en 1 and clk event then capture clk on the rising edge S lta xor b xor c logic End if End process Begin start processes Carry processcken clk for sync operation or use processabcin for async declare variables for this process Begin If clk 1 and en 1 and clk event then capture clk on the rising edge Cout lta and b or b and c or a and c logic End if End process End struct Note that the sensitivity list tells the process when to trigger In the synchronous case the operation only happens when the clk pulse is received Likewise for the asynchronous case the answer is only reevaluated on a changing input signal Differences between variables and signals Signals are global wirelike That is that a signal can be used between processes Note that it takes one delay unit for an update to occur or one clock cycle in synchronous circuits One one process may drive a signal however multiple processes can read that signal Signal assignment is concurrent The following will swap A and B s values A lt B B lt A is equal to 12 B lt A A lt B Variables are local registerlike Updates are immediate and the variable can be read and written several times in a clock Variable assignment is sequential 39 A is NOT e ual to 13 q A B In the rst case C gets B s value In the second case C gets A s original value Components Up to now designs have been relatively simple enough to allow for the use of one VHDL le But what if your design is complex and has multiple logic units Component instancing allows you to use the same logic several times For the previous case a multiple bit adder might be preferred To create this rst examine the gure below A3 downto 0 B3 downto 0 C3 downto 0 S4 downto 0 Figure l 4bit adder The four bit adder can be implemented using the one bit adder created above Note that 2 control regions exist The fourth adder is slightly different since its carry shows up at the output Library ieee Use ieeestd7logic71164all Entity master is Port a IN stdilogicivector3 downto 0 b IN stdilogicivector3 downto 0 s OUT stdilogicivector4 downto O ck en IN stdilogic End master Architecture struct of master is Declare Signals Signal c stdilogicivector3 downto O Declare Components note that component declaration is similar to entity declaration Component oneibitiadd is Port A in stdilogic B in stdilogic Cin in stdilogic S out stdilogic Cout out stdilogic Clk in stdilogic En in stdilogicx end component Begin assign defaults CO lt O Clearly the first carry in is zero For generate loops GI for i in O to 3 Generate Gl if i 3 Generate cell one bit add port map Ai Bi Ci Si Cil clEenT End Generate G1 G2 if i 3 Generate cell oneibitiadd port map Ai Bi Ci Si Sil clken End Generate G2 End Generate GI End Struct


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