Digital CMOSVLSI Design
Digital CMOSVLSI Design EEL 5344C
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This 14 page Class Notes was uploaded by Mr. Chelsie Bergstrom on Wednesday September 23, 2015. The Class Notes belongs to EEL 5344C at University of South Florida taught by Sanjukta Bhanja in Fall. Since its upload, it has received 84 views. For similar materials see /class/212709/eel-5344c-university-of-south-florida in Electrical Engineering at University of South Florida.
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Date Created: 09/23/15
EEL 5344 Digital CMOS VLSI Design Fall 2008 Handout on CADENCE Virtuoso Layout Editor RA Karthikeyan Lingasubramanian Setting up the environment a Create a new directory and move in to that directory Sun Server mkdir ltdirectory namegt Sun Server cd ltdirectory namegt b Type this command on the prompt Sun Server digitalinit Note You must always move into this directory to invoke Cadence Virtuoso You must not invoke Virtuoso from any other directory Creating a library c Start icf b by typing this command at grad Sun Server digitalicfb amp d Create a new library by selecting le New library from icib window Fig1 Fig1 A window pops up Fig 2 Enter a library name in the Name field 0K l Cancel lnetauus mm If ynu will we creaung mask layau39lur Directpry Technulugy Fm Name uUlel39 physical dam in this library yuu will nm a igchnulng y la Irynuip39lain m use nnly schema or HD data a wchnulugy le is nutre39quim dr 1i compne anpw igcn I 397 in ash ann l E m an zx39l39sung teclmla need a tach l Design Manager NuDMl Fig2 When you click 0k a Window pops up Fig 3 asking for ASCII technology le enter the le name as projecttf E Lead Technology File I OK Cancel Defalt si Apply 39 ASCII Technology Flle ml I project ta I I 233333 Teefu z zggs 1amp2 mylib Fig3 e Go to the terminalSun Server and copy the following les divaDRCrul and divaEXTrul to mylib directory Sun Server cp divaDRC rul divaEXT rul mylib Fig4 Creating a New Cell view f Create a cell View by selecting FileNewCellview from iclb window Fig1 Select the library name as mylib the library name that you entered before and type the cell name say Inverter and select the Tool as Virtuoso as in Fig5 39 Create New File 39l 0K earcu l Durans H lp um Nana mm l eelum Vlsw Manna Wm5 Tuol nrumau LI mu lib1M laggeLaaudnLcds mg Fig5 Click quot0kquot the LSW and layout window opens as in g6 and Fig7 vi i iqu Fig6 draw a nmos select p Well from LSW window select rectangle from layout window and draw a quotp W911 make sure that the width is atleast 2pm as mentioned in the DRC rules sheet Draw n r region and then an active region without violating the DRC rules Follow the same procedure to draw the layout of a pmos While drawing the layout make sure to save the design from time to time Also verify for the correctness of the design by selecting VerifyDRC from the Layout window Use metall to connect the active region to the sources VDD and GND the metall layer and the active region has to be connected through a contact Meta12 can be connected to metall through via Note that meta12 cannot be directly connected to the active region it has to be connected to the metall layer rst and then this metall can be connected to the active region Fig7 Poly has to be used for the gate Creating pins Pins can be created by selecting CreatePin from the layout Window For example to create a supply pin select CreatePin and type the Pin name as Vdd Note that the pin name for the supply voltage has to start With uppercase v V Which is shown in Fig8 Select the 10 type as quotInputoutputquot and the pin has to be the same type as the layer on Which it goes In other words if the pin is to be placed on metall it has to be of type metall Use meaningful names for inputs and outputs select the 10 type as Input or Output depending on the desired pin type mm hum ml ranma names Kiln nk mm x w n V Wch n Mule quotmmxi pm mm nil shun m away an name msqu Flquot Na m 0mm uu ME mum uuluuL I 39mulunlpul swim mquot Hn ly39ln MaliJaln Hn mu 0 5 Access Dnclnl I m I mum I um I mgn I my Mum Fig8 Use labels to name the pins and the design To print the label name select CreatePin and type the label name as Vdd There are a few commands that can mapped to keys C ommand Key Stretch Copy c M ove m Delete del Rotate Undo g 9 After the design is completed it has to be saved by typing Design Save from the layout window The design so saved has to be veri ed by typing Verify9DRC from the layout window The number of errors and warnings if any in the design would be shown in the icfb window Also the errors and warnings would be shown with blinking signs in the layout window The reason for warning or error can be know by selecting Vel ify markers Explain from the layout window and then clicking on the blinking part in the layout The errors have to be corrected before going to the next step The extracted view has to be veri ed by selecting Vel ify Extract A new window with the extracted design will open which will be much similar to the layout window DRC Rules Note These dimensions are the minimum allowed dimensions in micrometers Active Region 08 NPlus PPlus N Well PWell quot Width Metall 06 Meta12 06 Poly 04 Contact 04 Via 04 Spacing Metall 7 Metall 06 Metall 7 Contact 02 Metall 7 Via 02 Metall 7 Poly 02 Meta12 7 Metal2 06 Meta12 7 Contact 02 Meta12 7 Via 02 Meta12 7 Poly 02 Poly 7 Contact 02 Poly 7 Via 02 N Well 7 Nwell 20 PWe117 PWell 20 EEL 5344 Digital CMOS VLSI Design Handout on Hspice RA Karma ungamrarmaan vm 1mulator that vmr SPICE was F I mm mm 1r der usedm 1ndustxy ta venfy nrcmt desrgrrs andta predmt me cxrcuxtbeha sums cf SPICE exist 5 angmally develapedrr 1975 at Umversxty cf Cahfamxa Berke1ey Many ver f which are 175 E 17C versmn LLl ve Berkeley The prrmary reasan why 5 rmrmes me mrcuxt behavmr accurately mum 1071514 range campared ta me rea1 implementation Cansmler the SPICE nethst for an Invener 1 qrrvereer Circuit 2 m0 out in vdd vdd pfet quot41 17 3 m1 out in d f 2 4 can out 0 5 vdd vdd 0 5 s v39 0 ULSE 2 43 2quot 1n 1quot 5n zon 7 oPTIons 2051 ms 8 200 9 mum T v in Vout ME quow avg power from 000ns to 1000115 10 a 11 uonm pfet mos LEVE 12 n at quotms LEVEL 13 EIID Nme A emnmembegjnswme wu nut w GND Frg 1a Input Descriptinn Any splee lnput le wth an Extmsmn m eentatns hut types efstatements a statements desmpnun quhe eempenents and the mtemunnechuns Llnes zea tn the my sp descnpuun z Guntml statements tells SPICE what type ufanalysls tn perfurm un the eneult Llnes 7s a 3 Output statements spee eswhatuutputsatetuhepnntenlunpluttenlLlnes arm 4 statements speci es what munlels neenl tn he usenl set the slmulatlun uf eumpunents eg FETs Llnes llelz The textual aesmpuun m the pneymus page mnuels the lnyene shuwn m Flgure la The rst hne alymys enntatns the descnphun uf the eueult Llne z desenhes the FFET and hne 3 the NFET The geneal fumat ufFET desenpuunls Mname ND NE Nslt NBgt NlndNamew Then tunltx 2M ND NS NS 4 V quot numbers uf the Dram Gate Suurce and Bulk temtnals nespeeuyely By default the nude th length and wldLh quhe gate tn L and W are e m Llne4 nlesenhes aeapaetnn General ful39mat nfaeapaetnms Cname N1 N2 V21leltlC gt eunent m t n M d Llnes 5 and a desmbe yultage suurces General nrmat fut lnnlepennlent yultage and eunent suurces l5 anmge snch Vname Name N1 N2 TypeValue smelt salute name Name N1 N2 TypeValuez T u an h Dr P r TRAN uepenhng un the type uf analysls Value gyes the value ufthe suurce The name uf a yeltage and eunent suurce must stan mth v and lnemeeuyely The geneal lh ls Vname N1 N2 PULSE V1 V2 TD Tr Tf PW Period Where V1 initial voltage V2 peak voltage TD initial delay time Tr rise time Tf fall time PW pulsewidth and Period total time period Line 7 speci es various options that we would like to use for simulation The argument quotLISTquot produces an element summary of list of the input data to be printed The argument quotNODEquot causes a node crossreference table to be printed The argument quotPOSTquot enables storing of simulation results for analysis For more detailed explanation look in to the SPICE Manual referred below Line 8 TRAN asks the SPICE to perform a transient analysis from 0ns to 20ns in increments of 200 picoseconds PRINT statement on line 9 causes the voltage waveforms to be printed MEASURE statement on line 10 speci es the circuit properties we would like measure in this case the average power consumption in the time period 0ns to lOns Lines 1112 specify the models we want to use for the FETs in the circuit LEVEL1is the basic model that incorporates only rstorder effects of the MOSFET The last line in the input description is an END line that signals the end of the circuit input Simulating the Circuit in awaves 1 In the AvanWaves window select Design 9 Open 9 Filter 9 Input This will list the input le quotinvspquot in the dialog box Press 0k 2 Select Design 9 Current This will invoke a dialog box entitled quotCurrent Designquot Click on the item D0 ltgt inverter and press OK Now the current design is invsp 3 Select Tools 9 Run HSPICE This will invoke a quotRun Managerquot window Select the design and click on the Run button In the left sub window the status of the design changes from Running to Done at the end of the simulation 4 Select Tools 9 Results Browser In Results Browser window Click on item quotTransient inverter circuitquot in the top dialog box This will give rise to various elds in quotTypesquot and quotCurvesquot dialog boxes 5 In the quotCurvesquot dialog box double click on Vin and Vout This will result in a display of the voltage waveforms on the nodes in and out 6 Familiarize yourself with various options available under the buttons Panels Window Measure and Con guration 7 Select Tools 9 Print Select File and Postscript options in the dialog box Type a le name say invps Click Print This will save the current waveform window as a postscript le Running from the command line If you wish to run HSpice from the command line then type Sun Server hspice inv sp gt inv 115 When the job nishes HSPICE displays gtinfo hspice job concluded real 11 user 01 sys 01 When you are done with the simulation you can check for correct operation of the circuit by looking at the output waveforms that can be plotting in awaves by typing this command at the grad within the invsprun1 directoryif you are checking the inverter circuit Sun Server awaves inv the windows shown in Fig2 and Fig3 pop up I 1 z 3 I CurrentX Axis TIME Apply I Default Fllter 39 Apply Default l Close I Help 1 Fig2 Fig3 You can now plot the required signal on the awaves window You can analyze the results by viewing the quotinvlis and quotinvst0 les in your favorite text editor When you spice the input le the following new les will be in your directory invlis invic invst0 and invmt0 Familiarize yourself with the contents of these les Simulating Cadence Virtuoso Layout in Hspice Openthe Extractedview and se1 ct Tools Other Then select simula on Ini alize the following window Fig4 pops up select the run dilectoxy as sayinvsp1un1 Fig 4 Click quotOKquot another window shown in Fig5 pops up select the simulator name as quothspicequot and click quotOKquot Fig5 Now select Simulation Options a window shown in the Fig6 pops up select quotRenedist Enn39re Designquot and click quotOKquot Fig6 Select Simulation 9 NetlistSimulate which will lead to the popup window shown below in Fig7 uncheck the simulate option and click quotOKquot Natl Fig 8 In Sunblast we will get an alternative screen which will be explained during the demo Now go to the grad terminal change the director to the quotinvsprun1quot directory The directory has a file named quotnetlistquot that contains the following lines 1 net 0 gnd 2 net 1 Vdd 3 net 2 1P 4 net 3 OP 5 net 4 gnd 6 model mode11 pmos 1eve12 vtoO7 gamma04 kp15e05 1ambda003 tox6eO7 pmos0 0 8 m0 3 2 1 mode11 w14u 104u l 9 model mode12 nmos 1eve12 vtoO7 gamma02 kp3e05 1ambda002 tox6eO7 1O nmos1 1 11 m1 3 2 4 O mode12 w14u 104u Change the name of the netlist le as inVsp Edit this le by adding the desired statements 1 net 0 gndl 2 net 1 Vddl 3 net 2 1P 4 net 3 OP 5 net 4 gnd 6 V2 2 4 dc 0 giving input to the circuit 7 model mode11 pmos 1eve12 vtoO7 gamma04 kp15e05 1ambda003 tox6eO7 8 pmos0 0 9 m0 3 2 1 1 mode11 w14u 104u 10 model mode12 nmos 1eve12 vtoO7 gamma02 kp3e05 1ambda002 tox6eO7 nmos1 1 m1 3 2 4 O mode12 w14u 104u 13 measure risetime falltime and propagation delay make sure there is PWL input 14 measure tran tr trig VO val01 rise2 targ VO val09 rise2 15 measure tran tf trig VO val09 fall2 targ VO val01 fall2 16 measure tran prdelay trig VA1 val05 rise2 targ VO val05 fall2 17 options post list 18 tran 01ns 400ns 19 end H H m H note The lines in bold are the newly added ones The edited le might be simulated by following the procedure given on pages 3 and 4
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