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by: Dr. Garrison Mohr


Dr. Garrison Mohr
GPA 3.87

Mark Smotherman

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Mark Smotherman
Class Notes
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This 7 page Class Notes was uploaded by Dr. Garrison Mohr on Saturday September 26, 2015. The Class Notes belongs to CP SC 330 at Clemson University taught by Mark Smotherman in Fall. Since its upload, it has received 41 views. For similar materials see /class/214264/cp-sc-330-clemson-university in ComputerScienence at Clemson University.

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Date Created: 09/26/15
Register general purpose register small amount of readily available memory that can be accessed more quickly than cache or main memory s a subsystem that transfers data between components of a computer MAR memory address register MDR memory data register Memory bus address data and control lines Connected to one end of the MAR and MDR in CPU on other end of the main memory internal CPU bus this type of bus uses data lines only provides interconnection among registers and fn units tristate buffer a single input single output logic device with three output states the third of which acts to electrically disconnect the output from a shared communication connection eg shared bus PU central processing unit Data path flow of data through the CPU registers and buffers control signal an enabling signal or pulse sent to gates that control the sending or receiving of data at registers and the selection of operations at function units in a datapath hardwired control processors hardware instructions signals are generated directly by the bits As opposed to a microprogram that takes care of the control microprogrammed control implementing the control of a CPU using a stored program approach in which the control signals are stored typically in an encoded form as sets of microinstructions in a control store This method allows new programs to simply be downloaded to the processor or control store when new or different functionality is needed As opposed to a hardwired These microprograms must be very carefully designed as EVERYTHING depends on their speed control store very fast memory dedicated to holding the microcode of the control pipelining allow multiple steps to be executed in tandem parallel Five different components to the pipeline Reduces the amount of computation per cyle Overlapping instructions allows all parts of processor to be working at once throughput is increased by having instructions completed more frequently pipeline stages IF ID EX MEM WB Instruction fetch instruction decode execute memory read write result write back structural hazard A structural hazard occurs when two separate instructions attempt to access a particular hardware module at the same me data dependencies instruction s are dependant on other instructions because they change the data RAW read after write ordering must be preserved true dependency WAR write after read ordering must be preserved anti dependenc WAW write after write ordering must be preserved output dependency load use data hazard a data hazard in which the data being loaded has not yet become available when it is needed by another instruction pipeline stall pipeline stall occurs when a hazard is about to happen the pipeline delays execution etc of the next step to wait for the data to be available register scoreboard a set of in use bits one per register that implements stalling dependant instructions Forwarding when a result from one instruction is to be used as the input to the ALU in the next instruction we can use forwarding to move data directly from the ALU output to the ALU input of the next cycle before that data has been written to the register In this way we can avoid the need for a stall in these situations but at the expense of adding an additional forwarding unit to control this mechanism control hazard branch hazard occurs when a branch instruction is processed While the branch is executing the program may continue executing sequentially in the wrong order Because it did not know were branching branch target address BTA branch taken branch not taken untaken delayed branch branch delay slot the instruction that follows a delayed branch in the source code which will be executed regardless of the direction taken by the branch branch prediction misprediction misprediction recovery flushing pipeline stages dynamic branch prediction branch target address cache BTAC a cache of previously visited branch target addresses which can be used by the IF pipeline stage to redirect instruction fetching when a branch is predicted taken branch history table BHT branch target buffer BTB branch history shift register BHSR a record of untaken taken actions of the most recent branches in which each action is stored as a single bit Ountaken ltaken and which as a bit string can be used as an index into a pattern history table during branch prediction gshare branch prediction algorithm random access memory RAM memory cell array row decoder row address strobe RAS row buffer c lumn decoder column address strobe CAS pagemode DRAM read only memory mmm programmable ROM PRmm erasable PROM EPRmm memory hierarchy locality spatial locality t o a locality working set instruction cache data cache multilevel cache primary cache level one L1 secondary cache level two L2 cache hit hit rate hit time cache miss miss rate miss penalty refill burst transfer over memory bus for refill fetch policy demand fetch or prefetch placement policy fully associative set associative direct mapped replacement policy LRU pseudo LRU random etc write hit policy write through or write back write miss policy write allocate or write no allocate cache lines often called cache blocks tag valid bit dirty bit also known as modified bit and changed bit direct mapped cache set associative cache fully associative cache compulsory miss capacity miss conflict miss Study Guide CPSC 330 Computer Organization Test 1 General Technical Terms kilo 3 mega 6 giga 9 terra l2 peta l5 exa l8 milli 3 micro 6 nano 9 pico l2 bit binary digit either 0 or l byte 8 bits word a fixed sized group of bits that are handled together by the system Desktop Computer 7 pretty obvious Server a computer that provides computation file storage andor printing to multiple users across a network Embedded computer a computer used inside another device running one or more predetermined applications Supercomputer a computer with highest cost and performance instruction set architecture ISA an abstract interface between the hardware and the lowest level software that encompasses all the information necessary to write a machine language program that will run correctly including instructions registers l o etcm memory the storage area in which programs are kept when they are running and that contains the data needed by the running programs RAM Random Access Memory takes basically the same amount of time to access any part of the memory Static is more expensive faster and less dense than dynamic cache memory a small fast memory that acts as a buffer for a slower larger memory primary memory main memory memory used to hold programs while they are running typically DRAM secondary memory nonvolatile memory used to store programs and data between runs typically consists of magnetic disks magnetic disk hard disk secondary memory composed of rotating platters of disks with magnetic recording material Transistor an onoff switch controlled by an electric signal Wafer a slice of silicon used to create chips Die a rectangular piece of silicon containing manufactured integrated circuits up to millions of transistors integrated circuit chip a device combining dozens to millions of transistors Performance Terms Workload the programs currently being run and associated inputs Throughput measure of work done per unit time Speedup the ratio of the execution times of two computer systems Hertz unit of measure for clock frequency Equivalent to cycles per second Latency measure of time from user depressing return or clicking mouse until first output appears Study Guide CPSC 330 Computer Organization Test 1 execution time response time the total time required for a computer to complete a task CPU execution time CPU time the actual time the CPU spends computing for a specific task user CPU time the cpu time spent in a a program itself system CPU time the time spent by the system performing tasks on behalf of the program clock frequency Hertz measure of how many cycles per second clock cycle tick the time for one clock period Usually of the processor clock which runs at a constant rate clock cycles per instruction CPI average number of clock cycles per instruction for a program or fragment of a program Whetstone measured performance by floating point arithmetic operations Dhrystone measured performance by integer and string operation efficiency SPEC benchmarks a set of benchmarks that use real programs to test performance Logic Terms combinational logic logic system whose blocks do not contain memory and therefore compute the same output given the same input sequential logic group of logic elements that contain memory and hence Whose value depends on the input as well as the current contents of the memory minterm product term a set of logic inputs joined by an AND The product terms form the first stage of a PLA Eg AB sum of products form disjunction of minterms joined by an OR Eg AB BA DeMorgan s theorems P Q P Q P Q NP NQ Karnaugh maps typically done by hand relies on visual skills logic representation Use with gates and Boolean expressions don t care simply don t care What the value of an output is gate a device that implements a basic logic function Glitch undesired signal lasting only a short time race hazard race condition output depends on small differences in signal timing number of gate levels circuit depth number of gates on the longest path in a gate diagram fanin number of inputs a logic gate can accept fanout number of inputs that can be driven by a logic gate output propagation delay programmable logic array PLA a structured logic element composed of a set of inputs and corresponding input complements Two stages l Generate product terms then 2 Generate sum of the product terms Can directly implement a truth table decoder a logic block that has a n bit input and 2An outputs Where only one output is asserted for each input combination Study Guide CPSC 330 Computer Organization Test 1 multiplexer mux basically a selector output is one of the inputs selected by the control Three parts a decoder that generates n signals an array of n AND gates each combining one of the inputs with a signal from the decoder and a single large OR gate that incorporates the outputs of the AND gates Can be thought of as an extension to a decoder halfadder adds two one bit binary numbers A and B It has two outputs S and C the value theoretically carried on to the next addition the final sum is 2C S fulladder adds binary numbers and accounts for values carried in as well as out A one bit full adder adds three one bit numbers often written as A B and Cin ripple carry adder essentially an n bit adder n bit adder built by connecting n full adders with carries propagating from right to left ie connect the carryiout of an adder to the carryiin of the adder in the next leftmost bit position the initial that is rightmost carryiin is zero ALU the arithmetic logic unit is the brawn of the computer the device that performs the arithmetic operations like addition and subtraction or logical operations like AND and OR latch A memory element in which the output is equal to the value of the stored state inside the element and the state is changed whenever the appropriate inputs change and the clock is asserted Basic element of cross coupled inverting gates nands or nors flipflop A memory element for which the output is equal to the value stored state inside the element and for which the internal state is changed only on a clock edge So the difference is that a flip flop is only changed once per clock cycle while a latch immediately reflects a change Memory element that prevents a race condition masterslave This flip flop is used to deal with feedback in circuits Made of two D latches It is called masterislave because the second latch in the series only changes in response to a change in the first master latch susceptible to quotone39s catchingquot where a O l O glitch on an input line causes the same state change as for a normal input of l on that line edgetriggered Also used to deal with feedback in circuits Doesn t have the problem of master slave RS latch Set reset latch When using static gates as building blocks the most fundamental latch is the simple SR latch where S and R stand for set and reset It can be constructed from a pair of cross coupled NOR logic gates The stored bit is present on the output marked Q JK flipflop The JK flip flop augments the behavior of the SR flip flop JSet KReset by interpreting the S R l condition as a quotflipquot or toggle command Specifically the combination J l K O is a Study Guide CPSC 330 Computer Organization Test 1 command to set the flip flop the combination J O K l is a command to reset the flip flop and the combination J K l is a command to toggle the flip flop ie change its output to the logical complement of its current value Setting J K 0 does NOT result in a D flip flop but rather will hold the current state D flipflop A flip flop with one data input that stores the value of that input signal in the internal memory when the clock edge occurs Two inputs clock and input D and two outputs Q and NQ The value of the internal state When C is asserted the latch is open and the value of the output Q becomes D setup time minimum time that input to an edge triggered flip flop must be valid prior to the edge hold time minimum time that input to an edge triggered flip flop must be valid after the edge register holds data shift register Type of sequential logic circuit mainly for storage of digital data They are a group of flip flops connected in a chain so that the output from one flip flop becomes the input of the next flip flop Most of the registers possess no characteristic internal sequence of states All the flip flops are driven by a common clock and all are set or reset simultaneously binary counter ripple through counter constructed from J K flip flops by taking the output of one cell to the clock input of the next The J and K inputs of each flip flop are set to l to produce a toggle at each cycle of the clock input For each two toggles of the first cell a toggle is produced in the second cell and so on down to the fourth cell This produces a binary number equal to the number of cycles of the input clock signal modulo 2n counter saturating up and down counter A counter that can change state in either direction under the control of an updown selector input is known as an updown counter When the selector is in the up state the counter increments its value When the selector is in the down state the counter decrements the count lt s saturating because it doesn t wrap around once it reaches the max up or down it can go So essentially it is bounded ring counter type of counter composed of a circular shift register The output of the last shift register is fed to the input of the first register


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