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by: Eloy Ferry


Eloy Ferry
GPA 3.84

Lin Zhu

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Lin Zhu
Class Notes
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This 59 page Class Notes was uploaded by Eloy Ferry on Saturday September 26, 2015. The Class Notes belongs to E C E 201L at Clemson University taught by Lin Zhu in Fall. Since its upload, it has received 43 views. For similar materials see /class/214309/e-c-e-201l-clemson-university in ELECTRICAL AND COMPUTER ENGINEERING at Clemson University.

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Date Created: 09/26/15
LABORATORY MANUAL ECE 201 Logic and Computing Devices Clemson University Department of Electrical and Computer Engineering Clemson SC 29634 Compiled January 2009 Table of Contents 1 Lab Introduction 1 Read lab introduction before coming to your first ECE 201 lab 11 Lab Kit Lab Kit Handout 10 Chip Pinouts 74007447 12 Chip Pinouts 74737495 13 Chip Pinouts 7415174193 14 Data Sheet Resources 15 III Labs Lab 1 Logic Gates A Smart Lighting System 16 Lab 2 EncodingDecoding Seven Segment LED Display 20 Lab 3 Combinational Circuits Parity Generation and Detection 27 Lab 4 Binary Arithmetic Adders 31 Lab 5 MSI Circuits Adders 35 Lab 6 Multiplexers and Serial Communications 40 Lab 7 Multipliers 46 Lab 8 Memory Cache 50 Lab 9 Sequential Design 55 ECE 201 Lab Introduction PURPOSE To familiarize students with the basis of safety lab procedures and the equipment to be used throughout the course EQUIPMENT ECE 201 Lab Kit REQUIREMENTS Each student should read and understand this introduction prior to the first lab meeting SAFETY Whenever electricity is used in an experiment some danger exits This should always be on your mind Most of the experiments in this course will use only low voltages which are not inherently dangerous However it is possible to incorrectly wire almost any experiment such that dangerous voltage levels result Subsequent lab courses require the use of high voltages There is only one way to prevent accidents THINK Plan what you are going to do Understand what you are being asked to do Ask questions Never turn the power on until you are con dent that everything is safe The careless use of electricity can have two results It can hurt you It can hurt equipment Obviously you want to avoid hurting anything To project yourself always treat electricity with respect Don39t handle quothotquot lead wires Don39t leave wire dangling about in space An old rule of thumb is to keep one hand in your pocket at all times This hopefully prevents the ow of electricity from one hand to another potentially causing the heart to stop Keeping one hand in your pocket also causes cramps and decreases efficiency so no one does it But keep in mind that when you touch a wire that is electrified the electricity will always want to ow and it is to your advantage to keep it from owing through you Don t hold electrified wire and make sure that no part of your body inadvertently comes into contact with a wire To protect equipment make sure that all of the hookups between power supplies oscilloscopes voltohm meters light emitting diodes LED s protoboards chips etc are as you want them to be Double check all wiring prior to turning on the power One way to destroy an Integrated Circuit LC is to reverse power leads You can tell because the abused IC will start smoking or will get so hot you cannot touch it Then throw away the LC When probing a circuit with a test lead make absolutely certain that you are making contact with the exact points you wish to test and ONLY those points When using a particular piece of test equipment understand the limitations of the equipment Don t try to use it to test something it wasn39t designed to test Read the manual In summary the way to keep yourself and the equipment from being damaged is to do everything slowly cautiously and carefully GOOD LAB PROCEDURES In order to make your experiments go easier there are some procedures which should be followed Most are generally common sense Before wiring a circuit a circuit diagram should be drawn and simulated This diagram should include pin numbers as shown below You can then check off each connection as it is wired For example after the top AND gate is connected to the OR gate on the right the line connecting them in the diagram should be checked off as having been wired Without some system like this it is very easy to forget which gate is which within a system If you don39t have a properly labeled circuit diagram prior to the beginning of lab your instructor will give you a zero for lab performance While wiring rewiring etc turn off the power This prevents the application of power to the circuit in unwanted places Violation of this rule will result in decreased lab performance grades The voltages used in this lab are generally on detrimental to the chips not students But it is very important to learn proper safety techniques before you enter the highervoltage experiments of other classes Try to avoid messy quotrat s nest wiring It is almost impossible to troubleshoot a messy wiring job It is also hard to make changes to a disorganized board Keep lead wires as short as possible and make neat at bends It is also smart not to wire across the top of the IC s Wire the power leads of chips first using a color scheme ifpossible Traditionally in DC applications RED 5 Volts and BLACK Ground Notice that this is different from AC applications where black is hot white is neutral anal green is ground You can expand on this e g use yellow wires for inputs and green for outputs This makes troubleshooting much easier Wire circuits carefully It is easier to wire it right than to spend hours tracking down an error Make certain fragile leads are not bent excessively They will break off after being bent back and forth several times Observe polarity markings on equipment and components Handle equipment carefully Don 39t drop anything Put all components back where they are supposed to be Before leaving the lab check that your bench position is neat and orderly and check the oor for wires Report any defective equipment to the instructor Turn off all equipment and make sure the bench power is off EQUIPMENT The proper care of the equipment used in this lab is essential If handled improperly many of the devices used to perform the experiments will give erroneous readings or fail to operate altogether Protoboard Your kit includes a plastic board used to wire together electric circuits This is called a breadboard or a protoboard since it is used to prototype circuits Figure 1 below shows how the terminals are connected internally inside the board The horizontal connections X and Y are called buses and are usually for power and ground 39 Each of these contacts are tied together All pins on each of these rows are connected together so one can use quot39 fora 5Volt bus and quot39 for OVolt Ground bus Note Some board buses are divided at the center of the board If the board is not marked as this one is then it should be checked Figure 1 Protoboard Connections Usually the top row is connected to the 5V power supply and is called the power bus The bottom row is connected to an external ground and is called the ground bus Figure 2 shows how the power and ground pins of C1 and C2 can be connected together by the red wires and black wires It also shows how the output of pin 3 on C1 can be connected to the input pin 1 of C2 with agreen wire Figure 2 Connecting Wires Special care is needed when using the protoboard If a wire which is too large is forced into one of the holes that particular contact point most probably will be damaged As a result the next time the protoboard is used and a wire is inserted into that hole the wire may not make contact with the internal connection strip and the circuit will not operate properly An even more aggravating situation is when the wire makes contact only part of the time This is called an intermittent fault Since the circuit will opemte correctly part of the time and then mysteriously fail this type of fault is very hard to nd A good rule to follow is if the wire doesn39t go in easily nd another wire Pay particular attention to components such as resistors capacitors etc since many have lead with diameters which allow insertion into the protoboard but still cause damage to the contacts T 0 avoid damage do not insert wires too far You will have to strip the wire leads before using them to interconnect circuits on your protoboards The proper way to do this is to use a pair of wire cutters to carefully strip 4 inch of insulation off of each end of the wire taking care not to nick the copper wire If you take more than a quarter inch off you risk having wire exposed above the protoboard which will cause a short if it touches another lead or lC pin If you cut less that a quarter off the wire may not make a good connection vvithinthe protoboard hole It also helps to cut the ends of the wire at an angle which produces a point on the end of the wire The wire will then slide into the protoboard easier Digi Trainer You will be using the DigiTrainer during this lab Each DigiTrainer has a protoboard in the middle It is recommended that you place your protoboard on top of the one that is connected to the Trainer This way you can use all of the functions provided by the Trainer and still be able to pick up your protoboard when the lab is nished with all connections intact Also you should prewire the circuit called for by each lab in order to save valuable lab time Figure 3 DigiTrainer Some of the features of the Digi Trainer are 0 OnOff Switch Turns the power to the Digi Trainer on and off 0 Power 5V and Ground provide 5 V and ground to the tie points associated with them Therefore if you connect a wire to one of the 5V tie points and also to the top row of holes on the protoboard all of the top row will be energized to 5V o Lamp Monitors LED39s with appropriate resistors that can be used to indicate ground light off or 5V light on You can insert small wires into the tie points of the LED39s and then insert the other end into a speci c point on the protoboard 0 Clock Device which causes the tie points connected to it to alternate between 5V and ground at a rate determined by the position of the rotary switch 0 Logic Switches Switches used to provide either 5 V or GRD to the associated tie points You could move a wire between 5 V and GRD to provide the same function but it is much easier to use the switches when a lot of changes are going to be required 0 Banana Plugs if present Jacks used to convert between banana jack leads and tie points and then to the protoboard 0 PULSER if present Switch used to provide a single pulse to a tie point This pulse can be described as a 5 V to ground to 5 V sequence or viceversa on a wire You could do the same thing by moving a switch described above from one position to the other and then back However the switch is a mechanical device and does not make each transition smoothly The switch actually quotbouncesquot on its contacts causing a series of pulses The pulsers perform the same function electrically and are therefore called quotdebouncedquot If Pulsers are not present then switches can be toggled back and forth to produce the same effect The Digi Trainer is a powerful and expensive design aid Do not abuse it Any questions you may have should be directed to the instructor Integrated Circuits IC39s The IC39s supplied with the kit are used in a variety of experiments Each looks similar to the one shown below 4quot 1n CID A I lli 1 III u LI I 39 l I I z zi i 7 Figure 4 IC Pin Numbering 39 39 39 39 1Pin 1 is designated by adot or anotch Usually on in logic the type of chips supplied with the kit the last pin 39 L A L V supply A L 39 quot quot pp it i connected to ground These are pins 14 and 7 respectively for 14pin IC s and 16 and 8 S for 16pin 1c The are Same exceptzmls 0 Mt we so always chmcl Speczal When tit Hymns T machine insertion a quot 39 39 39 on39 39 r 39 Thiscanbe done easily by attening the legs on atable top as shown below Ask you instructor to w you how this is done ifyou need elp IEHEEElEl From factory Bend one side then the other till legs are parallel Figure 5 Straightening IC Legs When you remove a chip 1c from the protoboard it is very easy to bend the legs by not Vn39 n 39Lpull L quotp quot 39 One end Will invariably rise before the other causing the legs on the other end to bend It may even result in a puncture wound to one of your fingers because the legs of the IC s are very sharp Be careful If an IC extractor is not available you should use the tip of a pen or pencil to gently pry up the legs on end of the chip and then the other as shown below Figure 7 Removing an IC Again ask your instructor to show you if you need some help Usually if a leg is bent twice it will break off easily and the IC is virtually useless so LAB REPORTS Each report should as a minimum include 0 Objectives 0 Circuit diagram Simulation 0 Explanation of circuit operation 0 Results 0 Conclusions and suggestions Failure to include these lab sections will result in a reduced report grade WORKING WITH THE SIMULATOR See the Digital Works Getting Started guide for an introduction to the simulator software before your first lab CONCLUSION The labs you are going to perform are fun Take your time Ask lots of questions so that you can learn as much as possible You ve paid for it Understand everything that an experiment can show you Try variations of circuits The amount of information you learn from these labs is directly proportional to the amount of thought and effort you put into them If you have any suggestions on how you could make this lab more informative or interesting please see the professor in charge Bill Reid and Dan Stanzione ECE 201 Lab Kit Notes 1 To interconnect your Integrated Circuits lC s properly the pin numbers must be known Each chip has an orientation notch which defines where pin 1 is located When the notch is on the left pin one is on the bottom left The pins are numbered counterclockwise from 1 l u A u A I I I n I I A I I n l r u mi in I I l I I l I I I I a I I I I n u n v III39ll I I I l I i I n n I I 1 n a a v w I u u I I I I r 7 SN74LS76AN 7 6969880901 393 islixe39m Sll7HLSll7N Each chip has a part number stamped on it which gives the chip s manufacturer function and performance As shown above the chip DV74LS374N is a 74374 logic chip which is an octal Dtype tristate flip flop The L8 means it is a Lowpower Schottky The Breadboard contains a grid of holes in which wires can be inserted to make an electrical connection with the pins legs of the IC The diagram below shows how contacts are connected internally it 17 u 39 039 i ii llllil lilll IiiIiullguiginningnu ii lii iiiii mlil IIHIIIIDHIIlllliillinililllimjill wliiilllq mwlll IllllllliilllliilIgIglmgllllll llilIHIIIIIIIIIIin llIglguiiiii mijgllgmgl quotilllilill lliiml7 i uniiibiiigml guggllnggl m I I I I quotI I I H I I I ll I I i i i I g 39i ii I i I U I 39I I I I l I i I ll ii i i i i m I I I4 I II I I i I I I I Ii iI I I I I1 II I I I I I I i i I CI I I I I I I I I ll El I I ll it i In I I a u l I I i I I I I I I I I I i I I I I I I D i I I I ll It I I I I I I I I I I I I1 I U I I D I I I I I U A I39 I I I I I l l I I I I I ill I I i I i I It i I I I E It I I I I I if I I i I i I Ii It I II I ll I I I I n W I I I ii I Ii i ii i l I I I It I I I I I ill 1 I I I l Iquot it I I I it i I I E I I U I I i I I I i I E n 2 2 a V 3 iii 1 e a 33 quot quotiii iiiii Ill Hiring lilil li llliilitlv militia iigg gglljs39u I i I ii i I I it I I in ii in I3 I ll Q g 3 Q i 1 j l m i Q g I u g g a i i i 3 a i I E I g E g Q r a if 4 Chips should be placed across the center groove of the breadboard as shown below I ill I I I I39 I ll I I I I I It i K it Compiled by DrW J Reid Spring 2002 10 ECE 201 Lab Kit Notes 2 Resistors and Capacitor Codes Multiplier Tolerance o o 0 Black 10 1 1 1 Brown 101 Brown i 1 2 2 2 Red 102 3 3 3 Orange 103 4 4 4 Yellow 10 5 5 5 Green 105 6 6 6 Blue 106 7 7 7 9 9 9 Capacitors come in many shapes sizes and types Some large electrolytic capacitors have the explicit value printed on them Some capacitors use the following code shown below where M is a multiplier and T is the tolerance The table below shows the values forthe given code numbers and letters III S 10 pF Letter gt 10 pF 0 i01 B 1 10 i025 C 2 100 i05 D 3 1000 i10 F i1 151Kz15391oz150pF 4 10000 i20 G i2 5 100000 H i3 759 7501 75pF J i5 8 001 K 110 9 01 M 20 Sometimes the letter R may be used to signify a decimal point or 2R2 22 pF or uF Compiled by DrW J Reid Spring 2002 ECE 201 Lab Kit Chip PinOuts 74007447 7400 Quad 2Input 7402 Quad 2Input 7404 Hex NAND Gate NOR Gate u Inverter YAB39 Y AB39 yA Input Output Input Output mm A B Y A B Y t h E t h t H L H H L L H H L H H L 7408 Quad 2Input 7409 Quad 2Input 7410 Triple 3Input AND Gate AND Gate Open Collector NAND Gate V B4 M Y4 BS A3 Y3 Um iIEIAIi M I39Itli IEEIEII M3 39II E39 VD C1 Y1 CS BS A3 Y3 r14 I1 I12 I11 I10 Is In Iiimi IIii Iiil I M 1III Itll III Inquot I1 I12 I11 I10 In ll 1 2 3 4 5 o i III IIII i ir III 1 2 a 4 5 5 A1 B1 Y1 A2 52 Y2 GND Mi IEiI I 39Iquot A Elli I ii Gail A1 B1 A2 BZ C2 Y2 GND YAB YAB YABC39 In ut Output In ut Output Input Output A B Y A B Y A B c Y L L L L L L X X L H L H L L H L X L X H H L L H L L L X X H H H H H H H H H H L 7420 Dual 4Input 7432 Quad 7447 BinarytoBCD NAND Gate 2Input 0R Gate Converter V E2 C2 NC 32 A2 Y2 MM EM AM 39it39lit IEIIIEI LIIIJEI I39tii V f g a b c d 9 I914 13 12 I11 I10 In ll imr Iiiai Itliili Iiiii quotIIII IEII III 15 15 14 1a 12 11 1o 9 om f 0 I b l tirade 1 2 3 4 5 6 1 B1 NC C1 D1 Y1 GND an BCLTRBRBDA i iquot 1I III lilli I ll Ilii iii iIII I IEII39I quotIquotquot M IEIIE 39Ii39ii iliiiltilitii B c me R5 R5 D A GND I Ten on In Y ABCD Y MB In ut Output In ut Output A B c D Y A B Y EIIIIEIHIEII X X X L H L L L X X L X H L H H X L X X H H L H quotm m L X X X H H H H sz H H H H L INSTRUMENTS Compiled by Dr W J Reid Spring 2002 ECE 201 Lab Kit Chip PinOuts 74737495 7473 Dual 7476 Dual 7486 Quad 2 lnput JK FlipFlop JK FlipFlop 1 J1 Q139 Q1 GND K2 02 02 14 1a 12 11 1o 9 X0 lii mll All il ill I 1 39Il39lli 5 I ll 1 2 5 a 5 6 1 I1 I2 I3 I4 I5 I I7 I39 39 Ill r Iii 39 Ck1 CH K1 VW CIQ CfZ J2 Ck1 PR1 CH J1 Va CIQ PR2 Cf2 Illl39l I511 W1 All llilil ll39 l IIEiNlIIII Inpu 5 Out uts Inputs Out uts Cir Clk J K Q I PR Cir Clk J K 039 Y AGBBA BAB L X X X L H L H X X X H L H l L L QU Qn H L X X X L H 39n t OUtPut H l H L H L L L X X X H H A B Y H l L H L H H H l L L OD QB L L L H l H H To gle H H l H L H L L H H H H X X 0B Qu H H l L H L H H L H H H l H H Toggle H H L 7490 Decade and Binary 7495 4Bit Shift Register Counter vac o a on 1933 A NC GA on GND QB 00 I14 l1 I1 I11 I10 la la 14 12 11 1o 9 a L L I1I23I4I5I6I 1 z a 4 5 a 59339 B B RIX1RX2 NC VCC Rq1R92 Inputs Outputs R01 R02 IK Q Q L L L L H 2 u N Il l g 111 Count Count Count Mode Count Change No Change No Change Undetermined Undetermined I gtltgtltIgtltII 5U vgtltvgtltIgtlt1 11 gtlt1 gtlt1 Iu gtlt L H H L L H HHHH 1111 1 1 gtltgtltgtltgtltgtltgtlt gtltgtltgtltgtltgtltgtlt Undetermined 39 Oututs 4Blt Inputs When COLIC2L When coHIC2H WIth Fast Carry 2123 2224 I L L H L IEllIi M4 1315 1011 Iiiliil Wm Elli rill IrIrIrIrIrIrIrI IIrrIIrrIIrrIIrr IIIIrrrrIIIIrrrr IIIIIIIIrrrrrrrr rIIIIIIrrIIrrIIr IrrrrIIIrIIIIrr IIIIIrrrIrrrrrrr IrrIIrrIIrrIIrr IIIrrrrIrrrIIII IIIIIIIFIIIrrrrr Compiled by Dr W J Reid Spring 2002 ECE 201 Lab Kit Chip PinOuts 7415174193 741 53 Dual 4to1 74 1 5 1 8to1 Vcc D4 16 mmmYWsmaeGND SelectorMUX DE m D7 A B C Multiplexer n uts Outpus Clear Cloc D Q Q39 L x x L H H T H H L H T L L H H L x on Qu 74155 Decoders Demultiplexers Sto Decoderor 1to8 Demulti lexer Inputs Outputs Selects Strobe 0 1 2 3 4 5 6 7 c a A G van m m x x x H H H H H H H H H L L L L L H H H H H H H L L H L H L H H H H H H L H L L H H L H H H H H L H H L H H H L H H H H H L L L H H H H L H H H H L H L H H H H H L H H H H L L H H H H H H L H H H H L H H H H H H H L 3to 8 Decoder or 1to8 Demultiplexer Inputs Outputs Inputs Outputs B A GA CA YAO YAl YAZ YA3 B A GB CB YBO YBl YBZ YB3 X X H X H H H H X X H X H H H H L L L H L H H H L L L L L H H H L H L H H L H H L H L L H L H H H L L H H H L H H L L L H H L H H H L H H H H L H H L L H H H L X X X L H H H H X X X H H H H H Compiled by Dr W J Reid 74175 Quad 1 2 Clear Q1 a 4 5 e 1e Q139D1l320239QZGND 74193 Dual Sync Counter w separate UPDown Clocks Ellilllll All 1 39 ll lIll iilliai IIIIIEI IIIIIquot Iiii 39 Lllliill I 39II II I Illquot 1 LllJllllli Dli lil Iiivii lzii III 1 1 SevenSegment Displays SA03IIHDB A 1 A 5 F DI B F B 5 g G I E z g g D H D 14 Oamlmn Am 11111 ABCDEFGHI 13108721196 Spring 2002 BSC514RD 764219105 Lab Kit Other resources Fairchild Data Sheets on the Web Texas Instruments Data Sheets on the Web ECE 201 Lab 1 Logic Gates A Smart Lighting System PURPOSE In this experiment you will explore the notion of combinational circuits and basic combinational design EQUIPMENT ECE 201 Lab Kit amp Digi Trainer REQUIREMENTS 0 Circuit diagrams for all three circuits with pin numbers clearly labeled 0 Verbal description of the function of the nal circuit 0 Truth table for the first function the light controller PROCEDURE Section 1 Designing and Building a Digital Light Control Consider the problem of constructing a light controller for a certain room in a house It is desirable for the light to be switched on if 1 A Burglar Alarm detects an intruder 2 A Master Light Switch is on or 3 An Auxiliary Switching system is active and a persons isare present in the room Item 3 requires further consideration First of all how is the system going to know if a person is in the room A motion andor sound detector could be used to produce a logic 1 Boolean True ifa person is detected The auxiliary switches mentioned above could be the wall switches already found in the room Assuming that the room has two doors then a three way switch at each door would be convenient In this configuration the light is off if both switches are up or both are down and it is on if one switch is up and the other is down This allows for the light to be switched no matter what the state of the switches is lEElwi39l39rh A lliwli39l39 quot39 ll irlllcznIju l I I 39 39ir1riltirl Figure 1 Wiring of a ThreeWay Switch For the lights to come on in our design not only must one switch be up and one down but a person must also be detected unless one of the other conditions Burglar Alarm or Master Switch turns them on Note that the person detector would probably have a timer which keeps the output high for a designated time after a person is detected Basically what we need is a circuit which will switch the lights on if and only if The Burglar Alarm is On OR The Master Switch is On OR A person is detected AND one but not both auxiliary switches is up Now let39s assign some variable names to the various switches inputs so that we can write an equation to describe the desired binary function Let B Burglar Alarm M Master Switch P Person Detector A1 Auxiliary Switch 1 and A2 Auxiliary Switch 2 Note that the necessary condition of Al and A2 to activate the lights is an Exclusive OR function one but not both Using the XOR symbol 9 we can write the desired lighting function FL as FLBMP39A1 A2 A circuit for this function can be drawn in the following manner IquotquotquotIlquotquot39 mm Illil IFIL lljquotquotl397ir lli gllquotl39tlill llggl 20r irltzlr cznlljl mi 1 Figure 2 Circuit Diagram for FL Note that the circuit above would not switch the light on directly The Binary signal that is 5 Volts DC from the output would need to go to a device say a relay which could switch on the 120Volt AC power to the lights In lab however we will wire the output directly to a light red LED since these require only 5 Volts DC Note also that the wall switches in lab are only switching 5 Volts in this case not the 120 Volts AC as would be found in the actual home One immediate problem of implementing this lab is there is no 3input OR gate in your lab kit Recall that the OR operation is associative allowing you to make a 3input OR from two 2input OR gates AORBORCABCABCABC m Now connect this circuit and check to see that it works properly Use the two left switches for A1 and A2 the next switch for P and the right most switch for M Use one of the Pulse Switches for B making certain to use the pin that goes high when the button is depressed normally open Then have your instructor verify the count Section 2 Implementing a Function with Different Gates It39s possible to implement this same function using only AND OR and NOT gates by using the definition of the XOR function Using Boolean Algebra FL BMPA1 BA2 B M PA139A2 A1A239 B M PA139A2 A1A239 DDraw a diagram for this circuit showing how to use 2input AND gates to make the 3input AND39s Wiring and checking this circuit is optional Section 3 Realizing an Arbitrary Boolean Function Now that we have looked at a real life example let39s look at an arbitrary function to see how we might realize it Rather than specifying the logic with words as in the previous example we will use a truth table This will be a function of four variables A B C D giving the truth table will have 16 entries ABCD E ABCD E 0000 1 1000 1 0001 0 1001 0 0010 1 1010 1 0011 1 1011 0 0100 0 1100 0 0101 0 1101 0 0110 1 1110 1 0111 0 1111 1 Using your Boolean algebra skills you can write an equation for this expression and simplify it to Minimal Sum Of Products form MSOP which gives you F B D ABC ABC CD DDraw a circuit for this function using only AND OR and NOT gates The function calls for two 3input AND gates and one 4input OR gate All you have available however are 2input AND and OR gates thus you must discover how to make 0 A 3input AND from two 2input AND s and 0 A 4input OR from three 2input OR s Remember that both the AND and OR operations are associative 3 Wire this circuit and have the lab instructor verify its proper function ECE 201 Lab 2 EncodingDecoding The SevenSegment Display PURPOSE To familiarize the student with the sevensegment LED display and the process of converting one type of binary information to another encodingdecoding A good understanding of BCD Binary Coded Decimal should also result EQUIPMENT ECE 201 Lab Kit amp DigiTrainer Simulation Software REQUIREMENTS 0 Circuit diagrams with pin numbers labeled 0 Verbal description of the function of the nal circuits 0 Truth Table for all seven segments and all seven functions in MSOP 0 Simulation of functional sevensegment display circuit PROCEDURE Section 1 About the SevenSegment Display 1m ro er connections to the sevense ment dis lay can destroy it Double check your 39 P P g P 0 connections before applying power The sevensegment LED Light Emitting Diode display is a common device in consumer electronics from calculators to clocks to microwave ovens In this lab you will learn the basic principles of operation of the sevensegment display and the process of converting BCD values to the proper signals to drive this display The display has seven separate barshaped LED39s arranged as shown In addition many sevensegment displays have one or two circular LED used as a decimal point Figure 1 A SevenSegment Display 20 Inside the sevensegment display one end of each LED is connected to a common point This common point is tied either to ground or to the positive supply depending on the speci c deVice If your seven segrnent display is designed to have the common connection tied to the positive supply 5V it is called a common anoale con guration as shown below To light these LED segments the inputs must be a logic low anwwrwmwl w llnn w H sh i113 uyi jg Irriuesiilquot3939 llil39iliigti 1iiii 5 Figure 2 Common Anode SevenSegment Display Circuitry To actually light up a single LED segment a resistor must be added to limit the current through the LED This resistor is critical If you connect the LED between 5 V anal ground without the resistor 0 the LED will momentarily glow bright anal then never glow again For this display use a 2209 resistor as shown below hMm imm m quotElm IFIIII39 II u quotBETH Figure 3 Resistors used with a Common Anode SevenSegment Display If Fa Fb etc are 5 V there is no voltage drop across the LED and resister resulting in no current ow through them and the LED remains dark Ifthe inputs are 0 Volts a current is produced and the diode glows If your lab kits contains a common cathode display the common point is ground instead of 5 V as shown below To light these segments a logic high must be supplied LED Segment Inputs Common GND Figure 4 Common Cathode SevenSegment Display Circuitry These LED circuits can be used in the last lab as a logic indicator to troubleshoot circuits Consider verifying the operation of the XOR gate of Lab 1 using a logic indicator shown below The LED functions as a logic test probe which lights up when the test point is a logic zero and does not light up when the test point is at a logic one quot 39 i nilwt quotit til Mill Hill quotin I lllhl I I iilli Figure 5 LED used as Logic Test Probe NOTE You can use the LED 39s built into the DigiDesigner for trouble shooting as discussed above Consider that they more appropriately turn on with a logic one instead of a logic zero because they have an inverter built into the circuit as shown below 5 VDc MI 220 9 Input Figure 6 DigiDesigner LED Wiring Now consider how the ten decimal numerals can be formed using the sevensegment display The gure below shows these digits 0 through 9 EEHEE HQEEE Figure 7 SevenSegment Display Decimal Representations Section 2 The BCD t0 SevenSegment Converter What we wish to do is input a BCD 4bit binary number to some combinational circuit which causes the appropriate segments of the display to light up For example if a O O O O is input to the circuit all of the LED pins on the sevensegment display should go low to light the segments except the pin connected to the center horizontal LED That is segments a through fSee Figure 1 What we need to do now is determine the appropriate combinational circuit to light each segment That is the each segment is turned on by certain Boolean function For example segment a is lit for 0 2 3 5 6 7 8 and 9 Therefore the circuit must produce a logic zero for these numbers to light segment a That is it must produce a logic one for the numbers 1 and 4 Remember that BCD numbers use only ten of the sixteen possible combinations of four bits 09 Therefore we do not care what comes out of the circuit for the last siX inputs 1 O l 0 through 1 l l 1 since these inputs should never occur The resulting symbol for these inputs should be whatever it takes to produce the least complicated circuit For the function of segment a we have the following truth table DCBA g3 DCBA EE 0000 0 1000 0 0001 1 1001 0 0010 0 1010 x 0011 0 1011 x 0100 1 1100 x 0101 0 1101 x 0110 0 1110 x 0111 0 1111 x The X s in the truth table above indicate the quotdon t carequot conditions that is rows in the table where we do not care what the output of the function is Using Boolean algebra we can write the minimum sumofproducts MSOP expression for FA as Fa D39C39B39A CB39A39 a What comes out of this circuit for each of the six invalid inputs For example what would FA be ifthe input were 1 01 0 Now make up a truth table for all seven segments and find a function MSOP for each 39 You need not make a separate truth table for each segment just list the inputs once anal have seven output columns as shown below w EAEEEEEREEEEEE 0000 000 0 1111 xxxxxxx We need not build all of these individual circuits with separate IC s however in order to use the sevensegment display Because this function is so common to electronics a single chip has been standardized to perform this conversion This chip which you have in your lab kit is the 7447 and is called a BCDtosevensegment display A block diagram for this chip is show below 33 5 YDC D Cl C b B 7447 3 A e f 9 Figure 8 7447 BCD to SevenSegment Display The 7447 has common collector outputs which can sink much more current than they can source supply Therefore the 7447 is designed for a common anode type display which needs a logic low to turn on the segments If you have a common cathode display then you must use an inverter on each input The inverter should be able to supply enough current to light a segment Now using the 4 switches of the Digi Designer as the BCD input connect the following circuit and verify that it functions properly Be sure to include a description of the circuit operation in your report iii quotuquot vr Figure 8 Using the 7447 BCD to SevenSegment Display ND Remember to be very careful wiring this circuit making sure that no resistor leads are shorted anywhere and that the power to the sevensegment display is connected to the correct pin Do Not connect any pin of the common anode sevensegment display directly to ground This will short out the segment forever Likewise do not connect any pin of the common cathode display to 5 V or it to will be shorted out forever Check the siX unused input combinations 1010 through 1111 and report which segments light up Does this match what you would expect from the seven equations you got for the decoder If not can you think of one reason why the output might not match your equations ECE 201 Lab 3 Combinational Circuits Parity Generation and Detection PURPOSE To familiarize the student with combination circuits by studying methods of parity generation and detection EQUIPMENT ECE 201 Lab Kit amp Digi Trainer Simulation Software REQUIREMENTS 0 Kamaugh Map for Parity Generator and Detector 0 Truth Table for Parity Detector 0 Verbal description of the function of the Parity GeneratorDetector 0 Simulation of functional Parity Generator Detector PROCEDURE Section 1 Parity Generator In this part of the lab we will design and build circuits to generate and detect odd parity for threebit words Our parity generator circuit will take three input bits X y and z and produce one output bit P The truth table for this parity generator is shown below x22 3 000 1 001 0 010 0 011 1 100 0 101 1 110 1 111 0 Use the Kamaugh Map to produce an MSOP representation of this function by grouping the 139s of the function P 9 How many 2 input AND and OR gates and how many inverters would be required to implement the equation for P above Remember it takes two 2input gates to make one 3 input gate ANDS ORS NOTS This circuit can be implemented with the chips in your lab kit but it would leave only one OR gate and no AND gates to implement our entire parity detection circuit Not to mention that it would be a pain to wire up Can we simplify this function in order to simplify the hardware This is one of those examples where you see why engineers can t be replaced by computers yet The Kmap guarantees us MSOP form but that s not the simplest form for this problem Neither is the MPOS form we39d get from grouping the zeroes Try it and see Notice that the Kamaugh map shows a checkerboard pattern every other square When this pattern exists the function can be implemented in either an XOR or XNOR operation The equation obtained for P can be simplified using the properties of Boolean algebra as follows P x39y39 xy 239 x39y xy39 2 x y39 z39 x 9y 2 Ifwe let A X B y then we have P A39z39 Az A 432I x CBy CBzI Therefore we can implement P with a threevariable XNOR gate Of course we don t have a three input XNOR gate in our lab kits but we can easily build one from two XOR gates 7486 and single inverter Recall that XOR is associative like AND or OR so that X y z X B y 9 z Use Digital Works to create a macro of your parity generator circuit m Wire up the circuit on your breadboard and test its function Section 2 Parity Detector Next we need to implement a Parity Detector circuit It will have four inputs the three information bits x y and z and the newly created parity bit P It will have one output bit the error E which will be high whenever there is a parity error Fill in the value for E in the truth table for this circuit below Remember E will be 1 whenever P is not the correct odd parity bit for the values of x y and z xsz E xsz E 0000 1000 0001 1001 0010 1010 0011 1011 0100 1100 0101 1101 0110 1110 0111 1111 Now nd an MSOP equation for E using the Karnaugh map below E Once again you ll notice that this equation would be a nuisance to wire up since we cannot form any groups on the map And once again we notice the familiar checkerboard pattern If we look back at our truth table we ll notice that E is true whenever there is an even number of 1 s in the four input variables just as P was 1 whenever there was an even number of 1 s in the input in the table for our generator circuit Once again we can implement this function as an XNOR of the four input variables Ex y z P39 Because of this property XNOR is also known as the even function and XOR is also known as the odd function Ifwe changed our truth table so that our output was true whenever there was an odd number of ls the resulting function would be an XOR and the Kamaugh map would still look like a checkerboard but the rst one would be in square 0 O O 1 instead of O O O 0 Create your parity detection circuit using the equation for E above as a macro in Digital Works with four inputs and 1 output and verify its function To test your simulation embed your generator and detector macros in the same circuit as shown in the gure below Figure 1 Parity Generator and Detector m Wire up your circuit on your breadboard This will require three more XOR gates and one more inverter You should have two 7486 chips in your kit Connect your parity generator to your parity detector and verify that it works correctly How might you change the circuit above to simulate a communication where a single bit ND error may be introduced to one of the four inputs to the parity detector ECE 201 Lab 4 Binary Arithmetic Adders PURPOSE The student should demonstrate knowledge of simple binary arithmetic and the mechanics of its use Each student is required to design simulate build and test a twobit full adder EQUIPMENT ECE 201 Lab Kit amp Digi Trainer Simulation Software REQUIREMENTS 0 Simulation of functional Full Adder 0 Functional Full Adder Circuit PROCEDURE Section 1 Adders Consider the problem of adding two singlebit numbers A and B resulting in a single twobit answer The truth table for this operation is shown below EES 0 0 0 l 0 l 0 0 l 0 0 0 l l l 0 The two output functions are labeled C and S where 8 stands for sum is the low order bit of the output The C stands for carry and is the high order bit of the output The functions for S and C can be written as the two MSOP equations below C AB S A B AB39 A circuit that implements these two functions is known as a half adder This adder is referred to as a half adder because it only solves half the general problem of adding numbers with more than one bit Let s take a look at an example of what happens when we add two 8bit numbers Carry 1 0 1 1 1 0 0 0 A 10111001 B 10101100 Sum 01100101 Note that except for the right most column we are actually adding three bits a bit from each of the 2 numbers and a carry bit from the bits immediately to the right Note also that each addition produces 2 bits the result bit S and the carry bit C Now let39s make a truth table for this addition process The truth table will have three variables one bit from each of the numbers A and B and a carry in bit Ci which represents the carry from the previous position The two outputs are the sum bit and the carry out bit Com which will be used in the next position CinAB 0 0 0 0 0 0 0 l 0 l 0 l 0 0 l 0 l l l 0 l 0 0 0 l l 0 l l 0 l l 0 l 0 l l l l l We39ll use Kamaugh maps to simplify the two functions in the table above into MSOP form S A AB Cout A AB Cirl 00 01 11 10 Cin 00 01 11 10 o D o m cn1 Cm1 TW J Figure 1 Full Adder Karnaugh Maps 03 As shown above the MSOP functions for S and Cout are Sum A B C AB C A39BC ABC Cm AB AC BC We can implement the function for Com in a straightforward manner as shown below Figure 2 Full Adder Carry Circuit The MSOP form S is a bit more complex however If we examine this function a bit more closely though we will see the now familiar checkerboard pattern in the Kmap and notice that S is only equal to 1 when an odd number of the input variables are l in the truth table The function for S can therefore be easily implemented with an EXOR function as shown below SumA BB BC Sum OWgt Figure 3 Full Adder Sum Circuit These two circuits together are called a full adder Section 2 Building a 2bit Full Adder m You are going to build a device which will add two unsigned 2bit numbers Use a pair of switches for each input value The results will be displayed on LEDs You will need to build two copies of the full adder The carry input to the right most adder will be tied to GND The ca1ry in of the left adder will be tied to the ca1ry out of the right adder 9 What happens to the carry out of the left adder In block diagram form the 2bit Full Adder looks like Figure 4 Full Adder Circuit You will need one 7486 two 7408 s and two 7432 s to build the above circuit D In this simulation you will build some simple circuits with gates and then use multiple copies of those circuits to build a larger more complicated device This is typical of how system design is done We use this same kind of procedure with Computer Aided Design CAD tools like your digital simulator Ideally you would like to enter the circuit for a full adder once test and debug it then turn it into a part we can use over and over again Then you could simply use two of those parts and draw the connections between them to build your two bit adder This is called a hierarchichal design In Digital Works hierarchy is achieved by using macros You used a macro in the previous lab for the 7447 driver chip This week you will want to create your own macro for the full adder circuit See the online Digital Works Getting Started guide for details on how Once your macro is created you will create another schematic that uses two copies of the macro and adding the switches and lights Your resulting schematic should look like the block diagram of the circuit shown above HINT It will probably be easier if you use one 7408 and one 7432 for each ca1ry generator rather than using one chip for parts of both full adders This way the two carry circuits can have identical pin assignments and also be physically separate to help avoid confusion This also makes it possible for you to label the pins correctly inside your full adder macro You are to turn in copies of the schematic for you fulladder macro as well as your nal circuit in lab ECE 201 Lab 5 MSI Circuits FourBit AdderSubtractor with Decimal Output PURPOSE To familiarize students with Medium Scale Integration MSI technology specifically adders The student should also become familiar with 1 s complement arithmetic EQUIPMENT ECE 201 Lab Kit amp Digi Trainer Simulation Software RE QUIRE ME NTS 0 Simulation of functional Full Adder 0 Functional Full Adder Circuit PROCEDURE Section 1 Adders In the last experiment we built a pair of adders and used them to add two 2bit numbers In this lab we will use an MSI chip containing four full adders to add and subtract two 4bit signed numbers using one s complement arithmetic All of the chips used thus far have been SSI Small Scale Integration chips which consist of single gates MSI chips combine dozens of gates into a single function on a chipin this case a 4bit full adder the 7483 LSI Large Scale Integration and VLSI Very Large Scale Integration combine hundreds or thousands of gates into very complex deVices on a single chip Microprocessors and related components fit into these categories Remember that by using one s complement arithmetic we can both add and subtract with the same circuitry The problem remains of how to complement a number so that subtraction can be performed Section 2 AdderSubtractor Part I Let us recall the operation of an XOR gate Note that if one input is 0 the output equals the other input On the other hand if one input is 1 then the output equals the complement of the other input X X Figure 1 Using an XOR Gate as an Inverter We can thus use XOR gates to perform a one s complement on command m1 n2 n3 n4 I P if T f 39 Compbmem om1 om2 om3 om4 Figure 2 Using XOR Gates as a One s Complementor In block diagram form the 7483 would appear as shown 39 l39l iil39 i 1 2 II W Hill IIIIIIIHIL quot39ilviir l illfii liuill z ilquotquot lr Al ml39i39 lllmD quotI quotmquot i quot quotquotquotquot linil ilquotquoti lllw M inquot t39Llil 39Inw n H All 555quot 39m w tr e umv UM iiJ lull II quotiiquot WEI Iquot r Lquotquot 39 ill quot39JI AI quotmquot 5 imli II i Figure 3 Block Diagram of 7483 Note that the carries are already interconnected within the chip The rightmost carry in C0 and left most carry out C4 are available for cascading to other 7483 s or other uses The A39s and BS are the inputs addends and the S s are the outputs sum Label the pin numbers on the following circuit construct it and verify that it both adds and subtracts A and B correctly 39 Ch eck pin numbers for power and ground B4A4 Ba A3 32 A2 3A Add w Subtract BACin BACm BACin BACm Full Full Full Full Adder Adder Adder Adder Com 5 Com 3 Cour S Cour 3 s s s s Figure 4 Using the 7483 for Addition and Subtraction Since we have only four switches we use these for the bits of A and will simply plug the B39s into either 5 V or ground to produce B eg For B 3 let B4 GND B3 GND B2 5 V B1 5 V 9 What happens if we add 0011 and 01 l 1 Is the result correct Why or why not 0 Why is C4 connected to C0 Be sure both chips are at one end of the breadboard to facilitate the further expansion of 0 th e circuit Part II It would be handy if we could display our results in a more easily readable form Using another XOR package a sevensegment display a few resistors to limit current so the sevensegment display won t smoke and a BCD to sevensegment decoder an extension of your second Lab this goal may be achieved by means of the following circuit B4SW1 B3 SW2 B2 SW3 B1 SW4 Add Subtract BAG BAG BAG BAG Full Full Full Full Adder Adder Adder Adder Cout S Cout S Cout S Cout S 1 I I i 7 D C 7447 B A BCDioSevenSegmen r Display a b c d e f g DP a b c d e f g SevenSegment Display Figure 5 AdderSubtractor with Display 3 Construct and test the operation of the circuit above x 9 The XOR s above may not be necessary depending on the type of sevensegment display you are using Ifthe sevensegment display is a common anode design then the sum S4 So must be inverted by XOR s because the segments are lit by sending segment inputs a through g low 0 instead of high This might seem strange but it will make perfect sense once you have studied the internal structure of TTL gates Ifyou are using a common cathode type device then these gates are not necessary Figure 6 Common Anode and Common Cathode Displays Remember that the sevensegment display must use resistors to limit the current through the Be careful not to short the resistor leads together This may result in a decrease in resistance and an thus an increase in current through the led segment causing it to quickly burn out and never shine again You need only to disconnect the wires to the lights in the rst circuit The rest can be left intact Questions to turn in with the lab report Do you think the 7447 is classed as SSI MSI or LSI In both circuits why are C0 and C4 connected together Why is the D input of the 7447 always 0 What is the purpose of the 3 XOR s connected to the A B and C inputs of the 7447 Explain fully in your own words Explain how to convert the above circuit to perform two39scomplement arithmetic Draw the circuit and explain its use Hint C0 can be used to form two39scomplement ECE201Lab6 Multiplexers and Serial Communication PURPOSE To familiarize students with the internal realization of multiplexers and to show an application of multiplexers and demultiplexers for use in serial communications EQUIPMENT ECE 201 Lab Kit amp Digi Trainer Simulation Software REQUIREMENTS 0 Circuit diagram with pin numbers labeled 0 Verbal description of the function of the nal circuit 0 Simulation of functional sevensegment display circuit PROCEDURE Section 1 The Realization of a 4bit Multiplexer A 4tol multiplexer functions like a fourposition switch such as the one shown below The switch contact can be moved to any one of the four positions The switch can not be moved anywhere else ie it must be in contact with one of the four inputs at any time The output signal of the rotary switch equals the signal on the input to which the switch rotor has been positioned Input 1 Input 2 e Output Input 3 Input 4 Figure 1 FourPosition Rotary Switch By now you may be wondering what this has to do with multiplexers which are little electronic gizmos having no actual switch contacts no knob to turn or lever to position or anything of the sort It 40 is helpful to think of a multiplexer as a rotary switch whose position is controlled by a binary number input to the device How many control bits would we need to select one of sixteen positions The control inputs will henceforth be called select lines since they are used to select one and only one input to be routed to the output We can redraw our rotary switch as follows lHquotH Hi Hl Hi4 mm 39 39lllll I39m I 0 I y mat m MMHMMm Kmmm Hum 3 m I31 ihml hmIHE W 1 mill I I m m hmwwwm Inn 1 Iv IA EEEILE Figure 2 4to1 Multiplexer The selectors 1 and So determine which position the switch is in Note that the order of 1 and So is important 81 is the most significant bit whereas So is the least significant bit Ifwe want to be slightly more technical we can formulate the Boolean equation for the output function of a four input multiplexer as f slsoI0 slsoI1 slsoI2 slsoI3 Note that when a binary zero 00 is on the select lines the output f is equal to I 0 when a binary three 1 l is on the select lines f equals I3 etc Section 2 Application Serial Communication Some notes before we get started in this section in addition to using multiplexers and demultiplexers we will use a 74193 counter chip You probably have not seen counters yet in your 201 lecture Don39t worry you don39t have to know how counters work in order to complete this lab You just have to know what they do they count in binary Connect the counter as shown at the end of this lab procedure and it will count repeatedly through the numbers 000 to 111 on the Q outputs incrementing once on each clock cycle toggle We ll discuss counter design after introducing sequential logic circuits You39ll also need to make use of your 74151 8to1 multiplexer chip and your 74155 chip Figure 3 74155 Logic Diagram Time multiplexing is often used with LED displays on calculators to reduce the amount of current the battery must supply to light the LED s Rather than lighting all of the segments at once one segment or groups of segments for multiple digits will be lit for a short time perhaps 1 ms Then the next segment or group will be lit for an equal time and so forth until all the segments have been lit Then the cycle repeats making each segment of display ash on and off so quickly that the display appears continuous to the human eye only slightly dimmer The battery is then required to supply a much smaller average current than when all the segments are displayed continuously Since LED s use a lot of current around 10mA all digits 8 this can greatly prolong battery life Time Multiplexing is also often used in communication systems where independent data streams must be sent over a single line or channel The phone company does this on its lines We are going to timemultiplex the seven segments of a 7segment display The 74193 counter will be used again where the three least signi cant bits driving both the Multiplexer and the Demultiplexer The Demultiplexer is essentially a backwards multiplexer one input and 2 outputs which are selected by n select lines We will construct a 1to8 demultiplexer from the 74155 Dual 1to4 demultiplexer The 74155 has two 1to4 demultiplexers one of which has an inverting input just to make life more dif cult A functional diagram of the 74155 is shown below 2221131 iiiquot 11 1 111111 11 quotI quotIquot rquot1239l ii I 1 w v 1 I39Ir 1 1221 llquot 2125111 1 It Ill 1111I 1 1 C III quot 11111111ilit III tIIZIhlZEk r u 11139 11 quotE MI 1 It 1 13 an v I t Inn W 1551 11 quot quotJ 31 11 11 quot39 quot film 1 I AIL I I J T 1553iH 1553 Figure 4 74155 Functional Diagram To use as a 1to8 demultiplexer connect as shown below G Inputs 1G and ZG connected together G 1Y0 1Y1 C Inputs 1C and 20 connected together 1Y2 74155 M 2Y0 2Y1 2Y2 c B A 2Y3 82 S1 SO Figure 5 74155 Used as 1to8 Demultiplexer Now connect the following circuit a D0 W G 1Y0 VAVAVA a c D2 74151 Serial 74155 1Y2 V v v c Seven d E 8to1 09mm 1to8 1Y3 Viviquot d Se lment e MUX Line DEMUX 2Y0 vvv 9 Display f vnv v f g D6 STRB 2Y2 VAVAV g D7CBA CBA2Y3 Qc QB GA 74193 UP DOWN COUNT COUNT LOAD CLEAR 39 J CLOCK 5 V Use DigiTrainer Clock Signal Figure 6 Parallel to Serial Communication l o WARNING Do not wire any pin of the sevensegment display to ground You can destroy it Also be sure that the bare leads of the resistors do not touch before turning on power To operate wire the inputs to the 74151 as appropriate to light the proper segments for the number 5 Set the clock on 1 Hz and check that the proper segments light Once all segments light or remain dark as they shouldiit will take 8 seconds for the number to be displayedispeed the clock up one setting at a time and observe the effect at each speed At 1 kHz the display will appear constant though a bit dimmer Questions to turn in with the lab report 1 Explain why the circuit connection on page 2 acts like a 18 demultiplexer 2 If this circuit were being used to transmit data over a single wire which connection on the nal circuit page 3 corresponds to the data wire Ignore timing problems with the counter 3 How do you think the phone company uses multiplexing to put many conversations over a single line 4 What other types of multiplexing can you think of Some notes on the simulation of this lab Your simulation package does not have 74151 and 74193 chip models Therefore you will have to make them from smaller parts that do exist The 74151 MUX can be made in one of two ways One approach would be to simply draw the AND OR diagram of an 8to1 MUX It39s pretty simple you just need eight 4input AND s each of which AND s the appropriate input line with the correct Minterm of the three select lines and an 8input OR function Hint Once you place a gate in Digital Works you can right click on it to increase the number of inputs to three or four Another approach would be to take advantage of the 4to1 MUX you made for Section 1 of this lab Two 4to1 MUXes can easily be connected to form an 8to1 MUX as shown below a Enables N u Output a UUUPUUUU q 32 31 30 Figure 7 8to1MUX from two 4to1 MUXes Digital Works does supply a 4bit counter macro which could be used for the 74193 but none of the pins are labeled making it hard to use Since we haven39t covered counters yet a counter macro is supplied to you on the lab web page You will also nd a macro for an 8to1 DEMUX on the lab page It is not exactly like the 74155 which can also be used as two 4to1 DEMUXes but it does have the lowactive outputs for this lab ECE 201 Lab 7 FourBit Combinational Multiplier PURPOSE To practice the combinational design process through the design of a 4bit multiplier EQUIPMENT Simulation Software REQUIREMENTS 0 Electronic copy of your design 0 Schematic of nal design 0 Printouts of any macros you used in your design 0 Brief report describing your circuit design and answering questions asked in the procedure INTRODUCTION This lab will be unlike preVious labs in two very signi cant ways First we re going to design circuits that are too complex to t on our breadboard with the parts in the lab kit so this lab will be done entirely with the simulator Second though this lab procedure will provide some insights into a possible design of a multiplier no circuit diagrams will be providediyou will do the design completely on your own The circuit you will be designing is a fourbit multiplier that is a circuit which inputs two 4bit numbers and outputs their 8bit product A truth table for this circuit would have eight inputs eight outputs and 256 rows You would need eight 8Variable Kamaugh maps to directly produce Boolean equations Since 8Variable Kamaugh maps would be quite unwieldy and we have not lea1ned the QuineMcCluskey algorithm we re going to have to think some about this one The following section describes the multiplication process in detail using steps that we39ve already gured out how to do After that it s up to you BACKGROUND The first thing you need to know about multiplication is that the AND operation works just like decimal multiplication l39l l and O39O O39l l39 O O The AND operator even has the same symbol as decimal multiplication So if you need to multiply a number by a single bit you can simply use AND gates Consider the example below 1011 1011 X l X 0 1011 0000 quotll 2139 I quotII quotI ICII quotII quotI quotll T r T l I 1 r r T l I I quotll Ill39 quotl quotl ll IEII III llill Things get a little more complicated when your multiplier has more than one bit The Boolean AND operator functions only with Boolean variables so we can only AND bits together not binary integers So how do we multiply multibit numbers together One way is to do things the same way we would perform the multiplication on paper multiply the first number by the least significant bit of the second number then add that result to the one you get by multiplying by the next bit and so on as shown in the example below 1 1 w 33 11 OH oo ooo IIIoIquot I I OOHO ol I I 1 1 1 12815 143 Note that we get an eight bit number from multiplying two fourbit numbers In the general case we can rewrite the problem symbolically below where Pij is the product AND of bit i of the multiplicand top number with bit j of the multiplier and Si is the sum of the column of numbers above it A3 A2 A1 A0 X B3 32 B1 B0 1330 1320 1310 1300 P31 P21 P11 1301 P32 P22 P12 1302 P33 P23 P13 1303 S7 56 55 S4 S3 52 51 So That s pretty close to something we can build We can multiply by single numbers and we can add numbers together The only complication is the adders we know how to build can only add two numbers at a time In this case we need to add up to ve bits at a time so we might want to create some partial sums to make use of the adders we have A possible way to do this is shown below A3 A2 A1 A0 X B3 32 B1 B0 P30 P20 P10 1quot 00 P31 P21 P11 P01 S05 S04 S03 S02 S01 S00 P32 P22 P12 P02 516 515 514 513 512 511 520 S7 Se 55 S4 53 52 51 So where Sij represents the j th output of the ith adder Notice that SOS is the carry of the rst adder 816 is the carry of the second adder and S7 is the carry ofthe third adder Also note that 00 is simply P00 Sn is equal to 01 and 2 is 812 Therefore we need only three fourbit adders which we have already built in lab PROCEDURE Bring an electronic copy of your design to lab with you and be prepared to demonstrate the operation of your functional multiplier Add appropriate switches and lights so that you can input two 4bit numbers and see your 8bit output D Tum in a printout of your nal schematic plus printouts of any macros you used in your designs as well Turn in a brief report describing your circuit design In your report consider if and how well this circuit design would scale up to multiplying bigger numbers Answer the following questions in your report 0 What would be the strengths and weaknesses of a large multiplier built in this fashion 0 What would the propagation delay be for the circuit in your simulation assuming a 1 ns delay for each gate A Note on Multipliers The multiplier you just built is pretty close to the kind used in highend arithmetic circuits a kind of multiplier known as an array multiplier Real array multipliers pass the carry through the adders to the last one rather than using ripple or lookahead adders to add the partial sums A special lookahead adder is designed for the last stage to speed up the process Multipliers built in this way are produce about the highest performance possible Many multipliers however are not built in this fashion A typical chip will use a much smaller slower but more complicated multiplier design based on registers which will be discussed in class ECE 201 Lab 8 Logic Design for a DirectMapped Cache PURPOSE To understand the function and design of a directmapped memory cache EQUIPMENT Simulation Software REQUIREMENTS 0 Electronic copy of your design 0 Schematic of final design Printouts of any macros you used in your design 0 Brief report describing your circuit design and answering questions asked in the procedure BACKGROUND Memory A computer39s memory is organized as a linear collection of storage locations Each location has an address Typical computer memories are byte addressable meaning that each byte in the memory has its own unique address even though you usually read the memory a word at a time and a word is typically greater than a byte The size of the address limits the amount of memory the computer can see Most computers use at least a 32bit address bus meaning they can address 232 Bytes or 4 GB of memory Naturally the rst Byte ofmemory is located at address 0 O O O O O O 015 and the last one is located at FFFFFFFF15 One of the most fundamental things a computer has to do is retrieve information from memory The main memory of a computer stores both the programs the computer will run and the data the programs need During operation a computer s processor continuously generates a stream of addresses rst to get instructions out of the memory and then to fetch the data operands that those instructions need Memory Hierarchy Unfortunately memory is relatively slow and I 39 when r J to r As a result a CPU can spend a lot of its time doing nothing while it waits for a memory request to complete In fact 50 bandwidth the amount of data you can transmit in a given time interval to memory is one of the primary limiting factors in a computer s efficiency It is called the von Neumann bottleneck To deal with this problem cost effectively a memory hierarchy has been created The basic concept is that data a processor needs most often will be kept in a small fast but expensive memory and less frequently used data will be kept in progressively larger slower and cheaper memories The fastest memory are registers on the CPU constructed of very fast transistorsithe socalled on chip or Level 1 cache The second level of the hierarchy is typically an offchip or L2 cache made up of a fast static RAM The third level is main memory generally made up of slower lessexpensive dynamic RAMs and the fourth level is the very large slow and inexpensive secondary storage such as a disk drive When the computer needs to read a byte of memory it generates an address The next step is to figure out where the data associated with that address is currently residing is it in one of the caches main memory or on disk The first thing to check is the L1 cache If the location desired is there this is known as a cache hit and the value can be read immediately Ifthe location is not there a cache miss occurs and the memory hierarchy must be searched through until the data and that around it is located and brought into the L1 cache Caches The purpose of this project is to build the logic that determines if the data located at a given address is or isn39t in the cache The output of your circuit will be a signal indicating whether we have a cache hit or miss We will be looking at a scheme known as direct mapped caching So before we can get started we need to examine how a directmapped cache works A cache is divided into a number of lines A line is a contiguous block of bytes in the memory that are stored at a single cache address We will be designing circuits for a fictional computer which has a 16bit address bus and a cache made up of 16 lines containing 256 Bytes each This means our computer will be able to address a total of 216 or 64 KB of RAM and at any time a maximum 16 39 256 4096 or 4 KB of this memory will be in the cache To use our directmapped cache we will break the address into three fields Since the 256 bytes that make up a lineblock are contiguous the last 8 bits 28 256 of any address is the offset into the cache line Since there are 16 lines in the cache we need four bits of the address to determine which line in the cache the address will be in The upper four bits of the address are the cache tag telling us which block is present The decomposition of the address into fields is shown in the following figure lbw bubnbub11b1o b9 bslb be h bb b b bo Tag Cache Line Other Address Figure 1 Fields of a Memory Address For example an address of llllOOlOOOllOOlO OxF232 has atag of OXF a line address of0X2 and an offset of 0X32 This type of cache is called directmapped because there is only one place in the cache where each address in memory may reside However since the cache is only 4 kB and the whole memory is 64 kB only 16 of the possible 256 lines can be in the cache at any one time The mapping of 256 bytes of memory to the cache lines is shown below Only memory addresses whose cache line address eld matches can be in a particular cache line Therefore if you are looking at cache line address 3 only memory addresses who have the bits O 011 in bits bu b8 can go into that cache line That is the only 256byte blocks whose addresses start at 0X03 OO 0x13 00 0x23 00 OxF 3 00 can go into cache line 3 Blocks that t into a particular cache line are shown across a row in the gure below Cache Main Memory Line TagContenWalid Blocks block con1ains 256 00000 1000 00011 00102 0011 E 01004 0101 5 0110 6 01117 1000 8 1001 9 1010 A 1011 B 1100 C 1101 D 1110 E 1111 F 1200 3200 F200 1400 1500 1700 1800 Contains Addresses through Note that for every address that goes into a single cache line the line address is always the same and there is exactly one block possible for each of the 16 tags Therefore to see if you have a cache hit you can ignore the offset and simply compare the tag to the tag currently stored in the appropriate line of the cache To make this easier associated with the cache there is a tag memory a small memory that stores the tag of each block currently stored in the cache line There is also one additional valid bit with each tag entry which indicates if any valid block is stored at that cache line at power on for instance none of the lines are filled yet there are several other cases when cache lines are invalid that we won39t go into For the cache described above a 16X5 memory would be needed to store the 16 4 bit tags plus their corresponding valid bits PROCEDURE You are to design and simulate a circuit which determines if a cache hit or a miss is made for the system described above You will have a 16X5 tag memory which you will implement using a ROM or RAM since they39re exactly the same in Digital Works You will initialize the tag memory according to the table below Address ValidTag 0000 1 0001 0001 1 0001 0010 1 1111 0011 1 1110 0100 0 0001 0101 0 0101 0110 0 1010 0111 0 1010 1000 1 0000 1001 1 0000 1010 1 0000 1011 1 0111 1100 0 0000 1101 0 1111 1110 1 0010 1111 1 0011 The most significant bit in each word will be the valid bit and the other four bits will be the tag You will receive as input a 16bit address You will use the cache line address bits to retrieve the appropriate tag from your memory Then you will compare the tag you got from the memory to the tag in your address using a 4bit comparator you are expected to design a 4bit comparator macro see below You will have one output hit which will be a 1 if the tags are equal and the valid bit is l and a 0 otherwise Connect eight switches to the inputs of your simulation corresponding to address bits 815 so your instructor can enter addresses to test the design Wire the hit signal to an LED Bring an electronic copy of your design to lab with you and be prepared to demonstrate the operation of your functional memory cache Add appropriate input switches and an output light so that you can input the eight highorder bits of the 16bit address consisting of a 4bit tag and 4bit cache line and see your LED output A cache hit is lit and a cache miss is unlit A Note on Comparators Recall that the XNOR function is also called equivalence where x By xy x39y39 Also recall that two binary numbers would be equivalent if the rst bits were equivalent and the second bits were equivalent and the third bits were equivalent and so on ECE 201 Lab 9 Sequential Design Three Bit Counter PURPOSE To understand the design and restrictions of Sequential Circuits EQUIPMENT ECE 201 Lab Kit amp Digi Trainer Simulation Software REQUIREMENTS 0 Electronic copy of your design 0 Schematic of nal design 0 State Transition Tables 0 Karnaugh Maps with Boolean reductions for each variable 0 Brief report describing your circuit design and answering questions asked in the procedure PROCEDURE Assume that you have just designed and built a sequential circuit for a robot which will complete the remainder of your engineering classes for you All you need to complete it is an updown threebit counter It is Sunday night and you have three tests on Monday Unfortunately Radio Shack is closed so you will have to make do with your 201 Lab Kit or you will have to take those tests yourself Looking in your parts bag you nd the following parts left 1 7476 Dual J K Flipflop 1 74175 Quad D Flipflop With several of each of the following o 7408 Quad 2 input AND o 7432 Quad 2 input OR o 7486 Quad 2 input XOR Next you realize that the only thing remaining for you to construct the counter on is your Digi Trainer box which limits you to only five chips It is immediately obvious that the 7476 is insufficient since you need three ip ops thus you start by choosing the 7415 which contains four ip ops Next you do a quick design and using c as the control bit variable C 0 means count up C 1 means count down and Q3Q2Ql as the counter bits you obtain the following equations for the three inputs to the D ip op D3 CQ3Q2Q1 C Q3Q2Q1 C Q3Q2 CQ3Q1 Q3Q2Q1 D2 CQ Qi CQle CVQVZQl C39QzQi With only twoinput AND and OR gates the decoding for D3 alone would require four packages thus the Digi Trainer is not large enough Leaving that for the moment you move on to D2 This looks bad super cially but after a moment s re ection you realize that can be implemented with dual 2input XOR gates D1 must have Q 1 but this is available on the 74175 Well two out of three implemented and less than two full chips used isn39t bad for a start If you could implement the remaining bit with three or fewer chips plus two XOR gates you ll have the rest ofthe semester off You next try using a J K ip op for bit three You decide trying to gure out how to use some XOR s to implement D3 would take too long and might not work anyway As it turns out the J and K inputs for Q3 can be realized using one 7408 and one OR gate Determine the appropriate circuitry for J and K and connect the whole mess using a switch for the control bit In addition connect one of the pulsers or switches if pulsers are not available to the clear inputs of the 7476 and the 74175 to allow presetting of the counter to 000 This should be the pulser pin that goes low when the button is pressed Note that the preset pin of the 7476 must be tied to 5V Use three lights for the output Which bit goes to the left most light Initially use the clock at 1 Hz to clock the circuit HINTS Make out the complete state transition table to get J and K This is not absolutely necessary but may avoid confusion and errors Compare the equations for J and K If you don t immediately see how to implement D with two XOR s factor out the c and c39 terms to recognize the XOR Use an extra XOR to invert c as you did for the addersubtractor circuit Verify that the circuit counts up if c is 0 and down if c is 1 Also verify that the pulser clears the counter Note The clock of the 74175 must be inverted relative to that of the 7476 Either use the complimentary clock outputs on the DigiTrainer or invert the clock with an XOR 0 Watch the power connections on the 7476 If you hook up pin 13 to 5V and pin 5 to Ground You will destroy the chip 0 Is it possible to implement D3 within the stated limitations Ifso how


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