Indus Simulation IMSE 643
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This 7 page Class Notes was uploaded by Abe Kuhic IV on Monday September 28, 2015. The Class Notes belongs to IMSE 643 at Kansas State University taught by Chih-Hang Wu in Fall. Since its upload, it has received 17 views. For similar materials see /class/214952/imse-643-kansas-state-university in Industrial & Manufacturing Engineering at Kansas State University.
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Date Created: 09/28/15
IMSE 643 INDUSTRIAL SIMULATION HOMEWORK PROJECT 2 DUE BY 500PM FRIDAY OCTOBER 22 2010 Consider the Double Data Rate DDR Memory packaging facility described in Homework 1 with the following changes The pre and postpackaging inspection operations are now separated into two separate workstations due to the demands on additional capacity The 8 wafers to the system 120 sets at a time and the interarrival times are exponentially distributed with a mean of 24 hours The 12 wafers to the system 240 sets at a time and the interarrival time follows a normal distribution with the mean of 48 hours and the standard deviation of 6 hours Both wafer types arrive in deliver trucks but there is only one unloading bay in the facility other trucks have to wait in the parking lots outside the facility There is an additional Plastic Molding station with two plastic molding machines that premold the plastic packaging materials for packaging the memory chips The plastic molding machine s throughputs is unknown however a set of 2000 observations on the plastic molding machine are available in per hour The machine produces 60 of the packaging materials for 2GB DDR chips Model A and 40 for the 1GB DDR Model B Assuming the raw plastic materials for feeding the molding machine need to be re lled every 6 hours according to l 39 39 quot quot 39 which can produce 300 000 plastic molds You have to model this part as part of vour 39 Before the memory chips go into the packaging station 2 the memory chips have to be matched with the proper plastic packaging counterpart At each workstation if not speci ed otherwise one operator is needed to perform a single job operation The Plastic Molding operations need only the machine not labor and the testinginspection stations consists of a critical testing equipment each that requires 2 operators for each The preinspection station has 2 inspection machines The inspected 8 and 12 wafers are sent to the separation station on a miniwafer pallet pallets can take wafers in both sizes and only one pallet can be loaded at a time at the end of inspection station The pallet has a capacity of 10 wafers The pallet is moved to the die separation station with following two situations 1 the pallet is lll or 2 the pallet has been waiting more than 12 hours long The pallets are delivered to the die separation station by one of the operators using an handcart not the forkli s routing time follows UNIF35 minutes where the pallet remains until all the wafer are loaded on the separation machine and only then the pallet can be released The empty pallets are returned by the operator back to the assembly station There are total of 15 pallets available for the process The die separation station has one separation machines that require one operator on each job The die separation station separates an 8 wafer into 100 dies of lGBB DDR RAM chips and separats an 12 wafer into 180 dies of 2GB DDR RAM chips After the separation operation the memory chips are handledtransported in trays that hold 3050 chips per tray The packaging process consists of two packaging workstations with a backup station as described in Homework 1 that pack the corresponding DDR RAM models Each work station requires one operator The backup station uses 2 operators per operation The packaged memory chips are sent to the post packaging inspection station Two operator are needed to operate the testing equipment for each inspection batch The processing time given in homework 1 are assumed to be for 10 chips The transportation among the plastic molding station die separation station packaging stations and the postpackaging inspection station is accomplished by using ve battery operated miniforkli s The distances among these workstations are given in Table l Page 1 IMSE 643 INDUSTRIAL SIMULATION HOMEWORK PROJECT 2 DUE BY 500PM FRIDAY OCTOBER 22 2010 Assume that all operators are cross trained so that any operator can perform any of the operations There are total of twentyfour operators and four miniforklift truc s The velocity of the miniforkli truck is 800 ftmin The distances between the stations in feet are as follows WP gt 90m 9 0 Model the above subsystem using SIMANARENA Simulate the process for 36000 sets of finished 12 wafers and 24000 of nished 8 wafers You are required to use the sequences to route the wafers and memory chips in the system Report average and maximum workinprogress inventory in terms of number of memory chips for each model and operators utilization Collect the following statistics for each workstation machine utilization maximal and average queue lengths queue times and average cycle times Determine the optimal tray size after the die separation station for your system Report how many pallets were sent forward before they were full Recommend optimal number of operators and optimal number of inspection equipments in each station Assuming the cost of the inspections equipment runs 3 million a pieces please justify your recommendations and it costs 200hour of waiting times in the inspection stations for each tray of DDR chips Assume that the critical testing 39 l quot l 391 t in the pi malfunctions from time to time When the inspection station is down the process has to be stopped and the rest of the jobs have to be performed after the equipment is fixed The time between breakdowns is exponentially distributed with a mean of 20 hours Maintenance on the critical equipment is performed by a single engineer who takes an exponentially distributed repair time with a mean of 3 hours Calculate the maintenance person utilization add one more maintenance engineer 39 station 1 Each 2GB memory chip can sell for 30 and each 1GB memory chip can be sold to 12 Determine the optimal product mix for the system You can change the product arrivals and production targets in question 1 to determine the optimal product mix Assuming production costs for each 2GB and 1GB chip is 20 and 7 respectively Page 2 IMSE 643 INDUSTRIAL SIMULATION HOMEWORK PROJECT 2 DUE BY 500PM FRIDAY OCTOBER 22 2010 Additional Requirements for Graduate Students N 2 Estimate the capacity of the system by gradually increasing or decrease the inputs optimize the arrival patterens to the system until the system cannot effectively produce jobs Determine optimal priority schemes to maximize your productivity and clearly define what the productivity means Detect the bottlenecks in the previous setups and see if you still can increase the capacity by making changes to the system State your changes and study the tradeoff between the additional capacity and the additional resources that you have to commit to get that extra capacity Page 3 IMSE 643 INDUSTRIAL SIMULATION HOMEWORK PROJECT 3 DUE DATE 500 P M FRIDAY NOVEMBER 12 2010 This is an project to be performed individually Consider the Memory Chip Packaging subsystem described in Homework 2 Consider the following changes to the system setup 0 The waferspallets and dietrays are transported in batches between any two workstations using 6 AGV s Assume that there is one Entering station and one Shipping station There is no AGV needed for the transportation between Packaging 2 station to Backup packaging The network map and distances are given in Figure 1 below 0 Add one more equipments in the postinspection station the die separation station respectively to your system and give the pre and post inspection stations highest priority for obtaining operators Assume the operators are allowed to work across the stations The dietrays departing from packaging operations have the highest priority for requesting an AGV The dietrays departing from the separation station have the second highest priority for requesting an AGV Assume that we give higher priorities to when the tray spent longer time in the system for the postinspection queue shipping queue and packaging queues Requirements for All Students 1 5 Model the above described subsystem using SIMAN andor ARENA Simulate the process for 30 replications of one year worth of operation in each replication Report average workinprocess inventory for each model both on wafer and chip counts AGV and operator utilizations Collect the maximal and average queue length and queue time for the AGV queue Collect the following statistics for each workstation machine utilization if a machine resource needed maximal and average queue lengths queue times and average cycle times Use the statistical output analysis techinques to determine whether the following performance parameters are significantly different from the original setup in Homework Project 2 This means you will have to run your Homework 2 models 30 replications of one year each as well or not 0 Average WIP inventory levels 0 Total ow times and total cycle times for both models 0 Queue times and queue lengths for the inspection and packaging operations Determine the optimal number of operators and what are the best assignments of these operators Report the change in the output statistics Page 1 IMSE 643 INDUSTRIAL SIMULATION HOMEWORK PROJECT 3 DUE DATE 500 P M FRIDAY NOVEMBER 12 2010 Additional Requirements for Graduate Students Simulate the process for 10 replications of successfully processing 36000 sets of finished 12 wafers and 24000 of 8 wafers respectively in each replication and perform the same output analysis Use different random number seeds for interalrival times processing times and transportation times In addition determine whether the system throughput has been signi cantly improved by the new setup N Use the variance reduction techniques to determine the estimated relationship between the interarrival times and the computers nished for both models E Determine the optimal arrival patterns for the wafer about to minimize your production cycle 80 50 Q Entering Staging 60 Molding Pack1 Pack ng Sep ration 100 AGV Velocity 65 ftmin Acceleration 8 ftmin2 Deceleration 10 ftmin2 Turn Velocity 085 Size 1 zone Zone Size 10 ftzone Intersection length 3zones Figure 1 Network Map for AGV39S Page 2 IMSE 643 INDUSTRIAL SIMULATION HOMEWORK PROJECT 1 Due by 500PM Friday September 24 A computer memory packaging facility consists of six workstations one inspectiontesting station one die separation station two Integrated Circuit packaging stations a backup packaging station and a shipping station Wafers of two different sizes of 8 inch for 1GB DDR RAMs and 12 inch for ZBG DDR RAMs supplied by two upstream wafer manufacturers are tested cutted and packaged using the same facility The rst upstream wafer factory sends parts for 8 wafers to the subsystem 10 sets at a time and the interarrival times are exponentially distributed with a mean of 12 hours The second upstream wafer factory sends 12 wafers to the subsystem 20 sets at a time and the interarrival time follows a normal distribution with the mean of 36 hours and the standard deviation of 6 hours The wafers for both sizes are tested upon arrival at the inspectiontesting station The inspection station tests the parts for any damage during manufacturing and shipping If the wafer are con rmed good it is sent to the die separation station otherwise the wafer for the model is discarded The Die Separation Station separates an 8 wafer to 4 dies of 1GB DDR RAM chips and an 12 wafer to 8 dies of 2GB DDR RAM chips The processing times of the separation and inspection stations follow triangular distributions and the corresponding parameters are given in Tables 2 and 3 The separated dies are then forwarded to the packaging stations for wire bonding and plastic packaging operations The die packaging process consists of two packaging workstations that put the die into an plastic package bond the golden wires to the die and sealed with packaging material Dies for 2GB DDR must go to the packaging station 1 and then to the packaging station 2 Dies for 1GB DDR must go to the packaging station 2 and then to the packaging station 1 Packaging station 2 has only 128 buffer spaces If the packaging station 2 runs out of buffer spaces the parts are re routed to another backup station The processing time for the backup station is the same both memory chips and is distributed uniformly between 05 to 15 minutes After the chips have been packaged they are sent to the inspectiontesting station Then the inspection station tests the functionalities of the packaged memory chips If a chip is confirmed as a good product the chip will be sent to the shipping department and then the chip departs the system If the memory chip is considered as a noncon rmed product it will be discarded If the memory chips goes through the backup assembly station it is considered to be inspected online and does not need to be reinspected at the inspection station It would directly go to the shipping station The processing times for the two packaging stations separation station and the incoming inspection station follow triangular distributions The processing times for the shipping station and the postpackaging inspection is based on normal distribution The corresponding parameters are given below Table 1 Processing Times for the Packaging Stations in minutes Packaging 1 Packaging 2 Max Max Page 1 N E 4 IMSE 643 INDUSTRIAL SIMULATION HOMEWORK PROJECT 1 Due by 500PM Friday September 24 Table 2 Processing Times for the Separation Station in minutes Separation Operation 1GB 15 Table 3 Processing Times for the shipping incoming inspection and post packaging inspection station in minutes Dev Max Model the above described subsystem using SIMAN or Arena Simulate the process from Janurary 1 2010 March 31 2010 Assuming 24 working hours per working day and 7 working days a week Report the average number of memory chips produced from this system each day and number wafers have entered the system each day Collect the following statistics for each workstation machine utilization maximal and average queue lengths and average cycle times Remodel the subsystem for the case where 2GB DDR RAMs are given higher priority over 1GB DDR RAMs and compare your results Assume that the failure rates for receiving inspection are 8 and 12 for 8 and 12 wafers respectively Assume that the failure rates for post packaging testing are 5 and 8 for 1GB and 2GB DDR RAMs respectively Additional Requirements for Graduate Students Need additional sections clearly disscuss the pros and cons of each recommendations 1 N Assume that the memory chips are processed according to a priority established based on their time spent in the subsystem Model the system again and see if there has been a change in the outcome Detect the bottlenecks and suggest a solution to eliminate them Model the system again according to your suggestion and compare the results with the original model setup Page 2
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