Digital System Design w VHDL
Digital System Design w VHDL ECE 545
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Date Created: 09/28/15
ECE 545 Digilal System Design with VHDL Lecture 11 Design Ophmizanon 111808 Outline 39 Demgn Opwmzauon 1pe11mng Rewmng swam Macmne Encodmg C1ock1ngFSM 0mm CAD Too1Op11onsVoyanS1s and1mp1ememamn Ammmme 1mpvovemen s Add111ona10p11mza11ons P3131191 oncessmg Fo1d1ng Un1o1dmg swarm men Puma Specmc Usmg SW1 Regmevs SRL P101901 Specmc Reduc1ngTo1a1 Fvocessmg Tune 39 Vanamesversusagnas Resources Voinei Pedrom Circuit Design with VHDL Chapter 7 Signals an V ria es Chapter 9 State Machines Design Optimization Design Optimization Typicaiiy you design ior one or more oi the ioiiowing Smaii aiea P Higniniougnpui Laigeiniougnpuiaiea Tne ioiiowmg siides show now to optimize a design to improve its periormance in one or more oi the above metrics 1 Pipelining Combinational Logic Timing tLOGlC t5 tCLKZO clk CLOCK PERIOD T tCLK2Q tLOGIC lt T ts to avoid setup time violation Rewriting the equation tCLK2Q tLOGIC tS lt T a J tpalh Critical Path A path is defined as a path from the output of one flipflop to the input of another flipflop 39 Path delay tpath tCLK2Q tLOGIC ts The largest of all the path delays in a circuit is called the critical path delay tormcalipath The associated path is called the critical path There can be millions of paths in a circuit timing analysis CAD tools help to locate the critical path Minimum Period and Maximum Clock Frequency The minimum period a circuit can be clocked is equal to the critical path Tmin tcn39ticaLpath Maximum frequency 1 Tmin 1 tcmicaLpath Timing parameters de nition units delay time from point gtp0 int ns clock period T rising edge gtrising edge us of clock clock frequency MHZ clock perlod latency time from inputaoutput US throughput output bitstime unit MbitS S Latency 8 bIIs I I I Dml al a I InPUt I Eng t H I output I 39 I I I I I I 39 I clk input X inputo X input1 x input2 x X x output unknown X outputO X outputl Latency is the time between inputn and outputn Ie tIIne takes lrorn lIrst Input to lIrst output second Input to second output etc Latency Is usually constant tor a system but not always Also called Inputtooutput latency 30qu the number oi rising edges oi the ciku ln tnIs example 3 rIsIng edges lrom Input to output latencyIs 3 cycles Latency is measured in clock cycles then translated to seconds ln tnIs example say clock perIod Is IO ns tnen latency Is 30 ns 11 Throughput input Il clk input X input0 X input1 X input2 X X output unknown X outputO X outputl 1 L Mmesen u L a r r Bits per output sam le r p oulpul samples In tnIs example 8 bIts per output sarnple r r I r r Can be measured In clock cycles then translated to tIIne ln tnIs example tIIne between consecutIve output samples 1 clock cycle 10 ns Throughput 8 bits per output sample 10 ns 08 bits ns 800 Mbitss Pipelining Conceptual tLOG C 10 ns 0 Assuming tCLKZQ tS 0 ns the critical path is 10 ns and the maximum clockfrequency is 100 MHz Latency 2 cycles Pipelining Conceptual Combinationa register splits logic in haltquotquot tLOGlCA 5 5 tLOGlCB 5 5 Purpose of Fipeiining is to reduce the critical path of the circuit by inserting an additional register cal ed a pipeline register This splits the combinational logic in hall Now critical path delay is 5 ns so maximum clock frequency is 200 MHZ Double the clock lrequency However latency increases to 3 cycles and area is increased due to additional register In general pipelining increases throughput at the cost of increased latency and areapower Pipelining Real Life Issues Combinationa L Lo tCLKZO 05 ns tLOG c 10 ns t5 06 ns In real designs cannot ignore tCLKZQ and tS This circuit has tormcaLpath 111 ns 9 maximum clock frequency 90 MHz Latency 2 cycles Pipelining Real Life Issues Combinationa register splits logic in halfquot Combinationa Logic A t 06 ns tCLKZO 05 ns tLOG CA 5 ns tS 06 ns tLOG CB 5 ns 5 tCLKZO 05 ns This circuit has to W 61 ns 9 maximum ciock irequency 163 MHZ o 7 2h instead at ideai Ztimes taster Latency s cydes Spiitting the combinatiohai iogic into three equai iogic sections 013 33 ns i m cioddiequericy 227 MHZ 2 27mm taster instead oi ideai s timestastei tency 4 cydes Important 1mm and iscause real overhead in reai designs usuaiiy LOGiCA and LOGiCB do not cohvehiehtiy equai exactiy haii oi LOGiC Sometimes they are more some imes they are iess depending on gates Wire eiays etc The worstrcase path at tLOGiCA and tLOGiCB determines ciiticai path Timing parameters de nition unlts pipelining delay time from point gtp0int ns clock period T rising edge gtrising edge ns good of clock 1 MHz clock frequency good clock period latency time from inputaoutput US bad throughput output bitstime unit Mbitss good Pipelining Note 1 Feedforward vs Feedback PIEeIInIng In general pipelining only possible on feedforward paths not feedback paths Feedback path pipelining requires special examination to retain the same functionality Feedforward paths can be pipelined with no change in functionality only a change in latency 9 XOR function Feedforward Path versus Feedback Path i dout H i i r dll i R4n1 R4n R2n R1 n R0n FEEDBACK SECTION generally cannot be pipelined unless certain properties exist FEEDFORWARD SECTION generally can always be pipelined Pipelining Feedback Path a 9 XOR function comb logic lockup table 1 1 dout I E i dll i Previously R4n1 R4n R2n R1 n R0n Now if we insert pipeline register R4n1 R4n R2n1 R1 n1 R0n1 This is the wrong equation In general be careful with trying to pipeline feedback systems or you will change signal ow graph equations Pipelining Feedforward path Assume this is critical path and want to W insert pipeline register here to make I comb logic lookup table part A comb logic lookup abl r e partA 9 XOR function i dout 39 d This does not change the functionality only the latency so pipelining is fine Very important Be sure to add register to din to ensure 39 39 paths is the same 21 Pipelining Note 2 Using the Synthesis Tool You can add pipeline registers manually or have the tool assist you Synplify Pro and XST have a pipelining option This means you can leave a number of pipeline registers at the end of a combinational logic function and the tool will move the registers to achieve the best critical path delay The tool does not create pipeline registers It only moves the ones which you provide in your VHDL code Example of Synplify Pro or XST Pipelining Option Before Pipelining Note 3 Effects of Pipelining on Controller ASM and Timing of Control Signals Also make sure any pipeline stages added in your datapath are reflected in your ASM o Ifyou are not careful you may enable a register or counter one cycle too soon or too late Pipelining Summary In general pipelining increases throughput at the cost of increased latency and areapower Important tCLKZQ and t8 cause real overhead For beginners do not pipeline feedback paths pipeline feedforward paths only If you add a pipeline register to one path make sure all paths which require the same timing converging or diverging paths have pipeline registers as well to maintain correct timing Also make sure your controller ASM reflects any pipeline registers added in your datapath else you may enable a counter one cycle too early or late or your inputoutput data may be one cycle too early or late May not be too useful for the project Multipliervhd lerary IEEE use leeevstdiloglcills vall7 use leeevstdiloglciunslgnedvall entlty multlpller 15 gener1c inputsislze integer 32 e 32 plpellne 1nteger 2 H p1pe11ne glves number of p1pe11ne stages H 1 comblnatlonal clrcult port clock 1n stdiloglc 1nputA 1nputB 1n stdiloglcivectorluputsislzeel downto 0 output out stdiloglcivectoroutputislzerl downto 0 end multlpller archltecture behavlor of multlpller 15 5191131 result stdiloglcivector21nputsislzeel downto 0 type p1pe 15 arrayp1pe11neel downto o of stdiloglcivectoroutputislzeel downto o slgnal plpellneiregs plpe Multipliervhd cont39d quotin Multipllcatlon 777777 resu1t lt 1nputA 1nputB Plpellne stages 77777 H plpellneiregsplpellnerl lt resultmutputislzerl downto o Ujlpellne for 1 1n p1pe11ner2 downto o generate Uireglster processclock begln fclock 39139 an clock39event tnen ellneiregsu lt plpellneiregsu rl end 1f end process end generate output lt p1pe11ne7regs O end behavl or Multiplierimplvhd lerary IEEE use leeevstdiloglcillszlvall ent1ty multlpllerilmpl 15 gener1c inputsislze integer plpellne 1nteger 4 H 1pe11ne glves number of p1pe11ne stages 1 comblnatlonal clrcult 7 port clock 1n stdiloglc 1nputA luputB 1n stdiloglcivectorluputsislzerl downto 0 output out stdiloglcivectoroutputislzerl downt end multipllerilmpl architecture 1mp1ementatlon of multlpllerilmpl 15 Multiplierimplvhd component multlplier c luputsislze 1nteger Outputislze 1nteger p1pe11ne 1nteger H 1pe11ne glves number of p1pe11ne stages 7 1 comblnatlonal clrcu 7 port clock 1n stdiloglc 1nputA luputB 1n stdiloglcivectorinputsislzerl downto o output out stdiloglcivectoroutputislzerl downto o 7 end component signal 1nA7reg 1nB7reg stdiloglcivectorluputsislzerl downto 0 5191131 result stdiloglcivectoroutputislzerl downto begln Multiplierlmplvhd Uilnputireglster process clock begln fclock 39139 and clock39event then 1nA reg lt 1nputA 1nB7reg lt 1nputB an end process Uimultlpller multlpller generlc map luputsislze gt luputsislze Outputislze gt Outputislze p1pe11ne gt p1pe11ne port map 1nputB output Uioutputireglster process clock begln fclock 39139 and clock39event then o put lt result d 1f nd ocess end 1mp1ementat1on 2 Retiming Retiming using Synplify Pro and XST Rettmmg moves regtsters regtster batahcthg across combthattohat gates or LUTs ensuring identica behavior Does not change the number ot regtsters m the path but may change totat number ot regtsters m the demgh ts a superset ot ptpettmhg Retiming Example 1 Before Register 3 Register Register l Small 39 combinatorial 5 logic deiay 39 Ioglc delay n A A i A Register is pushed thmugh After 39 combinatorial logic Register h Register Balanced Iogicdelay A asquot A is very similar to pipelining logic delay V A In this example retiming L Retiming Example 2 Before 1 After ZED D In this example functionality is exactly the same but the total number of registers in the circuit is different Retiming using Synplify Pro and XST Often retiming is set to off turn on to enable tool to retime Retiming only works if all registers share same reset enable clock etc If any of these are different then moving the register would potentially change the functionality of the circuit Options to Select In Synplify Pro Pipelining can be turned on using quotPipeliningquot option 0 Default on Retiming can be turned on using quotFletimingquot option 0 Default off In XilinX XST Pipelining and Retiming both turned on using quotRegister Balancingquot Option 0 Default off When using Aldec interfacing to XST look for quotXilinx Specificquot Tab Be careful when using nondefault flags as you may get strange behavior depending on coding style 3 State Machine Encoding Slate Encoding Problem 39 Siaie Encoding Can Have a Big iniiuence on Opiimaiiiy oi ine FSM impiemeniaiion o neinodsoin iinanoneoking aii possibie encodingsaie known in pioduce opinnaiciicuii Feasibieioismaiioiicuiison 39 Using Enumeiaied Types ioi Siaies inVHDL Leaves Encoding Piobiem ioi Syninesis Tooi 39 Can av mai stale assunmem code exaciii now you wani ine siaies in be assigned39o binaryvaiues OR synthesb Tool stale assunmem aiiowine syninesisiooisio assign siaies w binaryvaiues Types of State Encoding Binary Sequential States Encoded as Consecutive Binary Numbers Small number of used flipflops Potentially complex transition functions leading to slow implementations OneHot Only One Bit ls Active Number of used flipflops as big as number of states Simple and fast transition functions Preferable coding technique in FPGAs Binary versus OneHot State Binary Code OneHot Code so 000 10000000 81 001 01000000 82 010 00100000 83 011 00010000 84 100 00001000 85 101 00000100 86 1 10 00000010 87 1 1 1 00000001 A userdefined attribute for manual state as3Ignment ENTITY declaratlon not shown ARCHITECTURE Behavior OF simple IS YPE Stateitype IS A B C ATTRIBUTE ENUMiENCODING STRING ATTRIBUTE ENUMiENCODING or Statsityps TYPE IS quot00 01 11quot SIGNAL yjresent yinext Stateitype BEGIN cont39d Using constants for manual state assignment ARCHITECTURE Behavlor OF Slmple Is SUB ABCisTATE is STDiLOGIcivECTOR1 DOWNTO 0 CONSTANT A ABCisTATE CONSTANT B ABCisTATE CONSTANT C ABCisTATE SIGNAL yjrsssnt yinsxt ABCisTATE PROCESS w yjresen N CASE yjresent IS WHEN A gt IF w 7 39039 THEN yinext lt A ELSE yinext lt B END IF cont39d V V V Synplify Pro State Assignment Synthesis Options 39 ompi r sop o e rac s i o Imlzes V s a soreencoes e FSMs based upon the number of states 0 2 4 Sequential 5 40 Onehot Over 40 Gray It is recommended that you enable this option However the chosen encoding may not be optimal If the critical paths go through a statemachine andor through the output decoding logic of a statemachine it Is worth experimentln With different engodings This is achieved through the syniencoding attribute in t e constraint file s c Additionally VHDL enumerated types that are not FSMs are encoded based on the efault Enumerated Encoding implementation option It is recommended to initiall set this option to quotdefaultquot which provides the same statebased scheme describe above Similarly it may be worth experimenting with different encodings through the synienumiencoding attribute in the constraint file sdc M Explorer This option performs a timingdriven state encoding The Synplify Pro tool automatically selects the best encodin or the specified timing ltis recommended to leave this option disable but If you turn It on you Will see FSMs In the critical path Source http39llwww 39 39 39 quot 39 Iwouwa Synplify Pro options for enumerated types that are not state machines Default Enum Encoding Specifies default encoding style for enumerated types default encoding style is set by the synthesis tool sequential more than one bit of the state register can change at a time but because more than one bit can be hot the value must be decoded to determine the state For example 000 001 010 011 100 onehot only one bit of the state register changes at a time and only one of the state registers is hot driven by a 39139 For example 0000000100100100 1000 gray only one bit of the state register changes at a time but because more than one bit can be hot the value must be decoded to determine the state Forexample 000 001 011 010 110 Xilinx XST State Assignment Synthesis Options FSM Encoding Algorithm This option allows setting the fsmiencoding constraint that determines the finite state machine coding technique to be used You can select one of eight options from the drop down list box Auto selects the needed optimization algorithms during the synthesis process OneHot ensures that an individual state register is dedicated to one state Only one flipflop is active or hot at an one time Onehot encodin is very appropriate With most FPGA targets where a large number of flipflops areavailable It is also a good alternative when trying to optimize speed or to reduce power dissipation Compact this option will minimize the number of state variables and flipflops This technique is based on hypercube immersion Compact encoding is appropnate when tiying to optimize area codes to the states on these paths Next state equations are minimi Gray this option will guarantee that only one state variable switches between two consecutive states It is appropriate for controllers exhibiting long paths Without branching Johnson The Johnson encoding option much like the Gray option shows benefik with state machines containing long paths With no branching User this option will cause the synthesis tool to use the encoding defined in the source file None disables automatic FSM extraction Sequential this option consisk of identifying long paths and applyingdsuccessive radix two ze Optimizing State Machines You can manually encodes the states or apply various synthesis tool encoding options to achieve an optimal state machine design 4 Clocking FSM Outputs Critical path can be irom controller to daiapaih MSW 39 Ca mhingr Mm Reset cw Solution Register the controller outputs Reset Clock Present State BREAKS THE CRITICAL PATH Clocking FSM Outputs Concerns Be careful that your state machine and inputoutput are in sync with the new registered outputs Else you may get an enable or a mux signal which arrives a cycle too early or a cycle too late You may also get inputs and outputs to the system which are a cycle too early or late 5 CAD Tool Options for Synthesis and Implementation Motivation The user can impiement diiiereni options on Synpiiiy Pro and XST ior synthesis as weii as Xiiinx iSE ior impiementaiion These aiiow the user to taiior according to area speed power eto Specific flags For specific flags and explanations see Synplify Pro Synthesis httpsupportaldeccomKnowedgeBaseArticleaspxaid000705 ampshowquot 10909 39svnplicitv svnthesis Option XST Synthesis httpsupportaldeccomKnowedgeBaseArticleaspxaid000705 ampshowAvh00202htmxst synthesis options Xilinx ISE Implementation httpsupportaldeccomKnowedgeBaseArticleaspxaid000705 ampshowAvh00203htmitxilinx ise imp options Pay particular attention to the EFFORT of all the tools Synplify Pro Tips and Hints Useful tips and hints at httpwwwsynplicitycomiteraturesyndicatedarchivehtml 6 Architecture Improvements Architecture Improvements The most eHectwe way 01 mprovmg your deswgn rs otten through archneoture mprovemen s T ese means mptememmg a dMerent archneoture tor your b ock e carryookahead adder r carryHome adder usmg a RAM versus a ookup tab e etc 7 Additional Optimizations Parallel Processing Folding Unfolding Strength Reduction Additional Optimizations Additional optimizations include parallel processing lolding unlolding strengtn reduction etc Some topics covere VLSl digital signal p oliered next sernest 5 some n a new din EOE 64 rocessing class ECE 699 to be er Unfolding Simple Example During round operation for n0 to 19 do An1 lt Bn and Bn1 lt An Cn and Cn1 lt An Assume critical path is 10 ns 0 20 rounds x10 ns 200 ns processing time Unfolding Simple Example Cont39d Unfold by 2 times ie do two rounds at a time An1 lt Bn and Bn1 lt An Cn and Cn1 lt An An2 lt Bn1 and Bn2 lt An1 Cn1 and Cn2 lt An1 Thus An2 lt An Cn and Bn2 lt Bn An and Cn2 lt Bn Critical path is still 10 ns but now do two rounds at a time so only do 10 super rounds total 0 More area but less processing time 10 rounds x10 ns 100 ns processing time 8 Project Specific Using Shift Register SRL16 Xilinx CLB Configurable logic block CLB Al Al Slice Slice 1 CLB f r f CLB ff Logiccell l Logiccell l Logiccell l Logiccell l Slice Slice 1 CLB W H CLB L l Logiccell l Logiccell if WT Logic cell l Logic cell l The Design Warrior s Guide to FPGAs Devices Tools and Flows ISBN 0750676043 Copyright 2004 Mentor Graphics Corp wwwmentorcom 62 Simplified view of a Xilinx Logic Cell a lt b gt c c y d lt flipflop q 9 FDC clock clock enable setJreset The Design Warrior s Guide to FPGAS Devicesy Tools and Flows iSBN 0750676043 Copyngnl2004 Mentorerapnics Corp WWW mentor com 63 um Each LUT can be configured as shift register 0 Serial in serial out Dynamically addressable delay up to 16 cycles For programmable pipeline Cascade for greater cycle delay Use CLB flipflops to add depth 8 DEPTH3 0 Shift Register 12 Qcles Operation A Operation B 3v cls eraionC i 3 Qcles Registerrich FPGA 9Cvcle imbalance 0 Allows for addition of pipeline stages to increase throughput Data paths must be balanced to keep desired functionality Instead of needing 5 slices each with two flipflops using shift registers SRL16 need only 1 slice 39 More info htiplwwwxilinxcomisupportdocumentationuseriguidesu9331pdf Spartan3 SRL16 Primitive gure 7a snLctaE Primitive The shift register can be configured eight ways Note 0 Can have an enable signal 0 Cannot have a reset or set signal 0 quotonlyquot left shift supported but often tools can easily figure out how to turn right shift into left LFSR Artificial Example R29 R28 input output 0 32 flipflops required Can use 16 slices each slice has two flipflops in logic cell OR can use 2 slices each slice has two SRL16s Using Set and Reset o If reset goes to all 32 flipflops then cannot use SRL16 Solution Only R31 gets a reset signal The rest of the flipflops do not Often but not always it is good enough to reset or set only the flipflop receiving the input bit Try to implement this in your project if possible during the optimization phase of the project VHDL code not inferring SRL16 llbrary IEEE use IEEEVSTDiLOGIC71164Vall7 entlty shlftreg 15 port clk 1n STDiLOGIC7 reset 1 1n STDiLOGIC7 1nput 1n STDiLOGIC7 Output 1 out STDiLOGIC 7 end snlftreg archltecture behavioral of shlftreg 1s Reset prevents the use slgnal r stdiloglcivector l downto O of SRUG begln process clk reset begln 1f reset I 139 then r lt S gt 39O39 elslf clk39event and c1k39139 r30 downto r31 lt r31 xor rO xor luput then 0 lt r31 downto 1 end 1f end process o p t lt ro end behavloral XST Report INFO HDL ADVISDR A 31151 shut regxster was found for sxgnsl 70 and 1 cells 15 snces emo39 e setreset 1091c woul 1 r ved E ms simple shut zegxster The majonty o sxmple pxpenne structures do no need to be setreset opexsuonsuy Gives us ihis hint to infer SRL16 selected Devlce 3s50pq20975 Number of 51 lCeS 19 out of 769 2 Number of shoe Flip Flops 32 out of 1536 2 Number of 4 mput LUTS 1 out of 1536 0 Number of 10s 4 Number of bonded 1013s 4 out of 124 3 Number of GCLKS 1 out f B 12 Synplify Pro Report Resource Usage Report for shiftreg Mapping to part xc3s50pq20875 Cell usage FDC 32 uses LUT3 1 use 10 ports 4 10 primitives 3 IBUF 2 uses OBUF 1 use Gives us this hint to BUFGP 1 use infer SRL16 lO Register bits 0 Register bits not including lOs 32 2 Global Clock Buffers l of 8 12 Mapping Summary Total LUTs l 0 n Synplify Pro Technology View l ia i g F E I l nj JunELF L ErE1E1r1 smear EE39E39E39EES39T39E39quot LlLi E 5539 72 VHDL code inferring SRL16 llbrary IEEE use IEEEVSTDiLOGIC71164Vall7 ent1ty shlftreg 1s port clk 1n STDiLOGIC reset 1 1n STDiLOGIC 1nput 1n STDiLOGIC output 1 out STDiLOGIC 7 end sn1ftreg arch1tecture behavloral of shlftreg 1 s1gna1 r stdiloglcivector31 downto 0 1n Only R31 isreset beg processc1kreset beg1n 1f reset39139 then r81lt390w elslf clk39event and c1k39139 then r30 downto O lt r31 downto 1 r31 lt r31 xor rO Xor luput end 1f end process o p t lt ro end behavloral XST Report III process1ng Un1t ltsh1ftreggt F ound Blrblt shlft reg1ster for s1gna1 ltr70gt Un1t lt shlftreg gt processed Dev1ce ut111zat1on summary selected Dev1ce 3s50pq20975 Number of Sllces 2 out of 768 0 Number or sl1ce Fllp Flops 2 out of 1536 0 Number of n ut LUTS 4 out of 1536 0 Nu used as 1091C 2 umb r used as sh1tt reglsters 2 Number or 10s 4 Number of bonded loss 4 out of 124 3 Number or GCLKS 1 out f s 12 2 slices instead of 18 Synplify Pro Report Resource Usage Report for shiftreg Mapping to part xc3s50pq20875 Cell usage FDC i use FDE 1 use GND 1 use VCC 1 use LUT3 1 use 10 orts 4 IO primitives 3 IBUF 2 uses OBUF 1 use BU39FGP 1 use SRL primitives SRLC16E 2 uses IO Register bits 0 Register bits not including IOs 2 0 Global Clock Buffers i of 8 12 Mapping Summary Total LUTs 3 0 Synplify Pro Technology View SRL16 shift registers Synplify Pro 0 Similar to inference of block RAM using Synplify Pro sometimes need to tell Synplify Pro you will use shift registers See the tips at 39 httpwww svnnlir ifv I riu Irifl l39ipsHints v1 3pdf If Synplify Pro is not extracting shift registers use the attributes synsrlstyle is quotnoexxtractflsrlquot OR synsrlstyle is quotselectsrlquot 6 this is Synplicity39s default flag Use the following to make sure it is uses flipflops not SRL synstyle is quotregistersquot VHDL code inferring SRL16 and forcing Synplify Pro to use SRL16 library IEEE use IEEEVSTDiLOGlcillszLall library Synplify entity sniftreg 15 port clk in STDiLOGIC reset 1 in STDiLOGIC input 1 in STDiLOGIC output 1 out STDiLOGIC 7 end shiftreg architecture behavioral of shiftreg 15 signal r stdiloglcivectoral downto o attribute synisrlstyls string attribute synisrlstyls of r signal is quotnoexxtractffisrin begl process clkreset begin 1f reset39139 then r31 lt O39 elslf clk39event and c1k39139 then r30 downto O lt r31 downto 1 r31 lt r31 xor ro xor input end 1f end process u p rO end behavloral 9 Project Specific Reducing Total Processing Time Throughput for Hash Function Fovnovmaisysi A Ouipmihmugh mpies ems WpicaW caicuiaie ouipui hioughpm pm Ms pevuuipuimpie woe haween wnsecuwe umpm Hash iunciion hioughpm is on uluwursuniyunceai dmevem end m uperaiiu Ouipmihmughpu depemcm in m Woesmimksanysersehecausem pmihmghpm mesqesize Fuvhash mm we mesure inpmihmughpuiiuv hbcis immihmugipm rsperirpmhh immencmemwmmmm rsperirpmhh cuxmsmmmmmumm Ex we hiSmiW mam chmmwmmungs as sii quotmnsi76m A ihmugipmm mm thsamd S steiiem bra emu imhiumuan Increasing Hash Function Throughput 0 To increase hash function throughput Increase bits per input block INVALID we cannot do this since input block size is fixed 0 Decrease number of cycles between input blocks VALID we can quotoverlapquot reading of input data and computation of hash function combine states when possible etc 0 Decrease clock period VALID design the hash function such that the critical path is as short as possible Example of Increasing Throughput To increase throughput want to minimize total processing time between input blocks total processing time clock cycles between input blocks clock period 0 Example Haiie hash Iunction which has 1 preprocess cycle 80 rounds 1 postprocess cycle 82 clock cyc es Pre rocess logic critical path lo ns ol lo ic Round logiccritical path 20 ns ol logiceach round Pos process logiccritical path 30 ns 0 ogic critical path minimum clock period 9 max t 0 20 30 30 ns Total processing time 82 clock cycles quot 30 ns 2460 ns Nowdividethe 39 39 39 39 39 39 39 39 quot L 39 Now N p 39g39N 39V 39 n u H 15nsr nthepostvl processing cycle Preprocess logic critical path 10 ns ol logic Round logiccritical path 20 ns ol logiceach round Postprocess logic critical path 17 ns ol logic critical path minimum clock period 9 max t 0 20 t7 20 ns Total processing time 83 clock cycles quot20 ns 1660 ns RESULT increased total number ol clock c cles b one clock BUT decreased criticalfath bylo ns 9 results in decrease ol total processing time y32 n thus throughput is increased by3 quotnl There is a tradeoll between number ol cycles and clock period Variables vs Signals Variable and Signal Assignments in Process Slalemenls s A ln a pmcess s1alemerll alarm assgnmem l exeomes lmmedla39elv lldu multlpleassgnmemsln me we ramble lheassgnmemsare all exeomed sequemally Illarable s nmvslhleumsdeulapmcess yum med massgn llln aslgralln hevslhle umslde mapmcess Slgnals ln apmcessasgralasslgnmem cexecmesunlyanoe allneend ollne recess ll yum u slgral assgnnenl multlple llmes Man 5 ml rwmmended empl ln De alrl cases men lne lasl slgrlal asslgrl menl chmnubgball wlll he asslgrled Asgnal svslhleumsdema mg Enan lrlpuls am umpm parts are held as sgnals nan are slglab whbhcan anlyhean lgM lard sue Masgnmem 31mm Olmm are swab whbhcan MW be an lei hardsde massgnmemshtemem Bit Counter using Variables Correct llbrary less use leeevstdiloglcills vall7 use leeev stdiloglciunslgnedvall use leeevstdiloglciarithvall entlty numblts 1s port x 1n stdiloglcivector downto 0 count out stdiloglcivectoru downto 0 end numblts archltecture behavlor of numblts 15 e 1n process x 77 count the number of blts 1n x equal to 1 Varlable tmp 1nteger begln t z o for 1 1n 0 to 2 loop 1 X1 39139 then tmp tmp 1 and 1f end loop count lt stdiloglcivectorconviunslgnedmmp2 end process end behavlor Incorrect Code using Signals llbrary less use leeevstdiloglcills vall7 useleeev stdiloglciunslgnedvall use le akstdiloglciarlthvall entlty numbltsls port x 1n gid loglcivectorw downto o count out std loglcivectoru downto 0 end numblts lt archltecture behavlor of numb rts 1s slgnal tmp 1nteger range 0 to 7 be 1 count the number of bfts1n x equal to l end loop count lt stdiloglcivectorconviunslgner tmp2 end process end behavlor Nbit NAND Entity LIBRARY ieee USE ieee stdilogicill64 all ENT ITY NANDD I S GENERIC 1391 INTEGER 8 PORT X IN STDiLOGIC7VECTORl TO 1391 Y OUT STDiLOGIC END NANDD Nbit NAND architecture using variables Correct ARCHITECTURE behaviorall OF NANDn IS BEGIN PROCESS X VARIABLE Tmp STDiLOGIC BEGIN Tmp Xl ANDibits FOR 1 IN 2 TO 11 LOOP Tmp Tmp AND x1 END LOOP ANDibitS Y lt NOT Tmp END PROCESS END 1 ehavioral I CTURE behavioralZ OF NANDn IS GNAL Tmp STDiLOGIC BEGIN Nbit NAND architecture using signals Incorrect 7amp3ng PRO CBS 8 x3 GIN Tmp lt Xl ANDibits FOR 1 IN 2TQ11 LOOP Tmp lt END LOOP AN Tmp AND x 1 FN Dibits Y lt NOT Tmp END PROCESS END 1 ehavioral 2 Nbit NAND architecture using signals Correct ARCHITECTURE dataflowl OE NANDD IS SIGNAL Tmp BEGI STDiLOGICiVECTORl TO 1391 Tmp1 lt Xl ANDibitS FOR 1 IN 2 TO 11 GENERATE Tmpi lt Tmpi1 AND X i END GENERATE ANDibitS Y lt NOT Tmpn END dataflowl Nbit NAND architecture using signals Correct W ARCHITECTURE dataflowZ OF NANDD IS SIGNAL Tmp STDiLOGICiV39ECTOYHI TO 1391 BEGIN Tmp lt OTHERS gt 39139 39039 WHENXTmp ELSE 39139 END dataflowZ Parity generator entity LIBRARY ieee USE ieeestdilogicill64all ENTITY oddParityLoop IS GENERIC Width INTEGER 8 PORT ad 1 in STDiLOGICiV39ECTOR Width 7 I DOWNTO 0 oddParity out STDiLOGIC END oddParityLoop Parity generator architecture using signals Correct ARCHITECTURE dataflow OF oddParityGen IS SIGNAL genxor STDiLOGIC7VECTORWidth DOWNTO 0 BEGIN genXor0 lt 39039 parTree FOR 1 IN 1 TO width GENERATE genXori lt genXori l XOR adi 7 1 END GENERATE oddParity lt genxorhridth END dataflow Parity generator architecture using variables ggrrggt ARCHITECTURE behavioral OF oddParityLoop IS BEGIN PROCESS ad VARIABLE loopXor STDiLOGIC BEGIN loopXor 39 O 39 FOR 1 IN 0 to width 1 LOOP loopXor loopXor XOR ad 1 oddParity lt loopxor END PROCESS END 1 ehavioral
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