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Computer Organization

by: Antonina Wuckert

Computer Organization ECE 445

Antonina Wuckert
GPA 3.94


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Class Notes
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This 3 page Class Notes was uploaded by Antonina Wuckert on Monday September 28, 2015. The Class Notes belongs to ECE 445 at George Mason University taught by Staff in Fall. Since its upload, it has received 5 views. For similar materials see /class/215042/ece-445-george-mason-university in ELECTRICAL AND COMPUTER ENGINEERING at George Mason University.

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Date Created: 09/28/15
ECE 445 Midterm Review Topics 39 Computer Functional Units Input Output Memory Arithmetic amp Logic Control 39 Assembly Language gt Register Transfer Notation RTN 39 Processor Registers MAR MDR PC IR SP AC LINK General Registers 39 Fetch and Execute Cycles 39 Bus Architectures SingleBus MultipleBus 39 System Software Compiler Assembler Text Editor Operating System 39 Performance Equation T N S R RISC vs CISC 39 Memory Organization Dimensions Operations Byte Addressability Timing 39 Instruction Types 1 2 3Address Transfer Arithmetic Logic Control 39 Instruction Sequencing and Branching Condition Codes 39 Shift Instructions Arithmetic Logical Shift Rotate 39 VHDL Slice Alias TriState Logic Array Loop 39 VHDL Models Counter Register Memory Bus Decoder Controller 39 Addressing Modes Immediate Register Absolute Indirect Index Relative Autoincrement Autodecrement 39 TwoPass Assembler Symbol Table Assembly Language gt Machine Instructions 39 Stack SP Push Pop 39 Subroutines Call Return Nesting Parameter Passing 39 Example Processors ARM Motorola 39 Control Unit Fetch Execute RTN gt Control Signals 39 Hardwired Control Control Step Counter IR Decoders Encoder Control Signal Matrix gt Control Signal Logic Functions 39 Microprogram Control Microinstructions Control Store uPC uAR uIR Encoding Horizontal Vertical BitORing ECE445F05RJH 1 Review Problems 1 Given the following initial register and memory contents determine the updated contents after the execution Of the following assembly language sequence all values in Hex MOVE 8NUM2 ADD R0NUM3 MOVE R1 R2 Memory Registers Initial Updated Initial Updated Label Address Contents Contents Address Contents Contents NUMl 0 9 2 3 45 0 0 0 0B NUM4 0A 0 0 0A 1 5 67 8 NUMZ 0B 0 0 0 8 2 0 0 0 9 NUM3 0C 000C 3 OCOC 2 Given the instruction format from Homework 2 with the following Operations OP Fn Assembly Language RTN 000 Move MOVE SRCDST DST lt SRC 001 Add ADD SRCDST DST lt SRC DST 101 Call Subroutine CALL TGT LINK lt PC PC lt TGT 110 Return Subroutine RTS PC lt LINK lll Halt HALT Halt lt l a For the assembly language program below complete the address symbol table and machine language encoding in binary and hex Addr ORIGIN 04 OP SRC DST Value HeX ST MOVE x1R1 CALL INC MOVE R2x1 HALT ORIGIN 0A INC MOVE 1R2 ADD R1 R2 RTS ORIGIN OF x1 DATAWORD 5 ECE445F05RJH 2 3 Given the single bus architecture below with the following control signals BUS A Pcilnc M AR PCan PciEniout SPilnc SPiDec SPiEniout IRiEniln IRiEniout MARiEniln MDRiEnilnl MDRiEnioutZ Write Read Op YiEniln ZiEniln ZiEniout MEM a Determine the RTN sequence and control signals necessary to implement the execute cycle for the stack instruction PUSH PC RTN Control 4 5 6 b Determine the RTN sequence and control signals necessary to implement the execute cycle for the stack instruction POP PC RTN Control ECE445F05RJH 3


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