Adv Microprocessor Appl
Adv Microprocessor Appl ECE 6050
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This 49 page Class Notes was uploaded by Lizeth Hegmann on Wednesday September 30, 2015. The Class Notes belongs to ECE 6050 at Western Michigan University taught by Janos Grantner in Fall. Since its upload, it has received 25 views. For similar materials see /class/216773/ece-6050-western-michigan-university in Engineering Electrical & Compu at Western Michigan University.
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Date Created: 09/30/15
MI SIGNAL TIMING TS J W 33002 inhibited m snooped access baht case m looped access WQFSI case Sn 39 39 o 7 s from 2 to 4 clocks to a nowaits e c If snoop hit occurs m negates two clocks later for a fourclock access best case If snoop hit occurs and cache is not available there is additional delay of 12 clocks m is asserted durin RESET RESET revents the 040 from snoo in the bus therefore MI is asserted to prevent an alternate master from accessin me e memo is unable to respond CODEC Interface This chapter describes the ARM7100 CODEC interface 121 CODEC Interface 122 g ARM7100 Data Sheet 121 ARM ARM DDI 0035A CODEC Interface 121 CODEC Interface The CODEC interface allows direct connection of a telephony type CODEC to ARM7100 It provides all the necessary clocks and timing pulses and performs serialisation or visa versa ofthe data stream to or from the CODEC The interface is full duplex and contains two separate data FlFOs Data is transferred to orfrom the CODEC at 64 k bits per second This is either written to or read from a 16byte FIFO The sound interrupt is generated every 8 bytes that are transferred FIFO half fullempty which means the interrupt rate is reduced from 8 KHz to 1 KHz with a latency of l mSec See OChapter 8 ARM7 7 00 Programmer s Model for details of the CODEC interface registers ARM7100 Data Sheet g ARM DDI 0035A ARM Synchronous Serial Interface This chapter describes the synchronous serial interface 131 Synchronous Serial Interface 132 g ARM7100 Data Sheet 131 ARM ARM DDI 0035A Synchronous Serial Interface 131 Synchronous Serial Interface The synchronous serial interface provides a four wire interface to serial peripheral devices such as ADCs that have a SPITM or MicrowireTM compatible interface The clock output frequency is programmable and only active during data transmissions to save power The output channel is fed by an 8bit shift register The input channel is captured by a 16bit shift register The clock and synchronisation pulses are activated by a write to the output shift register During transfers the SSIBUSY synchronous serial interface busy bit in the system status flags register is set when the transfer is complete Valid data is in the 16bit read shift register when the SSEOTI interrupt is asserted and the SSIBUSY bit is cleared See OChapter 8 ARM7700 Programmer s Modefor details of the synchronous serial interface registers ARM7100 Data Sheet g ARM DDI 0035A ARM LCD Controller This chapter describes the LCD controller 141 LCD Controller 142 ARM DDI 0035A ARM7100 Data Sheet 141 ARM LCD Controller 141 LCD Controller The LCD controller provides all the necessary control signals to interface directly to a single panel multiplexed LCD The panel size is programmable and can be any width line length from 16 to 1024 pixels in 16 pixel increments The number of lines is achieved by programming the total number of pixels in the LCD The total video frame size is prgrammable up to 128Kb equating to a theoretical maximum panel size of 640 x 409 or 1024 x 256 pixels The video RAM is mapped into the base ofthe main DRAM memory area which is fixed at the physical address 0x00000000 The number of bits per pixel is programmable from 1 to 4 The screen is mapped to the video buffer as one contiguous block where each horizontal line of pixels is mapped to a set of consecutive bytes or words in the video RAM The video buffer can be accessed word wide as pixel 0 is mapped to the LSB in the buffer ie the pixels are arranged in a littleendian manner The pixel bit rate and hence the LCD refresh rate can be programmed from 18432MHz to 576KHz The LCD controller is programmed by writing to the LCD control register LCDCON The LCD controller also contains two 32bit palette registers These allow any 4 2 or 1 bit pixel value to be mapped to any of the 15 grey scale values available CFgure 747 Video Buffer Mapping on page 143 shows the organisation ofthe video map for all combinations of bits per pixel ARM7100 Data Sheet g ARM DDI 0035A ARM LCD Controller Pixel l Pixel2 Pixels Pixel4 Grey scale Grey scale Bito Bit l BitZ Bits Bit4 BitS Bit6 Bit7 4Bits per pixel Pixel l Pixel2 Pixels Pixel4 Grey scale Grey scale Grey scale Grey scale A Bito Bit l BitZ Bits Bit4 BitS Bit6 Bit7 ZBits per pixel Pixel l Pixel2 Pixels Pixel4 Bito Bit l BitZ Bits Bit4 BitS Bit6 Bit7 iBit per pixel Figure 141 Video Buffer Mapping The refresh rate is not affected by the number of bits per pixel However the LCD controller fetches twice the data per refresh for 4 bits per pixel compared to 2 bits per pixel The main reason for reducing the number of bits per pixel is to reduce the power consumption ofthe DRAMs in bank 0 where the video buffer is mapped See OChapter 8 ARM 7 7 00 Programmer s Model for details of the LCD controller registers ARM7100 Data Sheet ARM ARM DDI 0035A LCD Controller ARM7100 Data Sheet ARM DDI 0035A UART and SiR Encoder This chapter the UART and the SiR Encoder 151 UART 152 152 SiR Encoder 152 g ARM7100 Data Sheet 151 ARM ARM DDI 0035A UART and SiR Encoder 151 UART ARM7100 contains a built in UART which offers similarfunctionality to National Semiconductor s160550 device It can support bit rates of up to 1152 K bps and contains two 16 byte FlFOs for receive and transmit Only three MODEM control input signals CTS DSR and DCD are supported The additional RI input MODEM control line is not supported Output Modem control lines such as RTS and DTR are not explicitly supported but can be implemented using bits from the general purpose lO ports in ARM7100 UART operation and line speed are controlled by the UART bit rate and line control register UBRLCR Three interrupts can be generated by the UART RX is asserted when the FIFO becomes half full or if the FIFO is non empty for longer than 3 character length times with no more characters being received TX is asserted ifthe FlFO buffer reaches half empty Modem status is generated if either of the modem status bits change state Framing and parity errors are detected as each byte is received and pushed onto the RX FlFO An overrun error generates an RX interrupt immediately All error bits can be read from the 11bit wide data register The FlFO can also be programmed to be one byte depth only like a conventional UART with double buffering 152 SiR Encoder ARM7100 also contains a erA Infrared data association SiR protocol encoder Optionally this encoder can be switched in to the TX and RX signals so they can be used to drive an infrared interface directly For more details on the erA SiR protocol see the appropriate document detailing this protocol standard If the SiR protocol encoder is enabled the UART TX line is held in the passive state and transitions ofthe modem status or the RX line will have no effect See OChapter 8 ARM7700 Programmer s Model for details of the UART and SiR encoder registers ARM7100 Data Sheet ARM DDI 0035A Timer Counters This chapter describes the timer counters and the real time clock 161 Timer Counters 162 162 Real Time Clock 162 g ARM7100 Data Sheet 161 ARM ARM DDI 0035A Timer Counters 161 Timer Counters Two timer counters are integrated in ARM7100 They are identical and are referred to as T01 and T02 T01 and T02 each have an associated 16 bit readwrite data register and some control bits in the system control register The timer counters can be read at any time and each counter is loaded with the value written to the data register immediately This value is decremented on the second clock edge to arrive after the write When the timer counter under flows ie reaches 0 it asserts its appropriate interrupt The timers can be read at any time The clock source and mode is selectable by writing to various bits in the system control register 0lock sources are 512KHz and 2KHz The timer counters can operate in two modes Free running mode Prescale mode Free running mode In free running mode the counter wraps round to OXFFFF when it under flows and continues counting down Any value written to T01 orT02 will be decremented on the second edge of the selected clock Prescale mode In prescale mode the value written to T01 or T02 is automatically reloaded when the counter under flows Any value written to T01 or T02 will be decremented on the second edge ofthe selected clock This mode can be used to produce a programmable frequency to drive the BUZ output or generate a periodic interrupt 162 Real Time Clock ARM7100 contains a 32bit real time clock RTO This can be written to and read from in the same way as the timer counters but it is 32 bits wide The RTO is always clocked at 1 Hz It also contains a 32bit output match register which can be programmed to generate an interrupt when the time in the RTO matches a specific time written to this register See OChapter 8 ARM7700 Programmer s Model for details of the timer counter registers 16 2 ARM7100 Data Sheet g ARM DDI 0035A ARM DC to DC Converters This chapter describes the two DC to DC Converter Interfaces 171 DC to DC Converter Interfaces 172 g ARM7100 Data Sheet 171 ARM ARM DDI 0035A DC to DC Converters 171 DC to DC Converter Interfaces ARM7100 has two programmable duty ratio 96 KHz clock outputs which are intended to be used as drives for DC to DC converters in the PSU subsystem These clocks are enabled by external input pins which would normally be connected to the output from comparators monitoring the DC to DC converter output The duty ratio and hence the converter on time can be programmed from 1 in 16 to 15 in 16 The sense ofthe DC to DC converter drive signal active HIGH or LOW is determined by latching the state ofthis drive signal during power on reset ie a pull up on the drive signal results in an active LOW drive output and vice versa This allows either positive or negative voltages to be generated by the DC to DC converter 172 ARM7100 Data Sheet g ARM DDI 0035A ARM Power Management and Reset This chapter describes the power management states supported by ARM7100 181 State Control 182 182 Reset 183 g ARM7100 Data Sheet 181 ARM ARM DDI 0035A Power Management and Reset 181 State Control ARM7100 supports three basic power states Standby This equates to a computer being switched off that is no display The main oscillator is shut down Idle The device is functioning and all oscillators are running but the processor clock is halted while it waits for an event such as a key press Operating ARM7100 is fully operational In the standby state all the system memory and state is maintained and the system time is kept up to date The main oscillator is disabled and the system is static except for the low power watch crystal 32 KHz oscillator and divider chain to the real time clock The RUN signal is driven LOW when in the standby state When first powered or reset by the nPOR not Power on reset signal the system is forced to the standby state This is known as a cold reset and is the only completely asynchronous reset to ARM7100 The transition to the operating state is caused by one of the following o a rising edge on the wakeup input signal a selected interrupt being asserted Once self refresh is enabled for the DRAMs any transition to the standby state is synchronised to DRAM refresh cycles and forces all the DRAMs into self refresh mode Once in the operating state the idle state is entered by writing to an internal memory location in ARM7100 Execution ofthe next instruction continues in the operating state if an interrupt becomes active A write to another internal memory location causes the transition from the operating state to the standby state The system can also be forced into the standby state by hardware ifthe nPWRFL or nURESET inputs are forced LOW In this case the transition is synchronised with DRAM cycles to avoid any glitches or short cycles The system only transitions to the operating state from the standby state if the nEXTPWR BATOK and nPWRFL inputs are HIGH This prevents the system from attempting to start when the power supply is inadequate CFgure 787 State diagram on page 18 3 shows a state diagram for ARM7100 ARM7100 Data Sheet g ARM DDI 0035A ARM 182 Reset Power Management and Reset Interrupt or rising wakeup Write to standby location power fail or user reset Interrupt Power V or User reset Write to idle location Figure 181 State diagram There are three asynchronous resets to ARM7100 these are nPOR nPWRFL and nURESET If any of these are active a system reset is generated internally this will clear all the internal registers in ARM7100 to zero except for the DRAM refresh period register and the real time clock data register which are only cleared by an active nPOR It will also reset the ARM710a and cause it to start execution at the reset vector when ARM7100 returns to the operating state The RUN signal is HIGH when AR M71 00 is in the operating or idle states and LOW when in the standby state E ARM ARM7100 Data Sheet ARM DDI 0035A Power Management and Reset ARM7100 Data Sheet ARM DDI 0035A Memory Map This chapter describes the ARM7100 memory map 191 Memory Map 192 g ARM7100 Data Sheet 191 ARM ARM DDI 0035A Memory Map 191 Memory Map The ARM7100 address space is allocated in the following way The lower 2 Gb ofthe address space is allocated to ROM and expansion s ace The upper 1 Gb of address space is allocated to DRAM The remaining 1 Gb less 4Kb for internal registers is not accessible in ARM7100 The MMU should be programmed to cause an abort exception in this space Internal peripheral devices are communicated and configured through a set of internal memory locations from hex address 8000000 to 8000FFFF CFgure 797 ARM7700 memory map on page 19 3 shows how the 4 Gb address range ofthe ARM710 processor is mapped in ARM7100 192 ARM7100 Data Sheet g ARM DDI 0035A ARM Memory Mop DRAM Bank 3 256 Mbytes F0000000 DRAM Bank 2 256 Mbytes E0000000 DRAM Bank 1 256 Mbytes 00000000 DRAM Bank 0 255 Mbytes 00000000 Not Used 1 Gbyte 80001000 Internal Registers 4 Kbytes 80000000 Expansion CS7 256 Mbytes 70000000 Expansion CS6 256 Mbytes 60000000 Expansion CS5 256 Mbytes 50000000 Expansion CS4 256 Mbytes 40000000 Expansion CS3 256 Mbytes 30000000 Expansion CS2 255 Mbytes 20000000 ROM Bank 1 CS1 256 Mbytes 10000000 ROM Bank 0 CSO 256 Mbytes 00000000 Figure 191 ARM7100 memory map ARM DDI 0035A ARM7100 Data Sheet 193 Memory Map ARM7100 Data Sheet ARM DDI 0035A DC and AC Parameters This chapter describes the DC and AC Parameters 201 Absolute Maximum Ratings 202 202 DC Operating Conditions 202 203 DC Characteristics 203 204 AC Characteristics 205 ARM ARM7100 Data Sheet ARM DDI 0035A DC and AC Parameters 201 Absolute Maximum Ratings 202 DC Operating Conditions Parameters Min Max Unit DC Supply voltage 05 6 V DC input output voltage 05 Vdd 05 V DC input current 20 20 mA Storage temperature 40 125 C Lead temperature 300 C Table 201 DC maximum ratings Parameters Min Max Unit DC Supply voltage 27 55 V DC input output voltage 0 Vdd V DC input current 15 15 mA Operating temperature 0 70 C Table 202 DC operating conditions ARM7100 Data Sheet g ARM DDI 0035A ARM DC and AC Parameters 203 DC Characteristics All characteristics are specified at Vdd 30 to 36 volts and Vss 0 volts over an operating temperature of 0 C to 70 C Symbol Parameter Min Max Unit Conditions VIH CMOS input 07 x Vdd Vdd 03 V high voltage VlL CMOS input 03 02 x Vdd V low voltage VT Schmit t trigger 152 226 V positive going threshold VT Schmit t trigger 072 129 V negative going threshold Vhst Schmit t trigger 064 113 V VIL to VIH hysteresis VOH CMOS output Vdd 01 V IOH 08 mA high voltage Standard drive output Vdd 10 V IOH 4 mA Medium drive output Vdd 10 V IOH 6 mA High drive output Vdd 10 V IOH 12 mA Very high drive output Vdd 10 V IOH 24 mA VOL CMOS output 01 V lOL 08 mA low voltage Standard drive output 05 V IOL 4 mA Medium drive output 05 V IOL 6 mA High drive output 05 V IOL 12 mA Very high drive output 05 V IOL 24 mA IIN Input leakage 10 10 uA VIN VDD or GND current IOZ Output Tristate leak 10 10 uA VOUT VDD or GND age current CIN Input capacitance 5 pF COUT Output capacitance 5 pF CIO Transceiver 5 pF capacitance Table 203 DC characteristics E ARM ARM7100 Data Sheet ARM DDI 0035A 203 DC and AC Parameters Symbol Parameter Min Max Unit Conditions IDDStanup Startup current 100 uA Initial 100 mSec from consumption power up 32 KHZ oscillator not stable POR signal at VIL all other O static VIH VDD r 01V VIL GND 01V IDDStandby Standby current 50 uA Just 32 KHZ oscillator I consumption running all other O static VIH VDD r 01V VIL GND r 01V IDDidIe Idle current 5 mA Both oscillators running CPU consumption static LCD refresh active VIH VDD r 01V VIL GND r 01V IDDoperating Operating current con 30 mA All system active running typi sumption cal program VDDstandby Standby supply voltage 22 V Minimum standby voltage for state retention and RTC operation only Table 203 DC characteristics 204 ARM7100 Data Sheet ARM DDI 0035A ARM E DC and AC Parameters 204 AC Characteristics All characteristics are specified at Vdd 30 to 36 volts and Vss 0 volts over an operating temperature of 0 C to 70 C Symbol Parameter Min Max Unit T1 Falling C8 to data bus HiZ 0 25 n8 T2 Address change to valid write data 0 35 n8 T3 DATA in to falling EXPCLK setuptime 18 n8 T4 DATA in to falling EXPCLK hold time 0 n8 T5 EXPRDY to falling EXPCLK setup time 18 n8 T6 Falling EXPCLK to EXPRDY hold time 0 50 n8 T7 Rising nMWE to data nvalid hold time 5 n8 T8 Data valid to falling nMWE setup time 15 n8 T9 Row address to falling nCAS setup time 18 n8 T10 Falling nRAS to row address hold time 25 n8 T11 Column address to falling nCAS setup time 2 n8 T12 Falling nCAS to column address hold time 25 n8 T13 Write data valid to falling nCAS setup time 2 n8 T14 Write data valid from falling nCAS hold time 50 n8 T15 LCD CL2 low time 80 3475 nS T16 LCD CL2 high time 80 3475 nS T17 LCD rising CL2 to rising CL1 delay 0 25 ns 18 LCD falling CL1 to rising CL21 80 3475 nS T19 LCD CL1 high time 80 3475 nS T20 LCD falling CL1 to falling CL2 200 6950 nS T21 LCD falling CL1 to frm toggle 300 10425 nS T22 LCD falling CL1 to m toggle 10 20 n8 T23 LCD rising CL2 to display data change 10 20 n8 Table 204 AC Characteristics ARM7100 Data Sheet ARM DDI 0035A 205 DC and AC Parameters Symbol Parameter Min Max Unit Textrd zero wait state memory read access time 70 n8 Texwr zero wait state memory write access time 70 n8 Trc DRAM cycle time 150 n8 Trac Access time from RAS 70 n8 Trp RAS precharge time 70 n8 Tcas CAS pulse width 20 n8 Tcp CAS precharge in page mode 12 n8 Tpc Page mode cycle time 45 n8 Tcsa CAS setup time 15 n8 Tras RAS pulse width 80 n8 Table 205 System memory device parameter requirements 206 ARM7100 Data Sheet ARM DDI 0035A ARM E DC and AC Parameters EXPCLK ncqam Cain nMOE Aprm WORD D310 bus held T3 EXPRDY Ts Figure 201 Expansion and ROM read timing Notes x Texrd 70nS for maximum wait states and a main oscillator frequency of 18432 MHz This time can be extended by integer multiples ofthe clock period 54nS by either driving EXPRDY LOW or by by programming a number of wait states EXPRDY is sampled on the falling edge of EXPCLK before the data transfer lf LOW at this point the transfer is delayed by one clock period where EXPRDY is sampled again EXPCLK need not be referenced when driving EXPRDY but is shown for clarity 2 Consecutive reads with sequential access enabled are identical except that the sequential access wait state field is used to determine the number of wait states ARM7100 Data Sheet 207 ARM ARM DDI 0035A DC and AC Parameters EXPCLK nCS30 CS74 nMWE A270 WORD exwr D310 bus held me data EXP R DY Ts Figure 202 Expansion and ROM write timing Notes 1 Texwr 70nS max for zero wait states This time can be extended by integer multiples ofthe clock period 54 n8 by either driving EXPRDY LOW or by programming a number of wait states EXPRDY is sampled on the falling edge of EXPCLK before the data tansfer lf LOW at this point the transfer is delayed by one clock period where EXPRDY is sampled again EXPCLK need not be referenced when driving EXPRDY but is shown for clarity 2 Consecutive writes with sequential access enabled are identical except that the sequential access wait state filed is used to determine the number of wait states 3 Zero wait states for sequential writes is not supported one state will automatically be added 208 ARM7100 Data Sheet g ARM DDI 0035A ARM DC and AC Parameters DRA1201 X row X col X me Keen Xcm X l T T9Jloa Hi le nRAS30 Tras Trc Trpg nCAS30 TeasA Tpc I C D310 D nMOE nMWE U WORD WRITE EEK Figure 203 DRAM read cycles Notes 1 Trc Read cycle time 150nS max Trac Read access time from RAS 70nS max Trp RAS precharge time 70nS max Tcas CAS pulse width 20nS max Tcp CAS precharge in page mode 12nS max Tpc page mode cycle time 45nS min at max Word reads shown for byte reads only one of CAS30 will be active CAS0 for byte 0 etc ARM7100 Data Sheet 209 ARM ARM DDI 0035A DC and AC Parameters DRA120 nRAS30 nCAS30 D31 0 Data out Data out 2 Data out n nMOE nMWE U WORD U WRITE U Figure 204 DRAM write cycles Notes 1 Trc Write cycle time 150nS max at MCLK 18432MH2 Trac Write access time from RAS 70nS max at MCLK 18432MH2 Trp RAS precharge time 70nS max at MCLK 18432MH2 Tcas CAS pulse width 20nS max at MCLK 18432MH2 Tcp CAS precharge in page mode 66nS max at MCLK 18432MH2 Tpc page mode cycle time 45nS max at MCLK 18432MH2 ICDU ILQM Word writes shown for byte writes only one off CAS30 will be active CAS0 for byte 0 etc 2010 ARM7100 Data Sheet g ARM DDI 0035A ARM DC and AC Parameters i TVacc 39i DRA120 X row Xcoio ch Xcm Xcois i X Trp nCAS30 Tcas GP Tpc nMOE nMWE Figure 205 Video quad word read Notes 1 Timings are the same as page mode word reads 2 Tvacc video access cycle time 326nS at MCLK 18432 MHz E ARM ARM7100 Data Sheet 2041 ARM DDI 0035A DC and AC Parameters DRA120 X held x row X col X nRAS30 4j 7Tras nCAS30 T Tcsaal rc D310 X Held nMOE nMWE Figure 206 DRAM CAS before RAS refresh cycle Notes 1 Tcsa CAS setup time 25nS min at MCLK 18432MH2 Tras RAS pulse width 70nS min at MCLK 18432MH2 Trc Cycle time 150nS min at MCLK 18432MH2 60k When DRAM s are placed in self refresh entering standby the same timings apply except that Tras is extended indefinitely 2012 ARM7100 Data Sheet g ARM DDI 0035A ARM DC and AC Parameters DD30 Figure 207 LCD controller timing Notes 1 CFgure 207 LCD controler timing shows the end of a line 2 If FRM is HIGH during the CL1 pulse this marks the first line in the display 3 CL2 LOW time is doubled during the CL1 high pulse ARM7100 Data Sheet 2013 ARM ARM DDI 0035A DC and AC Parameters ARM DDI 0035A 2014 ARM7100 Data Sheet g ARM Physical Details This chapter describes the physical details of the AR M71 00 211 Pin diagrams for the ARM7100 212 g ARM7100 Data Sheet 211 ARM ARM DDI 0035A Physical Details 211 Pin diagrams for the ARM7100 The following two diagrams illustrate the top and side views of the ARM7100 All dimensions are given in millimetres D D1 Pin 156 Pin 105 LG LU 3 C x E E a ARM7100 m l39l1 Pin 1 identification 8 13 3 l c Q a 0 L Pin 1 Pin 52 Figure 211 Pin diagram for the ARM7100 212 ARM7100 Data Sheet g ARM DDI 0035A ARM Physical Details H D l l N lt I 2 i L J H T Figure 212 Side View of ARM71 00 chip Symbol Description Min Max A Package thckness plus stand off 14 16 A1 Stand off 005 015 A2 Package thickness 135 145 D Lead tip to Lead tip X 296 304 D1 Package body dimension X 278 282 E Lead tip to Lead tip Y 296 304 E1 Package body dimension Y 278 282 L Foot Length 045 075 L1 Total lead length 1 00 BSC e Lead pitch 1 00 BSC B Lead width with plating 017 027 Table 211 Chip dimensions Notes 1 Controlling dimension is mm 2 Dimensions D1 and E1 do not include mold protrusion which is 025mm 0010 inch 3 Lead frame material is copper 4 Lead finish is solder plate 5 Pin 1 identification may be either ink dot or dimple 6 0008 inch Package top dimensions can be smaller than bottom dimensions by 020mm ARM7100 Data Sheet ARM ARM DDI 0035A 21 3 Physical Details ARM7100 Data Sheet ARM DDI 0035A Pinout This chapter describes the ARM7100 pinout 221 Pin details 222 ARM DDI 0035A ARM7100 Data Sheet 221 ARM Pinoul 221 Pin details The following table gives the signal name for each ofthe 208 pins ofthe ARM7100 Pin number Signal name Pin number Signal name 1 CS5 27 PBZ 2 CS6 28 PB1 3 Gem 29 PBO 4 VDD 30 PE3 5 vss 31 PE2 6 EXPCLK 32 VDD 7 WORD 33 V88 8 WRITE 34 PA7 9 RUN 35 PA6 10 EXPRDY 36 PA5 1 1 PC7 37 PA4 1 2 PC6 38 PA3 13 PC5 39 PA2 1 4 PC4 40 PA1 1 5 PC3 41 PAO 16 PC2 42 LEDDRV 17 Pom 43 TXD 18 PCO 44 PH DIN 19 VDD 45 CTS 20 V88 46 RXD 21 V88 47 DCD 22 PB7 48 DSR 23 PB6 49 vss 24 PB5 50 RTCO UT 25 PB4 51 RTCI N 26 PB3 52 VDD Table 221 Pin numbers and signal names ARM7100 Data Sheet ARM DDI 0035A Pinout Pin number Signal name Pin number Signal name 53 nTEST1 82 DRIVEO 54 nTESTO 83 ADCCLK 55 EINT3 84 ADCOUT 56 nEINT2 85 SMPLCK 57 nEI NT1 86 FB1 58 nEXTFIQ 87 FBO 59 PE1 88 CO L7 60 PE0 89 CO L6 61 PD7 90 CO L5 62 PD6 91 CO L4 63 PD5 92 CO L3 64 PD4 93 CO L2 65 VDD 94 VDD 66 V88 95 V88 67 PD3 96 COL1 68 PD2 97 CO L0 69 PD1 98 BUZ 70 PD0 99 D31 71 PCMIN 100 D30 72 PCMCK 101 D29 73 PCMOUT 102 D28 74 PCMSYNC 103 A27DRA0 75 ADCIN 104 D27 76 nADCCS 105 A26DRA1 77 V88 1 06 D26 78 VDD 107 A25DRA2 79 V88 1 08 D25 80 VDD 109 A24DRA3 81 DRIVE1 1 1 0 VDD Table 221 Pin numbers and signal names Continued ARM7100 Data Sheet 223 ARM ARM DDI 0035A Pinout Pin number Signal name Pin number Signal name 1 1 1 VSS 140 A1 1 1 1 2 D24 1 41 VDD 113 A23DRA4 142 vss 114 D23 143 D11 115 A22DRA5 144 A10 116 D22 145 D10 117 A21DRA6 146 A9 118 D21 147 D9 119 A20DRA7 148 A8 120 D20 149 D8 121 A19DRA8 150 A7 122 D19 151 D7 123 A18DRA9 152 nBATCHG 124 D18 153 nEXTPWR 1 25 VDD 1 54 BATOK 1 26 V88 1 55 n PO R 127 VSS 156 MEDCHG 128 A17DRA10 157 VDD 129 D17 158 MOSCIN 130 A16DRA11 159 MOSCOUT 1 31 D1 6 1 60 V88 132 A15DRA12 161 nURESET 133 D15 162 WAKEUP 134 A14 163 nPWRFL 135 D14 164 A6 136 A13 165 D6 137 D13 166 A5 138 A12 167 D5 1 39 D1 2 1 68 VDD Table 221 Pin numbers and signal names Continued ARM7100 Data Sheet ARM DDI 0035A ARM E Pinout Pin number Signal name Pin number Signal name 169 VSS 189 DD2 170 A4 190 DD1 171 D4 191 DDO 172 A3 192 nRAS3 173 D3 193 nRAS2 174 A2 194 nRAS1 175 D2 195 nRAS0 176 A1 196 nCAS3 177 D1 197 nCAS2 178 A0 198 VDD 179 D0 199 VSS 180 VSS 200 nCAS1 181 VDD 201 nCAS0 182 VSS 202 nMWE 183 VDD 203 nMOE 184 CL2 204 nCS0 185 CL1 205 nCS1 186 FRM 206 nCS2 187 M 207 nCS3 188 DD3 208 CS4 Table 221 Pin numbers and signal names Continued ARM7100 Data Sheet 225 ARM ARM DDI 0035A Pinout ARM7100 Data Sheet ARM DDI 0035A Index A Abort operating mode 44 Access faults checking 715 Address translation 74 B Backward compatibility configuration bits 43 block diagram ARM704 33 Branch instructions 54 C CDP instruction 539 compilers 32 Condition codes 53 Configuration bits for backward compatibility 43 Configuration settings register 42 Control register big endian format 42 little endian format 42 Coprocessor data operations 539 Coprocessor instructions 538 CPSR flags 57 D Data processing instructions 56 DC parameters 201 Domain access control 714 Domain access control register 73 E Examples instruction set 548 Exceptions 47 abort 48 FIQ 47 IRQ 48 priorities 410 F Fault address register 73 713 Fault checking 715 Fault status register 73 713 FIQ exception 47 FIQ operating mode 44 g ARM7100 Data Sheet ARM ARM DDI 0035A Indexi ARM7IOO IDC cacheable bit 62 disable 63 enable 63 interaction with MMU and write buffer 718 operation 62 readIockwrite 63 reset 63 validity 62 instruction set ARM704 32 Instruction set examples loading a halfword 551 loading a word from an unknown alignment 5 50 multiply by constant 549 pseudo random binary sequence gneerator 5 49 using conditional instructions 548 Instruction set summary 52 Instruction speed summary 552 Internal coprocessor instructions 411 IRQ exception 48 IRQ operating mode 44 L LDC instruction 541 LDM instruction 527 LDR instruction 521 M MCR instruction 544 MLA instruction 519 MMU interaction with IDC and write buffer 718 MRC instruction 544 MRS instruction 515 MSR instruction 515 MUL instruction 519 0 Operating modes selecting 44 P Parameters DC 201 physical details 212 pin details 222 pin diagrams 212 R Register confidurations 42 Registers 44 411 MMU 73 3 Shifts 59 Signal descriptions 22 Software interrupt instruction 49 536 STC instruction 541 STM instruction 527 STR instruction 521 Supervisor operating mode 44 SWP instruction 534 T Translating references 75 Translation table base register 73 U Undefined instruction 547 Undefined instruction trap 49 Undefined operating mode 44 User operating mode 44 W Write buffer interaction with MMU and IDC 718 Indexii ARM DDI 0010E ARM7100 Data Sheet g
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