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Adv Microprocessor Appl

by: Lizeth Hegmann

Adv Microprocessor Appl ECE 6050

Lizeth Hegmann
GPA 3.61

Janos Grantner

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Janos Grantner
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This 34 page Class Notes was uploaded by Lizeth Hegmann on Wednesday September 30, 2015. The Class Notes belongs to ECE 6050 at Western Michigan University taught by Janos Grantner in Fall. Since its upload, it has received 25 views. For similar materials see /class/216773/ece-6050-western-michigan-university in Engineering Electrical & Compu at Western Michigan University.

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Date Created: 09/30/15
ARM 7100 Preliminary Data Sheet Document Number ARM DDI 0035A Issued January 1996 Copyright Advanced RISC Machines Ltd ARM 1996 All rights reserved I POWERED ARM Proprietary Notice ARM and the ARM Powered logo are trademarks of Advanced RISC Machines Ltd SPI is a registered trademark of Motorola Microwire is a registered trademark of National Semiconductor Neither the whole nor any part of the information contained in or the product described in this datasheet may be adapted or reproduced in any material form except with the prior written permission of the copyright holder The product described in this datasheet is subject to continuous developments and improvements All particulars of the product and its use contained in this datasheet are given by ARM in good faith However all warranties implied or expressed including but not limited to implied warranties or merchantability or fitness for purpose are excluded This datasheet is intended only to assist the reader in the use of the product ARM Ltd shall not be liable for any loss or damage arising from the use of any information in this datasheet or any error or omission in such information or any incorrect use of the product Change Log Issue Date By Change 01 Jan 95 AW Created 02 Feb 95 AW Changes after an initial preliminary review Changes to reflect updated specification A draft l Dec 95 AP Changes to reflect updated specification A Jan 96 AP Minor edits addition of timing diagrams Advanced RISC Machines Preface The ARM7100 is a high integration microcontroller particularly wellsuited for PDAs smart mobile phones handheld games portable instruments and similar applications Built around the ARM710 microprocessor the ARM7100 integrates LCD control glueless DRAM interface UART with infrared SIR protocol support and the other peripherals required for handheld computing applications In normal operation at 184MHz at 33V the ARM7100 consumes an extremely low 70mW and in standby less than 40uW which gives excellent battery performance System power is minimized by the ability to use selfrefresh DRAM when in standby ARM7100 was implemented using a modular design methodology and the AMBA internal bus architecture The ARM7100 is the ideal starting point from which to consider further ASSP devices for volume OEM applications Applications High integration and low power consumption makes the ARM7100 ideal for batterypowered portable computing applications 0 PDAs Smart Mobile phones Handheld games Electronic books and organizers Handheld instruments and data collection devices High specification pagers 0 Mobile epos terminals Its high performance and low cost features make the ARM7100 also suitable for 0 Office automation photocopiers faxes 0 Automotive user consoles Features 0 32bit ARM710 RISC cached processor 0 8Kb cache memory management unit and write buffer to deliver strong performance with inexpensive memory 0 Very low chip and system power consumption two low power modes and advanced power management 0 Glueless DRAM interface which supports selfrefresh DRAM to further reduce system power consumption 3072Mb total physical address range Support for 8 bit 16bit or 32bit wide ROMSRAM devices 36 bits of general purpose lO Flexible LCD controller with DMA support Full duplex UART with two 16byte FlFOs and erA industry standard infrared protocol support 0 Synchronous serial interface supporting multiple protocols for peripheral expansion o Telephony CODEC interface 0 Other peripherals include timercounters realtime clock DC DC converter interface and onchip clock generators Prefaceii ARM7100 Data Sheet g ARM DDI 0035A ARM Contents 1 Introduction 11 Introduction 12 12 System Description 12 13 Block Diagram 13 14 CPU Core 14 15 Datasheet Notation 14 2 Signal Description 21 21 Signal Descriptions 22 3 The ARM Processor Macrocell 31 Introduction 32 32 Instruction set 32 33 Memory Interface 33 34 Clocking 33 35 ARM Processor Block Diagram 33 4 The ARM Processor Programmer39s Model 41 4 1 Introduction 42 4 2 Register Configuration 42 43 Operating Mode Selection 44 44 Registers 44 4 5 Exceptions 47 4 6 Configuration Control Registers 411 47 ese 416 5 ARM Processor Instruction Set 51 51 Instruction Set Summary 52 52 The Condition Field 53 53 Branch and Branch with link B BL 54 54 Data Processing 56 55 PSR Transfer MRS MSR 515 56 Multiply and MultiplyAccumulate MUL MLA 519 57 Single Data Transfer LDR STR 521 Contentsi g ARM7100 Data Sheet ARM ARM DDI 0035A Contents 6 7 58 59 510 511 512 513 514 515 516 517 Block Data Transfer LDM STM Single Data Swap SWP Software Interrupt SWI Coprocessor Instructions Coprocessor data operations CDP Coprocessor Data Transfers LDC STC Coprocessor Register Transfers M RC MCR Undefined Instruction Instruction Set Examples Instruction Speed Summary Cache Write Buffer and Coprocessors ARM Pro 710 711 712 l x 0 Instruction and Data Cache ReadIockwrite IDC EnableDisable and Reset Write Buffer Coprocessors cessor MMU Introduction MMU Program Accessible Registers Address Translation Translation Process Translating Section References Translating Small Page References Translating Large Page References MMU Faults and CPU Aborts 712 Fault Address and Fault Status Registers FAR and FSR713 4 Domain Access Control Fault Checking Sequence Interaction ofthe MMU IDC and Write Buffer Effect of Reset ARM7100 Programmer s Model 81 82 83 Interrupt 91 Introduction Summary of Registers Register Descriptions Controller Interrupt Controller The Expansion and ROM Interface 101 The Expansion and ROM Interface DRAM controller 111 DRAM Controller CODEC Interface 121 CODEC Interface Synchronous Serial Interface 131 LCD Con 141 Synchronous Serial Interface troller LCD Controller Co ntentsii ARM7100 Data Sheet ARM DDI 0035A Contents E ARM 15 UART and SiR Encoder 151 151 UART 152 152 SiR Encoder 152 16 Timer Counters 161 161 Timer Counters 162 162 Real Time Clock 162 17 DC to DC Converters 171 171 DC to DC Converter Interfaces 172 18 Power Management and Reset 181 181 State Control 18 2 182 Reset 18 3 19 Memory Map 191 191 Memory Map 192 20 DC and AC Parameters 201 201 Absolute Maximum Ratings 202 202 DC Operating Conditions 202 203 DC Characteristics 203 204 AC Characteristics 205 21 Physical Details 211 211 Pin diagrams for the ARM7100 212 22 Pinout 221 221 Pin details 222 ARM7100 Data Sheet Contentsiii ARM DDI 0035A Contents Contents iv ARM7100 Data Sheet g ARM ARM DDI 0035A Introduciion This chapter provides an introduction to the ARM7100 11 Introduction 12 12 System Description 12 13 Block Diagram 13 14 CPU Core 14 15 Datasheet Notation 14 g ARM7100 Data Sheet ARM ARM DDI 0035A Inlroduclion 11 Introduction The ARM7100 is a highly integrated single chip microcontroller for PDA products using modular design techniques based on the Advanced Microcontroller Bus Architecture AMBA to simplify design and test while optimizing for lowest power 70mVV and low die size The ARM7100 delivers 184 MIPS peak at 33V and contains an embedded ARM710a core including 8kByte cache and MMU with ARM library peripherals such as an LCD controller UART and CODEC interface 12 System Description ARM7100 is based around the ARM710a processor core The principle functional blocks in ARM7100 are ARM7 CPU core memory management unit 8Kb of unified instruction and data cache interrupt and fast interrupt controller expansion and ROM interface giving 8 X 256 Mb expansion segments with independent wait state control DRAM controller supporting fast page mode and self refresh in standby 36 bits of general purpose peripheral lO telephony CODEC interface with 16 byte FlFOs programmable 4bit per pixel LCD controller full duplex UART and two 16byte FlFOs plus logic to implement the erA SIR protocol capable of speeds up to 115K bits per second two 16 bit general purpose counter timers A 32bit real time clock and comparator two DC to DC converter interfaces system state control and power management synchronous serial interface for Microwire or SPI peripherals such as ADCs pin test and device isolation logic external tracing support for debug a main 368MHz oscillator with PLLto create system frequency of 18432MHz a low power 32768 KHz oscillator CFgure 77 ARM7700 block diagram on page 13 shows a simplified block diagram of ARM7100 12 ARM7100 Data Sheet g ARM DDI 0035A ARM 13 Block Diagram Inlroduclion 18 432 MHz PLL 3 68 KHz Os lator Interrupt Controller BATOK nEXTPWR Power nPWRFL Management nBATCHG PAPB PCPD BUZ com 7 PSU Synchronous 8839 Serial lO EINTO2 nEXTFlQ MEDCHG t ARM7 UP core 8 Kb Cache Internal databus DODS l nPOR RUN State RESET Control WAKEUP EXPCLK ROMExpansion WORD Control CSO7 EXPRDY WRITE DRAM Controller MMU A027 DRAODRA12 FRO LCD LCD Drive Controller FRC RTC LED and photodiode UART CODEC CODEC lnte rface RS232 interface Figure 11 ARM7100 block diagram E E ARM DDI 0035A ARM7100 Data Sheet Inlroduclion 14 CPU Core The processor macrocell contains the ARM7 processor core with 8Kb of cache memory management unit and write buffer See OChapter 3 The ARM Processor Macrocel for a description ofthe ARM processor macrocell 15 Datasheet Notation 0X marks a Hexadecimal quantity BOLD external signals are shown in bold capital letters binary where it is not clear that a quantity is binary it is followed by the word bina 14 ARM7100 Data Sheet g ARM DDI 0035A ARM Signal Descriplion This chapter gives the name type and relevant details of each of the ARM7100 signals 21 Signal Descriptions 22 g ARM7100 Data Sheet 21 ARM ARM DDI 0035A Signal Descriplion 21 Signal Descriptions Name Type Description D031 IO 32bit system data bus for DRAM ROM and memory mapped expansion A014 O Least significant 15 bits of system byte address during ROM and expansion cycles A15 I DRA12 O 13bit multiplexed DRAM word address during DRAM cycles or address bits A27 I DRAO 16 to 27 of system byte address during ROM and expansion cycles nRAS03 O DRAM RAS outputs to DRAM banks 0 to 3 nCAS03 OM DRAM CAS outputs for bytes 0 to 3 within 32bit word nMOE O DRAM ROM and expansion output enable nMWE O DRAM ROM and expansion write enable nCS03 O Expansion channel O strobes Active LOW SRAM like chip selects for expansion CS47 O Expansion channel O strobes Active HIGH SRAM like chip selects for expansion EXPRDY Expansion channel ready External devices drive this LOWto extend expansion bus cycles WRITE O Transfer direction LOW during reads HIGH during writes from ARM7100 WORD O Word access enable Driven HIGH during word wide cycles LOW during byte wide cycles EXPCLK O Expansion clock output Clock output at the same phase and speed as the CPU clock Free running or active only during expansion IO cycles MEDCHG The MEDCHG input is intended to be driven by a system sensor indicating that a device connected to an external system port has been physically removed or inserted It can cause an interrupt to allow software to take appropriate action nEXTFlQ External active LOW fast interrupt request input EINT3 External active HIGH interrupt request input nElNT12 Two general purpose active LOW interrupt inputs nPWRFL Power fail input Active LOW deglitched input to force system into the standby state automatically BATOK Main battery OK input Falling edge generates a FIQ a low level while in standby inhibits system start up Deglitched input Table 21 Signal descriptions 22 ARM7100 Data Sheet g ARM DDI 0035A ARM Signal Descriplion Name Type Description nEXTPWR External power sense Must be driven LOW if the system is powered by external source nBATCHG New battery sense Should be driven LOW if battery voltage falls below the nobattery threshold nPOR S Poweron reset input Active LOW input completely resets the system RUN O System active output HIGH when system is active or idle LOW while in the standby state WAKEUP S Wake up input signal Rising edge forces system into operating state nURESET S User reset input Active LOW input PCMCK O CODEC clock output PCMSYNC O CODEC synchronisation pulse output PCMOUT O CODEC serial data output PCMIN CODEC serial data input ADCCLK O Synchronous serial interface ADC clock output SMPLCK O Synchronous serial interface ADC sample clock can be disabled nADCCS O Synchronous serial interface ADC active LOW chip select and synchronisation output ADCOUT O Synchronous serial interface ADC serial data output ADCIN Synchronous serial interface ADC serial data input LEDDRV O Infrared LED drive output PHDIN Infrared photo diode input TXD O RS232 Tx output RXD RS232 Rx input DSR RS232 DSR input DCD RS232 DCD input CTS RS232 CTS input DD03 O LCD display data CL1 O LCD line clock CL2 O LCD pixel clock FRM O LCD frame synchronisation pulse output M O LCD AC bias drive Table 21 Signal descriptions Continued ARM7100 Data Sheet 23 E ARM ARM DDI 0035A Signal Descriplion Name Type Description COL07 0 Keyboard column drives BUZ O This output is driven by direct software control or can be driven by a frequency generated by timer counter interrupts It is designed to drive a buzzer PA07 IO Port A O PB07 IO Port B O PC07 IO Port C O PD03 IO Port D O PD47 IOH Port D high drive O PE03 IO Port E O DRIVE01 IOVH DC to DC drive outputs FB01 DC to DC feedback inputs nTEST01 IP Test mode select inputs always HIGH for normal operation MOSCINIOUT Main 36864MHZ oscillator for 18432 MHz PLL RTCINIOUT Real time clock 32768 KHZ oscillator Table 21 Signal descriptions Continued Key to signal types and drive capabilities IOVH IO IOH Input Schmitt input Input with internal pullup Standard drive output Medium drive output Very high drive O Standard drive O High drive O See 0203 DC Characteristics on page 203 for more details ARM7100 Data Sheet g ARM DDl 0035A ARM The ARM Processor Mocrocell This chapter introduces the ARM processor 32bit microprocessor macroceII 31 Introduction 32 32 Instruction set 32 33 Memory Interface 33 34 Clocking 33 35 ARM Processor Block Diagram 33 g ARM7100 Data Sheet ARM ARM DDI 0035A The ARM Processor Mocrocell 31 Introduction ARM7100 contains a 32bit RISC ARM710a processor macrocell It has a 8Kb cache write buffer and a memory management unit M MU The ARM processor macrocell offers highlevel RISC performance yet its fully static design ensures minimal power consumption This makes it ideal for incorporation into ARM7100 This part ofthe datasheet describes the features ofthe ARM processor macrocell which are available to the user in its embedded state within ARM7100 It is not intended that this should be used as a standalone datasheet for a separate ARM processor macrocell 311 Architecture The ARM processor architecture is based on Reduced Instruction Set Computer RISC principles and the instruction set and related decode mechanism are greatly simplified compared with microprogrammed Complex Instruction Set Computers CISC The mixed data and instruction cache together with the write buffer substantially raise the average execution speed and reduce the average amount of memory bandwidth required by the processor The MMU supports a conventional twolevel pagetable structure and a number of extensions which make it ideal for embedded control UNIX and Object Oriented systems 32 Instruction set The instruction set comprises ten basic instruction types two ofthese make use ofthe onchip arithmetic logic unit barrel shifter and multiplierto perform highspeed operations on the data in a bank of 1 registers each 32 bits wide three classes of instruction control data transfer between memory and the registers one optimized for flexibility of addressing another for rapid context switching and the third for swapping data two instructions control the flow and privilege level of execution three types are dedicated to the control of external coprocessors which allow the functionality ofthe instruction set to be extended in an open and uniform way However as forthe ARM710 the facility to add external coprocessors to the ARM7100 is not available and software emulation of coprocessor activity will be required if these instructions are to perform a defined function The ARM instruction set is a good target for compilers of many different highlevel languages Where required for critical code segments assembly code programming is also straightforward unlike some RISC processors which depend on sophisticated compiler technology to manage complicated instruction interdependencies 32 ARM7100 Data Sheet g ARM DDI 0035A ARM The ARM Processor Mocrocell 33 Memory Interface The memory interface has been designed to allow the performance potential to be realised without incurring high costs in the memory system Speedcritical control signals are pipelined to allow system control functions to be implemented in standard lowpower logic and these control signals permit ARM7100 to exploit the page mode access offered by industrystandard DRAMs 34 Clocking ARM7100 uses the ARM processor macrocell in fastbus mode This means that the core FCLK frequency istied to the main processor input clock MCLK All references to FCLK in this datasheet should be read as MCLK 35 ARM Processor Block Diagram A310 NRW NBW MCLK SNA FCLK NRESET NMREQ Address Buffer Clock C 0 Internal Address Bus n t r I0 NIRQ MMU 8KByte ARM7 NF39Q Cache CPU C Internal Data Bus 0 Write p Buffer r o Iquot c DBE D310 Figure 31 ARM processor block diagram ARM7100 Data Sheet ARM ARM DDI 0035A The ARM Processor Macrocell 3 4 ARM7100 Data Sheet ARM DDI 0035A The ARM Processor Programmer39s Model This chapter describes the programmers model 41 Introduction 42 42 Register Configuration 42 43 Operating Mode Selection 44 44 Registers 44 45 Exceptions 47 46 Configuration Control Registers 411 47 Reset 416 ARM7100 Data Sheet ARM DDI 0035A ARM 4 1 The ARM Processor Programmer39s Model 41 Introduction The ARM processor supports a variety of operating configurations Some are controlled by register bits and are known as the register con gurations Others may be controlled by software and these are known as operating modes 42 Register Configuration The ARM processor provides 3 register configuration settings which may be changed while the processor is running These are discussed below 421 Big and littleendian the bigend bit The bigend bit in the control register sets whether the ARM7100 treats words in memory as being stored in bigendian or littleendian format See OChapter 6 Cache Write Buffer and Coprocessors for more information on the Control Register Memory is viewed as a linearcollection of bytes numbered upwards from zero Bytes 0 to 3 hold the first stored word bytes 4 to 7 the second and so on In the littleendian scheme the lowest numbered byte in a word is considered to be the least significant byte of the word and the highest numbered byte is the most significant Byte 0 of the memory system should be connected to data lines 7 through 0 D70 in this scheme Littleendian Higher Address 31 24 23 16 15 8 7 0 Word Address 11 10 9 8 8 7 6 5 4 4 3 2 1 0 0 Lower Address Least significant byte is at lowest address Word is addressed by byte address of least significant byte Figure 41 Littleendian addresses of bytes within word In the bigendian scheme the most significant byte of a word is stored at the lowest numbered byte and the least significant byte is stored at the highest numbered byte Byte 0 of the memory system should therefore be connected to data lines 31 through 24 D3124 Load and store are the only instructions affected by the endianness see 057 Singe Data Transfer LDR STR on page 521 for more details 42 ARM7100 Data Sheet g ARM DDI 0035A ARM The ARM Processor Programmer39s Model Bigendian Higher Address 31 24 23 16 15 8 7 0 Word Address 8 9 10 11 8 4 5 6 7 4 0 1 2 3 0 Lower Address Most significant byte is at lowest address Word is addressed by byte address of most significant byte Figure 42 Bigendian addresses of bytes within words 422 Configuration bits for backward compatibility The other two configuration bits prog32 and data32 are used for backward compatibility with earlier ARM processors but should normally be set to 1 This mode is recommended for compatibility with future ARM processors and all new code should be written to use only the 32bit operating modes Because the original ARM instruction set has been modified to accommodate 32bit operation there are certain additional restrictions which programmers must be aware of These are indicated in the text Reference should also be made to the ARM Application Notes Rules for ARM Code Writers and Notes for ARM Code Writers available from your supplier ARM7100 Data Sheet 43 ARM ARM DDI 0035A The ARM Processor Programmer39s Model 43 Operating Mode Selection The processor has a 32bit data bus and a 32bit address bus The processor supports byte 8bit and word 32bit data types where words must be aligned to four byte boundaries Instructions are exactly one word and data operations eg ADD are only performed on word quantities Load and store operations can transfer either bytes or words The processor supports six modes of operation 1 User mode usr the normal program execution state 2 FIQ mode fiq fast interrupt for data transfer or channel processes 3 IRQ mode irq used for general purpose interrupt handling 4 Supervisor mode svc a protected mode for the operating system 5 Abort mode abt entered after a data or instruction prefetch abort 6 Undefined mode und entered when an undefined instruction is executed Mode changes may be made under software control or may be brought about by external interrupts or exception processing Most application programs will execute in User mode The other modes known as privileged modes will be entered to service interrupts or exceptions or to access protected resources 44 Registers The processor has a total of 37 registers made up of 31 general 32bit registers and 6 status registers At any one time 16 general registers R0 to R15 and one or two status registers are visible to the programmer The visible registers depend on the processor mode The other registers known as the banked registers are switched in to support IRQ FIQ Supervisor Abort and Undefined mode processing DFigure 4 3 Register organisation on page 4 5 shows how the registers are arranged with the banked registers shaded In all modes 16 registers R0 to R15 are directly accessible All registers except R15 are general purpose and may be used to hold data or address values Register R15 holds the Program Counter PC When R15 is read bits 10 are zero and bits 31 2 contain the PC A seventeenth register the CPSR Current Program Status Register is also accessible It contains condition code flags and the current mode bits and may be thought of as an extension to the PC R14 is used as the subroutine link register and receives a copy of R15 when a Branch and Link instruction is executed It may be treated as a general purpose register at all other times R14svc R14irq R14fiq R14abt and R14und are used similarly to hold the return values of R15 when interrupts and exceptions arise or when Branch and Link instructions are executed within interrupt or exception routines ARM7100 Data Sheet g ARM DDI 0035A ARM The ARM Processor Programmer39s Model General Registers and Program Counter Modes User32 FIQ32 Supervisorlt52 Abort32 IRQ32 Undefined32 R0 R0 R0 R0 R0 R0 R1 R1 R1 R1 R1 R1 R2 R2 R2 R2 R2 R2 R3 R3 R3 R3 R3 R3 R4 R4 R4 R4 R4 R4 R5 R5 R5 R5 R5 R5 R6 R6 R6 R6 R6 R6 R7 R7 R7 R7 R7 R7 R8 R8fiq R8 R8 R8 R8 R9 R9fiq R9 R9 R9 R9 R10 R10fiq R10 R10 R10 R10 R11 R11fiq R11 R11 R11 R11 R12 R12fiq R12 R12 R12 R12 R13 R13fiq R13svc R13abt R13irq R13und R14 R14fiq R14svc R14abt R14irq hR14und R15 PC R15 PC R15 PC R15 PC R15 PC R15 PC Program Status Registers CPSR CPSR CPSR CPSR CPSR CPSR i SPSRfiq NSPSRgvc 3PSRabt i SPSRirq NSPSRjnd b banked register Figure 43 Register organisation FIQ mode has seven banked registers mapped to R8 14R8fiqR14fiq Many FIQ programs will not need to save any registers User mode IRQ mode Supervisor mode Abort mode and Undefined mode each have two banked registers mapped to R13 and R14 The two banked registers allow these modes to each have a private stack pointer and link register Supervisor IRQ Abort and Undefined mode programs which require more than these two banked registers are expected to save some or all of the caller39s registers R0 to R12 on their respective stacks They are then free to use these registers which they will restore before returning to the caller In addition there are also five SPSRs Saved Program Status Registers which are loaded with the CPSR when an exception occurs There is one SPSR for each privileged mode ARM7100 Data Sheet 45 ARM ARM DDI 0035A The ARM Processor Programmer39s Model ags control l l l l 31 30 29 28 27 8 7 6 5 4 3 2 1 0 N Z C V I F M4 M3 MZ M1 MO Overflow Mode bits Carry Borrow Extend FIQ disable Zero IRQ disable Negative Less Than Figure 44 Format of the program status registers PSRs The format of the Program Status Registers is shown in DFlgure 4 4 Format of the program status registers PSRs The N Z C and V bits are the condition code flags The condition code flags in the CPSR may be changed as a result of arithmetic and logical operations in the processor and may be tested by all instructions to determine ifthe instruction is to be executed The and F bits are the interrupt disable bits The I bit disables IRQ interrupts when it is set and the F bit disables FIQ interrupts when it is set The M0 M1 M2 M3 and M4 bits M40 are the mode bits and these determine the mode in which the processor operates The interpretation of the mode bits is shown in DTabe 4 7 The Mode Bits Not all bit combinations define a valid processor mode Only those explicitly described should be used The user should be aware that if any illegal value is programmed into the mode bits M40 the processor will enter an unrecoverable state lfthis occurs reset should be applied The bottom 28 bits of a PSR incorporating F and M40 are known collectively as the control bits These will change when an exception arises and in addition can be manipulated by software when the processor is in a privileged mode Unused bits in the PSRs are reserved and their state must be preserved when changing the flag or control bits Programs must not rely on specific values from the reserved bits when checking the PSR status since they may read as one or zero in future processors M40 Mode Accessible Register Set 10000 User PC R14R0 CPSR 10001 FIQ PC R14fiqR8fiq R7R0 CPSR SPSRfiq 10010 IRQ PC R14irqR13irq R12R0 CPSR SPSRirq 10011 Supervisor PC R14svcR13svc R12R0 CPSR SPSRsvc 10111 Abort PC R14abtR13abt R12R0 CPSR SPSRabt 11011 Undefined PC R14undR13und R12R0 CPSR SPSRund Table 41 The Mode Bits ARM7100 Data Sheet ARM DDI 0035A The ARM Processor Programmer39s Model 45 Exceptions 451 FIQ Exceptions arise whenever there is a need for the normal flow of program execution to be broken so that forexample the processor can be diverted to handle an interrupt from a peripheral The processor state just prior to handling the exception must be preserved so that the original program can be resumed when the exception routine has completed Many exceptions may arise at the same time The ARM processor handles exceptions by making use ofthe banked registers to save state The old PC and CPSR contents are copied into the appropriate R14 and SPSR and the PC and mode bits in the CPSR bits are forced to a value which depends on the exception Interrupt disable flags are set where required to prevent otherwise unmanageable nestings of exceptions In the case of a reentrant interrupt handler R14 and the SPSR should be saved onto a stack in main memory before reenabling the interrupt when transferring the SPSR register to and from a stack it is important to transferthe whole 32bitvalue and notjust the flag or control fields When multiple exceptions arise simultaneously a fixed priority determines the order in which they are handled This is listed later in 0457 Exception priorities on page 410 The FIQ Fast Interrupt reQuest exception is externally generated in response to a FIQ interrupt source becoming active causing the nFIQ input to the macrocell to be taken LOW This input can except asynchronous transitions and is delayed by one clock cycle for synchronisation before it can affect the processor execution flow FIQ is designed to support a data transfer or channel process and has sufficient private registers to remove the need for register saving in such applications thus minimising the overhead of context switching The FIQ exception may be disabled by setting the F flag in the CPSR but note that this is not possible from User mode Ifthe F flag is clear the processor checks for a LOW level on the output ofthe FIQ synchroniser at the end of each instruction When a FIQ is detected the processor 1 Saves the address ofthe next instruction to be executed plus 4 in R14fiq saves CPSR in SPSRfiq 2 Forces M4010001 FIQ mode and sets the F and I bits in the CPSR 3 Forces the PC to fetch the next instruction from address Ox IC To return normally from FIQ use SUBS PC R14fiq4 which will restore both the PC from R14 and the CPSR from SPSRfiq and resume execution of the interrupted code ARM7100 Data Sheet 47 ARM ARM DDI 0035A The ARM Processor Programmer39s Model 452 IRQ The IRQ Interrupt ReQuest exception is a normal interrupt caused by a LOW level on the anQ input to the macrocell It has a lower prioritythan FIQ and is masked out when a FIQ sequence is entered Its effect may be masked out at any time by setting the I bit in the CPSR but note that this is not possible from User mode lfthe flag is clear the processor checks for a LOW level on the output ofthe IRQ synchroniser at the end of each instruction When an IRQ is detected the processor 1 Saves the address of the next instruction to be executed plus 4 in R14irq saves CPSR in SPSRirq 2 Forces M4010010 IRQ mode and sets the I bit in the CPSR 3 Forces the PC to fetch the next instruction from address 0x18 To return normally from IRQ use SUBS PCR14irq4 which will restore both the PC and the CPSR and resume execution of the interrupted code 453 Abort An abort is signalled bythe internal Memory Management Unit An abort indicates that the current memory access cannot be completed For instance in a virtual memo system the data corresponding to the current address may have been moved out of memory onto a disc and considerable processor activity may be required to recover the data before the access can be performed successfully The ARM processor checks for aborts during memory access cycles When successfully aborted ARM processor will respond in one of two ways 1 lfthe abort occurred during an instruction prefetch a Prefetch Abort the prefetched instruction is marked as invalid but the abort exception does not occur immediately lfthe instruction is not executed for example as a result of a branch being taken while it is in the pipeline no abortwill occur An abort will take place ifthe instruction reaches the head ofthe pipeline and is about to be executed 2 lfthe abort occurred during a data access a Data Abort the action depends on the instruction type a Single data transfer instructions LDR STR will write back modified base registers and the Abort handler must be aware of this 8 The swap instruction SWP is aborted as though it had not executed though externally the read access may take place 8 Block data transfer instructions LDM STM complete and if writeback is set the base is updated If the instruction would normally have overwritten the base with data ie LDM with the base in the transfer list this overwriting is prevented All register overwriting is prevented after the Abort is indicated which means in particularthat R15 which is always last to be transferred is preserved in an aborted LDM instruction 48 ARM7100 Data Sheet g ARM DDI 0035A ARM The ARM Processor Programmer39s Model When either a prefetch or data abort occurs the processor x Saves the address of the aborted instruction plus 4 for prefetch aborts or 8 for data aborts in R14abt saves CPSR in SPSRabt Forces M4010111 Abort mode and sets the I bit in the CPSR I 3 Forces the PC to fetch the next instruction from either address OXOC prefetch abort or address 0x10 data abort To return afterfixing the reason forthe abort use SUBS PCR14abt4 for a prefetch abort or SUBS PCR14abt8 for a data abort This will restore both the PC and the CPSR and retry the aborted instruction The abort mechanism allows a demand paged virtual memory system to be implemented when suitable memory management software is available The processor is allowed to generate arbitrary addresses and when the data at an address is unavailable the MMU signals an abort The processor traps into system software which must work out the cause of the abort make the requested data available and retry the aborted instruction The application program needs no knowledge ofthe amount of memory available to it nor is its state in any way affected by the abort 454 Software interrupt The software interrupt instruction SWI is used for getting into Supervisor mode usually to request a particular supervisor function When a SWI is executed the processor 1 Saves the address ofthe SWI instruction plus 4 in R14svc saves CPSR in SPSRsvc 2 Forces M4010011 Supervisor mode and sets the I bit in the CPSR 3 Forces the PC to fetch the next instruction from address 0x08 To return from a SWI use MOVS PCR14svc This will restore the PC and CPSR and return to the instruction following the SWI 455 Undefined instruction trap When the ARM processor comes across an instruction which it cannot handle see OChapter 5 ARM Processor Instruction Set it will take the undefined instruction trap This includes all coprocessor instructions except MCR and MR0 operations which access the internal control coprocessor The trap may be used for software emulation ofa coprocessor in a system which does not have the coprocessor hardware or for general purpose instruction set extension by software emulation When the ARM processor takes the undefined instruction trap it 1 Saves the address ofthe Undefined or coprocessor instruction plus 4 in R14und saves CPSR in SPSRund 2 Forces M4011011 Undefined mode and sets the I bit in the CPSR ARM7100 Data Sheet 49 ARM ARM DDI 0035A The ARM Processor Programmer39s Model 3 Forces the PC to fetch the next instruction from address 0x04 To return from thistrap after emulating the failed instruction use MOVS PCR14und This will restore the CPSR and return to the instruction following the undefined instruction 456 Vector summary Address Exception Mode on Entry 0x00000000 Reset Supervisor 0x00000004 Undefined instruction Undefined 0x00000008 Software interrupt Supervisor 0x0000000C Abort prefetch Abort 0x00000010 Abort data Abort 0x00000014 reserved 0x00000018 IRQ IRQ 0x00000010 FIQ FIQ Table 42 Vector summary These are byte addresses and will normally contain a branch instruction pointing to the relevant routine The FIQ routine might reside at 0x10 onwards and thereby avoid the need for and execution time of a branch instruction 457 Exception priorities When multiple exceptions arise at the same time a fixed priority system determines the order in which they will be handled 1 2 3 4 5 6 Reset highest priority Data a be it FIQ IRQ Prefetch abort Undefined Instruction Software interrupt lowest priority Note that not all exceptions can occur at once Undefined instruction and software interrupt are mutually exclusive since they each correspond to particular non overlapping decodings ofthe current instruction If a data abort occurs at the same time as a FIQ and FIQs are enabled ie the F flag in the CPSR is clear ARM processor will enter the data abort handler and then immediately proceed to the FIQ vector A normal return from FIQ will cause the data ARM7100 Data Sheet ARM DDI 0035A The ARM Processor Programmer39s Model abort handler to resume execution Placing data abort at a higher priority than FIQ is necessary to ensure that the transfer error does not escape detection the time forthis exception entry should be added to worst case FIQ latency calculations 46 Configuration Control Registers The operation and configuration of the ARM processor is controlled both directly via coprocessor instructions and indirectly via the Memory Management Page tables The coprocessor instructions manipulate a number of onchip registers which control the configuration of the Cache write buffer MMU and a number of other configuration options To ensure backwards compatibility of future CPUs all reserved or unused bits in registers and coprocessor instructions should be programmed to 39039 Invalid registers must not be readwritten The following bits must be programmed to 39039 Register1 bits3111 Register 2 bits130 Register 5 bits310 Register 6 bits110 Register 7 bits310 Note The grey areas in the register and translation diagrams are reserved and should be programmed to 0 for future compatibility 461 Internal coprocessor instructions These registers may be read using MRC instructions and written using MCR instructions These operations are only allowed in nonuser modes and the undefined instruction trap will be taken if accesses are attempted in user mode 31 28 27 24 23 21 20 19 16 15 12 11 7 5 4 0 Cond 1 1 1 0 n CRn Rd 1 1 1 1 1 Cond ARM condition codes Crn ARMXXX Register Rd ARM Register n 1 MRC register read 0 MRC register write Figure 45 Format of internal coprocessor instructions MR0 and MCR 462 Registers The ARM processor contains registers which control the cache and MMU operation These registers are accessed using CPRT instructions to Coprocessor 15 with the processor in a privileged mode Only some of registers 07 are valid an access to an ARM7100 Data Sheet 4 11 ARM ARM DDI 0035A The ARM Processor Programmer39s Model invalid register will cause neither the access nor an undefined instruction trap and therefore should never be carried out an access to any ofthe registers 815 will cause the undefined instruction trap to be taken Register Register Reads Register Writes 0 ID Register Reserved 1 Reserved Control 2 Reserved Translation Table Base 3 Reserved Domain Access Control 4 Reserved Reserved 5 Fault Status Flush TLB 6 Fault Address Purge TLB 7 Reserved Flush IDC 815 Reserved Reserved Table 43 Cache and MMU control register Register 0 ID Register 0 is a readonly identity register that returns the ARM Ltd code for this chip 0x4104710x 31 Z4 Z3 16 15 4 3 0 41 04 710 Revision 412 ARM7100 Data Sheet g ARM DDI 0035A ARM The ARM Processor Programmer39s Model Register 1 Control Register 1 is write only and contains control bits A bits in this register are forced LOW by reset 313029282726 9876543210 lolOlOlolOlol0M0i0MviololololololololololRlslBlllDlPlWlClAlMl M BitO Enabledisable 0 onchip Memory Management Unit turned off 1 onchip Memory Management Unit turned on A Bit 1 Address Fault EnableDisable 0 alignment fault disabled 1 alignment fault enabled C Bit 2 Cache EnableDisable 0 Instruction data cache turned off 1 Instruction data cache turned on W Bit 3 Write buffer EnableDisable 0 Write buffer turned off 1 Write buffer turned on P Bit 4 ARM 3226 Bit Program Space 0 26bit Program Space selected 1 32bit Program Space selected D Bit 5 ARM 3226 Bit Data Space 0 26bit Data Space selected 1 32bit Data Space selected B Bit 7 BigIittIeendian 0 Littleendian operation 1 Bigendian operation S Bit8 System This bit controls the ARM processor permission system R Bit9 ROM This bit controls the ARM processor permission system ARM7100 Data Sheet 413 ARM ARM DDI 0035A The ARM Processor Programmer39s Model Register 2 Translation Table Base Register 2 is a writeonly register which holds the base of the currently active Level One page table 31 14 13 0 Translation Table Base Register 3 Domain Access Control Register 3 is a writeonly register which holds the current access control for domains to 15 313029282726252423222120191817161514131211109876543210 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register 4 Reserved Register 4 is Reserved Accessing this register has no effect but should never be attempted Register 5 Read Fault Status Reading register 5 returns the status of the last data fault It is not updated for a prefetch fault Note that only the bottom 12 bits are returned The upper 20 bits will be the last value on the internal data bus and therefore will have no meaning Bits 11 8 are always returned as zero 31 12 11 3 7 4 3 o 0 0 0 0 Domain Status Write Translation Lookaside Buffer Flush Writing Register 5 flushes the TLB The data written is discarded 414 ARM7100 Data Sheet g ARM DDI 0035A ARM The ARM Processor Programmer39s Model Register 6 Read Fault Address Reading register 6 returns the virtual address of the last data fault Fault Address Write TLB Purge Writing Register 6 purges the TLB the data is treated as an address and the TLB is searched for a corresponding page table descriptor If a match is found the corresponding entry is marked as invalid This allows the page table descriptors in main memory to be updated and invalid entries in the onchip TLB to be purged without requiring the entire TLB to be flushed 31 14 13 0 Purge Address Register 7 IDC Flush Register 7 is a writeonly register The data written to this register is discarded and the IDC is flushed Registers 8 15 Reserved Accessing any ofthese registers will cause the undefined instruction trap to be taken ARM7100 Data Sheet 415 ARM ARM DDI 0035A The ARM Processor Programmer39s Model 47 Reset When the nRESET input to the processor macrocell goes LOW the ARM processor abandons the executing instruction and then performs idle cycles from incrementing word addresses When the nRESET macrocell input goes HIGH again the ARM processor does the following 1 Overwrites R14svc and SPSRsvc by copying the current values of the PC and CPSR into them The value ofthe saved PC and CPSR is not defined I Forces M4010011 Supervisor mode and sets the and F bits in the CPSR 3 Forces the PC to fetch the next instruction from address 0X00 At the end of the reset sequence the MMU is disabled and the TLB is flushed so forces flat translation ie the physical address is the virtual address and there is no permission checking alignment faults are also disabled the cache is disabled and flushed the write buffer is disabled and flushed the ARM7 CPU core is put into 26bit data and address mode and littleendian mode ARM7100 Data Sheet ARM DDI 0035A


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