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by: Dr. Jake Carter


Dr. Jake Carter
GPA 3.83

Thomas Murphy

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Thomas Murphy
Class Notes
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This 28 page Class Notes was uploaded by Dr. Jake Carter on Saturday October 3, 2015. The Class Notes belongs to ENGR 2030 at Armstrong Atlantic State University taught by Thomas Murphy in Fall. Since its upload, it has received 107 views. For similar materials see /class/217870/engr-2030-armstrong-atlantic-state-university in Engineering and Tech at Armstrong Atlantic State University.




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Date Created: 10/03/15
Quartus 11 Introduction Using VHDL Design This tutorial presents an introduction to the Quartus H CAD system It gives a general overview of a typi cal CAD ow for designing circuits that are implemented by using FPGA devices and shows how this ow is realized in the Quartus II software The design process is illustrated by giving stepbystep instructions for using the Quartus II software to implement a very simple circuit in an Altera FPGA device The Quartus II system includes full support for all of the popular methods of entering a description of the desired circuit into a CAD system This tutorial makes use of the VHDL design entry method in which the user speci es the desired circuit in the VHDL hardware description language Two other versions of this tutorial are also available one uses the Verilog hardware description language and the other is based on de ning the desired circuit in the form of a schematic diagram The last step in the design process involves con guring the designed circuit in an actual FPGA device To show how this is done it is assumed that the user has access to the Altera DE2 Development and Education board connected to a computer that has Quartus II software installed A reader who does not have access to the DE2 board will still nd the tutorial useful to learn how the FPGA programming and con guration task is performed The screen captures in the tutorial were obtained using the Quartus II version 80 if other versions of the software are used some of the images may be slightly different Contents Typical CAD Flow Getting Started Starting a New Project VHDL Design Entry Compiling the Design Pin Assignm ent Simulating the Designed Circuit Programming and Con guring the FPGA Device Testing the Designed Circuit Computer Aided Design CAD software makes it easy to implement a desired logic circuit by using a pro grammable logic device such as a eldprogrammable gate array FPGA chip A typical FPGA CAD ow is illustrated in Figure l Design Entry Functional Simulation Yes Timing Analysis and Simulation No Timing Programming and Configuration Figure 1 Typical CAD ow The CAD ow involves the following steps 0 Design Entry 7 the desired circuit is speci ed either by means of a schematic diagram or by using a hardware description language such as Verilog or VH 0 Synthesis 7 the entered design is synthesized into a circuit that consists of the logic elements LES provided in the FPGA chip 0 Functional Simulation 7 the synthesized circuit is tested to verify its functional correctness this simulation does not take into account any timing issues o Fitting 7 the CAD Fitter tool determines the placement of the LEs de ned in the netlist into the LEs in an actual FPGA chip it also chooses routing wires in the chip to make the required connections between speci c LEs 0 Timing Analysis 7 propagation delays along the various paths in the tted circuit are analyzed to provide an indication of the expected performance of the circuit 0 Timing Simulation 7 the tted circuit is tested to verify both its functional correctness and timing 0 Programming and Con guration 7 the designed circuit is implemented in a physical FPGA chip by pro gramming the con guration switches that con gure the LEs and establish the required wiring connections This tutorial introduces the basic features of the Quartus II software It shows how the software can be used to design and implement a circuit speci ed by using the VHDL hardware description language It makes use of the graphical user interface to invoke the Quartus II comm ands Doing this tutorial the reader will learn about 0 Creating a project 0 Design entry using VHDL code 0 Synthesizing a circuit speci ed in VHDL code 0 Fitting a synthesized circuit into an Altera FPGA o Assigning the circuit inputs and outputs to speci c pins on the FPGA o Simulating the designed circuit 0 Programming and con guring the FPGA chip on Altera s DE2 board 1 Getting Started Each logic circuit or subcircuit being designed with Quartus II software is called a project The software works on one project at a time and keeps all information for that project in a single directory folder in the le system To begin a new logic circuit design the rst step is to create a directory to hold its les To hold the design les for this tutorial we will use a directory inlralularial The running example for this tutorial is a simple circuit for twoway light control Start the Quartus II software You should see a display similar to the one in Figure 2 This display consists of several windows that provide access to all the features of Quartus II software which the user selects with the computer mouse Most of the commands provided by Quartus II software can be accessed by using a set of menus that are located below the title bar For example in Figure 2 clicking the left mouse button on the menu named File opens the menu shown in Figure 3 Clicking the left mouse button on the entry Exit exits from Quartus II software In general whenever the mouse is used to select something the left button is used Hence we will not normally specify which button to press In the few cases when it is necessary to use the rightmouse button it will be speci ed explicitly as Edit Mew Emject siiqm enls Harassing mi Mndaw ab 9QE n n A swim Hievamwi AHievauhy EH2 DesignUh39us Tas x Haw momquot Av E n vWgwwewhmwwmmwu m QUARTUS II Versiun 80 Dncumemallnn E mg Pmcessmgquot ExnaWa Wu 3 5mm Fm Heb W255 n Waming A Evmcaiwammg Em Suppvessed Figure 2 The main Quarrle H display Edit View Projezt Assignments QDen New Project Mad a Open Plnjecz Cunvevt MAXPLU5 1 Mai w ctrIJ ct Cler bu Hum cvaate Lupdate E Lnr Cunve39t Programmlng Files IJ E3 39 J H Mn my 7 gm wwr Rt Racent les Recent Prujezts Ezit AltW4 L We Van3 Me i M y 4 Figure 3 An example of the File menu For some commands it is necessary to access two or more menus in sequence We use the convention Menul gtMenu2gtltem 39 439 4 H h A 39 A huuld rstclickthe on Menu1 then within this menu click on Menu2 and then within Menu2 click on Item For example File gt Exit uses the mouse to exit from the system Many commands can be invoked by clicking on an icon displayed in one of the toolbars To see the command associated with an icon position the mouse over the icon and a tooltip will appear that displays the command name 11 Quartus 11 Online Help Quartus 11 software provides comprehensive online documentation that answers many of the questions that may arise when using the software The documentation is accessed from the Help menu To get some idea of the extent or 39 quot iti wututwuite Jul ure reader 39 lelp ulcuu For instance selecting Help gt How to Use Help gives an indication ofwhat type ofhelp is provided user can quickly search through the Help topics by selecting Help gt Search which opens a dialog box into which keywords can be entere Another metho contextsensitive help is provided for quickly nding documentation for speci c topics While using most applications pressing the F1 function key on the keyboard opens a Help display that shows the commands available for the application 2 Starting a New Project To start working on a new design we rst have to de ne a new derign project Quartus 11 software makes the designer s task easy by providing support in the form ofa wizard Create a new project as follows 1 Select File gt New Project Mzard to reach the window in Figure 4 which asks for the name and directory of the project New Pr llclnr Name vel En ypage1nl 5 FE Whet e the hethhg diieelmy tet the pmiee D inlmlulmial Whet e the heme et the Diaieew ttght Whet te the heme al the luv level deslgn ehttty tet this pteteen This heme te case sensitive eha must exactly meteh the ehttty heme th the deSlEn ttte ttght Lise Existing Pmleel Settings t hmeh eeheet Figure 4 Creation ofa new project 2 Set the working directory to be introtutoria of course you can use some other directory name of your choice ifyou prefer The project must have a name which is usually the same as the toplevel design entity that will be included in the project 39 for both 39 enti as shown in Figure 4 Press Next Since we have not yet created the directory intromtoria Quartus 11 software displays the popup box in Figure 5 asking if it should create the desired directory Click Yes which leads to the window in Figure 6 A oiieemiy o Ilnlmlulmlal does not exist Do you want in Veale iv in Figure 5 Quartus ll software can create a new directory for the project zar Add F 5 page 2 at 5 Z Seieei ine dewquot lilesyau want la include in ine piaieei ElickAddAll la add all deSlgn Mes in ine piaieei diveclaw la ine piaieei Nate you can always add design Mes la ine piaieei ieiei iij Eiie name 1 4 nienene noiieieian Ad leii l gt sneeiry ine pain names al any nan delaull iinieiiee Hg Liming New nnisn eeneei Figure 6 The wizard can include userspeci ed design les 3 39 39 tospecify quot quot 39 39 quot 39 Assuming that we do not have any existing les click Next which leads to the wind w in Figure 7 NevPm cIW av Fam yRD c2 5 gspage 31115 Selecl lhe raw and devieeyau wanl m lavgel lav eamvilalmn me raw haw m vailahle device m Eamily Eyelane u v Package Any v i u Pm gaunl Any v SPEEd Evade v el device r Aim device seleeled by lhe Filler F Demhe device seleeled m Availahle devices m r Show advanced devices Axailahle devices lt Back rm Eaneel m I T M Figure 7 Choose the device family and a speci c device 39Luerpcuf quot quot quot quot II 39 quot We can let Ouaml 39 39G 39 39 39 39 39L or choose the device explicitly We will take the laner approach From the list of available devices choose the ex ire railed 39 39 used on Altera DFZ board Press Next which opens the window in Figure 8 New Prnjecl Wimrd rm Tunl Selling page 4 n 5 sugary lhe my EDA laals m addman m lhe Uuavlus u sallwave used W the Dvaleel r Deslgn Envy5mm 75mm Wm r 3 F l Winem WW r mm m l wank W cm Figure 8 Other EDA tools can be speci ed 5 The user can specify any thirdparty tools that should be used A commonly used term for CAD software for 39 39 39 39 FDA rmlv In niecuonic Design Automation This term is used in Quartus 11 messages that refer to thirdparty tools which are the tools developed and marketed by companies other than Altera Since we will rely solely on Quartus 11 tools we will not choose any other tools Press Next 6 A summary ofthe chosen settings appears in the screen shown in Figure 9 Press Finish which returns to the main Quartus ll window but with light speci ed as the new project in the display title bar as indicated in Figure 10 av Summarypag 5 gr 5 wnen you click Finisn ine pigieei will he cvealed niin ine lallawmg seuings Pigieei diieeigiy D MmekUP DacumenlalmnTulanalsN3 iniig seneniniigigigiiei Pigieei ame iigni Tap level design eniiiy iigni Numbev gr riies added Numhev gr gsei iinieiies added u Device essignnenis Feniiy name Eyeigne H e iee Epzcaarsms ED iggis Design eniiysyninesis ltNanegt singieiign ltNanegt ltNanegt rining analy i upeieiing egndiiigns gie valleys i z lgneiign lemvevalme ienge n 8539 saeei eeneei Figure 9 Summary ofthe project settings Figure 10 The Quartus II display for the created project 3 Design Entry Using VIIDL Code As a design example we will use the tvvo way light controller circuit shown in Figure 11 The circuit can be used to control a single light from either of the two switches 11 and 12 where a closed switch corresponds to the logic value 1 The truth table for the circuit is also given in the gure Note that this is just the ExclusiveOR function of the inpum 11 and 12 but we will specify it using the gates shown X1 OHHo s b OD O Figure 11 The light controller circuit The required circuit is described by the VHDL code in Figure 12 Note that the VHIDL entity is called light to match the name given in Figure 4 which was speci ed when the project was created This code can be typed into a le by using any text editor that stores ASCII les or by using the Quartus ll text editing facilities While the le can be given any name it is a common designers7 practice to use the same name as the name of the toplevel VHDL entity The le name must include the extension vhd which indicates a VHDL le So we will use the name lightvhd LIBRARY ieee 39 USE ieeestdilogic71164all 39 ENTITY light IS PORT x1 x2 IN STDiLOGIC 39 f OUT STDiLOGIC 39 END light 39 ARCHITECTURE LogicFunction OF light IS BEGIN f lt x1 AND NOT x2 OR NOT x1 AND x2 END LogicFunction 39 Figure 12 VHDL code for the circuit in Figure 11 31 Using the Quartus 11 Text Editor This section shows how to use the Quartus II Text Editor You can skip this section if you prefer to use some other text editor to create the VHDL source code le which we will name lightvhd Select File gt New to get the window in Figure 13 choose VHDL File and click OK This opens the Text Editor window The rst step is to specify a name for the le that will be created Select File gt Save As to open the popup box depicted in Figure 14 In the box labeled Save as type choose VHDL File In the box labeled File name type light Put a checkmark in the box Add file to current project Click Save which puts the le into the directory inl ratularial and leads to the Text Editor window shown in Figure 15 Maximize the Text Editor window and enter the VHDL code in Figure 12 into it Save the le by typing File gt Save or by typing the shortcut CtrIs Most of the comm ands available in the Text Editor are selfexplanatory Text is entered at the insertion point which is indicated by a thin vertical line The insertion point can be moved either by using the keyboard arrow keys or by using the mouse Two features of the Text Editor are especially convenient for typing VHDL code First the editor can display different types of VHDL statements in different colors which is the default choice Second the editor can automatically indent the text on a new line so that it matches the previous line Such options can be controlled by the settings in Tools gt Options gt TeXt Editor r3 lightvnd Save in My Recent Documents Deskmv My Documents My Eampmev 2 My Neiwmk Pisces F mnmmmiai v r r e DiagvamSehemahe He He Bin2k Em y F12 demmai Wei exa rawau We wavy imhahzahan ugg We La n a SignaWaD M 1m An Veeim Wayermm We sing We ck symha r e um Desmummy We Synavsys Des gn Eansnaims We Text Me igure 13 Choose to prepare a VHDL le Erv He ame 39 Save astVDe VHDL We r war mu 39 rv Add Me in cuuenmmeu Figure 14 Name the le cm Figure 15 Text Editor window 11 311 Using VHDL Templates The syntax of VHDL code is sometimes di lcult for a designer to remember To help with this issue the Text Editor provides a collection of VHDL templates The templates provide examples of various types of VHDL statements such as an ENTITY declamtion a CASE statement and assignment statements It is worthwhile to browse through the templates by selecting Edit gt Insert Template gt VHDL to become familiar with this resource 32 Adding Design Files to a Project As we indicated when discussing Figure 6 you can tell Quartus 11 software which design les it should use as part of the current project To see the list of les already included in the light project select Assignments gt Settings which leads to the window in Figure 16 As indicated on the le side of the gure click on the item Files An alternative way ofmaking this selection is to choose Project gt AddRemove Files in Project If you used the Quartus 11 Text Editor to create the le and checked the box labeled Add fi le to current project as described in Section 31 then the lightvhd le is already a part of the project and will be listed in the window in Figure 16 Otherwise the le must be added to the project So ifyou did not use the Quartus 11 Text Editor then place a copy of the le light vhd which you created using some other text editor into the directory introlutorial To add this le to the project click on the File name button in Figure 16 to get the popup window in Figure 17 Select the light vhd le and click Open The selected le is now indicated in the Files window of Figure 16 Click OK to include the lightvhd le in the project We should mention that in many cases the Quartus 11 software is able to automatically nd the right les to use for each entity referenced in VHDL code even if the le has not been explicitly added to the project However for complex projects that involve many les it is a good design practice to speci cally add the needed les to the proj ect as described above Settings 7 list General M Libraries Select lhe design Mes you want in meme m lhe pmjeel ElmkAddAll in add all design Me in lhe Device waxed due aw m lhe pmjecl Filename 1 Fe Type l bravely DewennyE l Dngvsgq Adm wotrle ltNanegt Unevalmg Selling and Eandmans Valle e r mveval EamwlalmnP Ea races Selling ng Estimate vly Tum EDA Taal Selling Deslgn EntrySynthesis Simulalmn MU Delaull Parameters Synthesis Nellisl UPlimizalmns FillevSellmgs Physical 5mm npnmenm limingAnaLVslsSellm s Time uesl mm Analyzer mam limingAnalyzer 82mm mam mm Analyzer R Logic Analyzer lnlevlaee 39 l 1 ewe Figure 16 Settings window EV tank in H3 mlmlulmial 5 EM 1 El Desklav My Documents My Eamvulei j Mypt ielwmk me name hgm Filesailwe DesignFileslquotldl39vhd39vhdl39v39vlg39Willa v Eam Figure 17 Select the le 4 Compiling the Designed Circuit L ode in the le lightvhd is processed by several Quartus 11 tools that analyze the code synthesize t and gener t an implementation of it for the target chip These tools are controlled by the application The VHD the circui program called the Com ile Run the Compiler by selecting Processing gt Start Compilation or by clicking on the toolbar icon gt that looks L on the left side ofthe Quartus 11 display Successful or unsuccessful compilation is indicated in a popup box Acknowledge it by clicking OK which leads to the Quartus II is ay in Figure 18 In the mes age window at the bottom ofthe gure Various messages are displayed In case of errors there will be appropriate messages given Fiaw Status Successiuirwedlun 25w oz 3 2mm mend it Veisian a n Buiid 2 5 nazaznna st FuiiVevsmn Revision awe TDD ievei My Name emiy Device Timing Made Mei timing ie uiiemenis Tutsi iDEiI eiemenis hinaimnai iunciians Dedicated iDEiI vegisievs EI332151EI z Tutsi VEEisievs Tutsi pins 3 m l lt 1 z Tutsi Wiuai Din n Tutsi memmy hits n mm 1 n 2 Embedded Muiiiviiev a m eiemenis n l n z Tutsi PLL n7 um 41 uaxcus 13 see mung Analyze was an emxs u waxnlngs rm uaxcus rr mu Eampllaman was an emxs 3 waxnlngs Figure 18 Display alter a success Jl compilation When the compilation is nished a compilation report is produced A window showing this report is opened automatically as seen in Figure 18 The window can be resized maximized or closed in the normal way and it can be opened at any time either by selecting Processing gt Compilation Report or by clicking on the icon 9 The report includes a number of sections listed on the le side of its window Figure 18 displays the Compiler Flow Summary section which indicates that only one logic element and three pins are needed to implement this tiny circuit on the selected FPGA chip 41 Errors Quartus II so ware displays messages produced during compilation in the Messages window If the VHDL design le is correct one of the messages will state that the compilation was successful and that there are no errors If the Compiler does not report zero errors then there is at least one mistake in the VHDL code In this case a message corresponding to each error found will be displayed in the Messages window Doubleclicking on an error message will highlight the offending statement in the VHDL code in the Text Editor window Similarly the Compiler may display some warning messages Their details can be explored in the same way as in the case of error messages The user can obtain more information about a speci c error or warning message by selecting the message and pressing the F1 inction key o see the effect of an error open the le lightvhd Remove the semicolon in the statement that de nes the function f illustrating a typographical error that is easily made Compile the erroneous design le by clicking on the F icon A popup box will ask if the changes made to the lightvhd le should be saved click Yes A er trying to compile the circuit Quartus II so ware will display apopup box indicating that the compilation was not successful Acknowledge it by clicking OK The compilation report summary given in Figure 19 now con rms the failed result Expand the Analysis amp Synthesis part of the report and then select Messages to have the messages displayed as shown in Figure 20 Doubleclick on the rst error message Quartus II so ware responds by opening the lightyhd le and highlighting the statement which is affected by the error as shown in Figure 21 Correct the error and recompile the design e Flaw Slams How Falled AWed Jun 2515 AWE zuua uarlus ll Vetslun 3 u Bulld 215 DEIZSlZ B SJ FUNamen wsmn Name 1 YnDJevel Entity Name llghl anvil r y Eyclnnell n 1 as hes gal naySVS vn IS EP2C35F87ZCE Fmal SE Summa Messages Total lugic elements Total wmbmanunal Vunclinns edmaled lag regislets Tara tamer Tale um Total vlluel um ma mama b39 s mbaidad maple 3bit elemen s mm Pamnon Me Tum PLL NA unll man39squot Merge Figure 19 Compilation report for the failed design 4 Cumpilalinn Repnll 7 Analysis 1 Synthesis Messages Analysls amp Synthesls Messages a plat new 53 12mm a t xt t xt txxtttttttttttttttttttt Runnan Uuaxcus n Analysls L SYnLh mend waxcus m n rrwnceisecmngsiflles x cexL39KZIIDquot e y y i In a c 7 7 em Em Unsum mm syntax em a lwhmvhdtgl m 3 u 5 law we mm mm D design unnzs 1 5 m s wms Error uuaxcus u mum 1 Synthesis was unsucce max u warnings gamma 55 Messages 1 quotExtvalnra Wan Wammg EvmcalWammg Eum 21 Flag 1 H A 11 Message ElaH Figure 20 Error messages wt light LIBRARY 3222 us eEEstd1Bgic4164all1 ENTITY light 15 pom x1x2 m m STD LOGIC our STD LOGIC ARCHITECTURE Logchuncclun or light IS EEGIN ilt x1 Am No1 leonmo39r x1 MID x2 wmdmmwwMH Figure 21 Identifying the location of the error 5 Pin Assignment During the compilation above the Quartus II Compiler was free to choose any pins on the selected FPGA to serve as inputs and outputs However the DE2 board has hardwired connections between the FPGA pins and the other components on the board We will use two toggle switches labeled SW0 and SW1 to provide the external inputs 961 and 962 to our example circuit These switches are connected to the FPGA pins N25 and N26 respectively We 15 will connect the output f to the green lightemitting diode labeled LEDGO which is hardwired to the FPGA pin AE22 Figure 22 The Assignment Editor window Pin assignments are made by using the Assignment Editor Select Assignments gt Assignment Editor to reach the window in Figure 22 Under Category select Pin Doubleclick on the entry ltltnewgtgt which is highlighted in blue in the column labeled To The dropdown menu in Figure 23 will appear Click on 961 as the rst pin to be assigned this will enter 961 in the displayed table Follow this by doubleclicking on the box to the right ofthis new 961 entry in the column labeled Location Now the dropdown menu in Figure 24 appears Scroll down and select PI NN25 Instead ofscrolling down the menu to nd the desired pin you canjust type the name ofthe pin N25 in the Location box Use the same procedure to assign input 962 to pin N26 and output f to pin AE22 which resulw in the image in Figure 25 To saVe the assignments made choose File gt Save You can also simply close the Assignment Editor window in which case a popup box will ask if you want to saVe the changes to assignments click Yes Recompile the circuit so that it will be compiled with the correct pin assignmenw v f I39KI D Figure 23 The dropdown menu displays the input and output names ilo Barks 2 M5122quot ilo Banks 10 as mygizan llo Bank 5 Lvosiisu iIo Bankz sdicatad Clank ciKi imam Inuut 110 Bank Dedicated am am Lvnscixup Input io m 2 Raw io m U0 Rpwnc E vuo Banks i at o Barks numbed ak cixsnvnsuxm Input 110 Bank Dedinahed duck cm NDSClKin Input 110 Bank i Daditatad Clark ciKz stcLKIw mm 110 Benin Raw 0 ivoszsp DPCLKiDQSilCQIM 110 Bank i Raw io LVDSZ n 110 Bank i am no ivosm 110 Bank i Raw io tvnszzp 110 Bank 2 Raw uo NDS31n v Figure 24 The available pins Figure 25 The complete assignment The DE2 board has xed pin assignments Having nished one design the user will want to use the same pin assignment for subsequent designs Going through the procedure described above becomes tedious if there are many pins used in the design A useful Quartus II feature allows the user to both export and import the pin assignments from a special le format rather than creating them manually using the Assignment Editor A simple le format that can be used for this purpose is the commasepamted value CSW format which is a common text le format that contains commadelimited values This le format is often used in conjunction with the Microsoft Excel spreadsheet program but the le can also be created by hand using any plain ASCII text editor The format for the le for our simple project is To Location x1 PIN7N25 x2 PIN N26 f PINiAE22 By 39 quot any number of 39 39 be created h 9 be imported into any design project Ifyou created a pin assignment for a particular project you can export it for use in a different project To see how this is done open again the Assignment Editor to reach the window in Figure 25 Now select File gt Export which leads to the window in Figure 26 Here the le lightcxv is available for export Click on Export Ifyou now look in the directory introtutorial you will see that the le light my has been created Save n tntmtttenet v as mes MyRecenl Documents L Desktav MyDacumenls MyEamDulev s Mypt letwmk Ftlename 39 Saveaslwe EammaSeparatedValueFtlel39csv v Eancel Figure 26 Exporting the pin assignment on can import a pin assignment by choosing Assignments gt Import Assignments This opens the dia logue in Figure 27 to select the le to import Type the name ofthe le including the cxv extension and the full L L t t r File OK Of course the desired le Impnrl Assignments Svemly tne sum2 and eeteganes a esstgnnents to val Eltck Lagtctack lmvmt rtteAsstgnnents la seteet Lagtctack lmvmt rttetsl 39Asstgnmenl sum2 a Ftlename 1 4 r Use Lagtctack lmvml FtleAsstgnmenls 17 Bow extsttng esstgnnents mm ttgnt qst hak helme tnpmttng Figure 27 Importing the pin assignment For convenience when using large designs all relevant pin assignments for the DE2 board are given in the le called DEZJiniaxsignmerLtmxv in the directory DEzitutorial dexign ex which is included on the CDROM 39 39 39 39 39 Alterz 39 p mi uttnti in the DE2 User JWmuaJ If we wanted to make the pin assignments for our example circuit by importing this le then we would have to use the same names in our VHDL design le namely SW0 SWJ and LEDG0 for x1 x2 andf respectively Since these signals are speci ed in the DEZJiniarsignmentmxv le as elemenm of vectors SW and LEDG we must refer to them in the same way in the VHDL design le For example in the jini 39 le the 39 L 4 W 7to SW0 since VHDL uses parentheses rather than square brackets these switches are referred to as SW07 to SW0 They can also be referred to as an array SW17 downto 0 6 Simulating the Designed Circuit Before implementing the designed circuit in the FPGA chip on the DE2 board it is prudent to simulate it to ascertain its co ectness Quartus 11 software includes a simulation tool that can be used to simulate the behavior of a designed circuit Before the circuit can be simulated it is necessary to create the desired waveforms called text vectors to represent the input signals It is also necessary to specify which outputs as well as possible internal points in the circuit the designer wishes to observe The simulator applies the test vectors to a model of the implemented circuit and determines the expected response We will use the Quartus II Waveform Editor to draw the test vectors as follows 1 Open the Waveform Editor window by selecting File gt New which gives the window shown in Figure 28 Choose Vector Waveform File and cl39ck O Ihe Waveform Editor window is depicted in Figure 29 Save the le under the name lightvwf note that this changes the name in the displayed window Set the desired simulation to run from 0 to 2 0 ns by selecting Edit gt End Time and entering 200 ns in the dialog box that pops up Selecting View gt Fit in Window displays the entire simulation range of 0 to 200 ns in the window as shown in Figure 30 You may wish to resize the window to its maximum size sup may System newquot Files AHDL rue Black DiagramSchematic rue r r 8 Venlag HDL rue VHDLFxle MemaVyFiles Hexadecimai Wei meail rue Mammy initialization rue VenhcahanDehuggmg Files in System Sam22s and thes rue Lagu Anavaev lntevlace rue Signallav u LagicAnavaev rue r r 9 Man me v y newquot Eanshamts rue Figure 28 Need to prepare anew le 1535quot Wu marvel 4 25 Slay Value at 5 1595quot Figure 29 The Waveform Editor window 19 Value at NW 5 95 ns Figure 30 The augmented Waveform Editor window Next we want to include the input and output nodes ofthe circuit to be simulated Click Edit gt Insert gt Insert Node or Bus to open the window in Figure 31 It is possible to type th name of a signal pin into th Name box but it is easier to click on the button labeled Node Finder to open the window in Figure 2 The Node Finder utility has a lter used to indicate what type of nodes are to be found Since we are interested in input and utput pins set the lter to Pins all Click the List bunon to nd the input and output nodes as indicated on the left side of the gure Insert Nude a Bus 1 Display may code Emmi as binavy Emmi Figure 31 The Insert Node or Bus dialogue Named Fl 4 we W at Euslamize mt EIK v J 17 lncludesubenlilies 4 Eancel and Selected Nudes N mm Name Name lmwm i x W WWW l We ptmzz umpm mm input Pwmza input Dilighlle Pmst input PlNiNZS Dilighlll PlNiAEZZ EMAle Figure 32 Selecting nodes to insert into the Waveform Editor Clickonthex 39 quot quot 39 39 Nodes box on the right side of the gure Do the same for x2 andf Click OK to close the Node Finder window and then click OK in the window of Figure 31 This leaves a fully displayed Waveform Editor window as shown in Figure 33 Ifyou did not select the nodes in the same order as displayed in Figure 33 it is possible to rearrange them To move a waveform u or down in the Waveform Editor window click on the node name in the Name column and release the mouse button The waveform is now highlighted to show the selection Click again on the waveform and drag it up or down in the Waveform Editor Value al 5 95 ns Figure 33 The nodes needed for simulation 4 We will now specify the logic 39 39 and 39 39 values at the output f will be generated automatically by the simulator To make it easy to draw the desired waveforms the Waveform Editor displays by default vertical guidelines and provides a drawing feature quot 39 39 39 Liluu in vicvv gt Snap to Grid Observe also a solid vertical line which can be moved by pointing to its top and dragging it horizontally This reference line is used in analyzing the timing of a circuit move it to the time 0 position The waveforms can be drawn using the Selection Tool which is activated by selecting the icon 3 in the toolbar or the Waveform Editing Tool which is activated by the icon 36 To simulate the behavior of a large circuit it is necessary to apply a suf cient number of input valuations and observe the expected values of the outputs In a large circuit the number of possible input valuations may be huge so in practice we choose a relatively small but representative sample of these input valuations However for our tiny circuit we can simulate all four input valuations given in Figure 11 We will use four 50ns time intervals to apply the four test vectors We can generate the desired input waveforms as follows Click on the waveform name for the x1 node 39 L 439 39 39 v aveionn Editor can be used to draw the desired waveforms 39 39 39 to 01unknnvm X 39 39 don t care DC inverting its existing value INV or de ning a clock waveform Each command can be activated by using the Edit gt Value command or via the toolbar for the Waveform Editor The Edit menu can also be opened by rightclicking on a waveform name Set x to 0 in the time interval 0 to 100 ns which is probably already set by default Next set x to 1 in the time interval 100 to 200 ns Do this by pressing the mouse at the start ofthe interval and dragging it to is end which highlighm the selected interval and choosing the logic value 1 in the toolbar Make x2 1 from 50 to 100 ns and also from 150 to 200 ns which corresponds to the truth table in Figure 11 This should produce the image in Figure 34 Observe that the output f is displayed as having an unknon value at this time which is indicated by a hashed pattern its value will be determined during simulation Save the le lnlewal l Value at D vs Figure 34 Setting of test values 61 Performing the Simulation A 4 39 4 39 39 L 39 4 39 two ways quotquot 39 p is to assume that logic elemenm and intercon nection wires in the FPGA are perfect thus causing no delay in propagation of signals through the circuit This is called fimctiom simulation A more complex alternative is to take all propagation delays into account which leads to timingximula on Typically functional simulation is used to verify the functional correctness of a circuit as it is being designed This takes much less time because the simulation can be performed simply by using the logic expressions that de ne the circuit 611 Functional Simulation To perform the functional simulation select Assignments gt Settings to open the Settings window On the left side ofthis window click on Simulator Settings to display the window in Figure 35 choose Functional as the simulation mode and click OK The Quartus II Simulalul 39 4 r 4 4 39 4 lightwa le Before running the functional simulation it is necessary to create the required netlist which is done by selecting Processing gt Generate Functional Simulation Netlist A simulation run is started by Process ing gt Start Simulation or by using the icon 5 At the end ofthe simulation Quartus 11 software indicates is successful completion and displays a Simulation Report illustrated in Figure 36 Ifyour report window does not show L 39 39 39 39 click on p 39 LU s ct it and choose View gt Fit in Wndow Observe that the output f is as speci ed in the truth table ofFigure 11 Selecl simuialmn Dvlmns simmenanme 1 v Simulalmn maul lighl vwi Add Multiple Files Simulation Denad Run simuialmn until all veclm stimuli ave used r End simuialmn at it much lilienng options Allin Mme Selling Desevivlmn sagging the We ar simuialmn la Devlmm luv the cuuenl Simuialmn locus new Figure 35 Specifying the simulation mode Value at News D D Figure 36 The result of functional simulation 612 Timing Simulation Having ascertained that the designed circuit is functionally correct we should now perform the timing simulation to see how it will behave when it is actually implemented in the chosen FPGA device Select Assignments gt Settings gt Simulator Settings to get to the window in Figure 35 choose Timing as the simulation mode and click OK Run the simulator which wa cluuu in Figure 37 39 a delay of about 6 ns in producing a change in the signal f from the time when the input signals I1 and r2 change their values This delay is due to the propagation delays in the logic element and the wires in the FPGA device Master mg Bar 1 Name Value at n as Figure 37 The result of timing simulation 7 Programming and Con guring the FPGA Device The FPGA TL 1 4 tion le is generated by the Quartus ll Compiler s Assembler module Altera s DE2 board allows the on guration to be done in two different ways knon G S modes The c n guration data is transferred from the as JTA and A o host computer which runs the Quartus 11 software to the boar y means of a cable that connects a USB port on the host computer to the leftmost USB connector on the board To use this connection it is necessary to have the USBBlaster driver installed If this driver is not already installed consult the tutorial Getting Started with Altera s DE2 Board for information about installing the driver Before using the board make sure that the USB cable is properly connected and turn on the power supply switch on the board In the JTAG mode the con guration data is loaded directly into the FPGA device The acronym JTAG stands for Joint Test Action Group This group de ned a simple way for testing digital circuits and loading data into them which became an IEEE standard If the FPGA is con gured in this manner it will retain its con guration as long as the power remains turned on The con guration information is lost when the power is turned o The second possibility is to use the Active Serial AS mode In this case a con guration device that includes some ash memory is used to store the con guration data Quartus ll software places the con guration data into the a 4 Thm u en Thus the FPGA need not be con gured by the Quartus 11 software if the power is turned o and on The choice i annn L The NAP mode while the PROG position selects the AS mode 71 JTAG Programing he r gramming and con guration task is performed as follows Flip the RUNFROG switch into the RUN position Select Tools gt Programmer to reach the window in Figure 38 Here it is necessary to specify the programming hardware and the mode that should be used If not already chosen by default select JTAG in the Mode box Also ifthe USBBlaster is not chosen by default press the Hardware Setup button and select the USBBlaster in the window that pops up as shown in Figure 39 Hardware Setup Ws laste39v Usa ni Made W5 3 Frames 1 r Enable veal lime lSP to allow background Diagramming rm MAX u dew28 Figure 38 The Programmer window 24 e that the con guration le lightsofis listed in the window in Figure 38 Ifthe le is not already listed then click Add File and select it This is a binary le produced by the Compiler s Assembler module which contains the data needed to con gure the FPGA device The extension sofstands for SRAM Object File Note also that the device selected is EP2C35F672 which is the FPGA device used on the DE2 board Click on the ProgramConfigure check box as shown in Figure 40 Hardware Setup Halawae Selma lime Selma Select a Diaglammlng haldwale seluv la use when Diaglammlng devlces m plaglammlng haldwale seluv aWiles anly a the salient plaglammel Wlmaw Eullenlly seiecled haldwale e Avallahle haldwale llems aaa Halawae Figure 39 The Hardware Setup window Haldwale Seluv D ahlasl39e viu Hi Made We a Plaaeee l lquot Enable veal llme lSP la allaw hackglaund plaglammlng llm MAX ll dew28 u Auto Delecl m elanaerle Figure 40 The updated Programmer window Now press Start in the window in Figure 40 An LED on the board will light up when the con guration data n to 0mm n failed then check to ensure that the board is properly powered on 72 Active Serial Mode Programing In this case the con guration data has to be loaded into the con guration device on the DE2 board which is identi ed by the name EPCSIG To specify the required con guration device select Assignments gt Device which leads to the window in Figure 41 Click on the Device and Pin Options bunon to reach the window in Figure 42 Now click on the Configuration tab to obtain the window in Figure 43 In the Con guration device box which may be set to click OK T 39 window in Figure 41 click OK Recompile the designed circuiL Semnge quotgm a deviceyau wam m Aavgei rm camviiahan Device raw Shaw m Avaiiahie devices mi gamuy EycianeH Package Any new 4 j Tavgei device r Am device seiecled by the Filter 6 pemhc device seiecled m Avaiiahie dew228 hst e An y 1 Shaw advanced devices 1 e i we Axaiiahie devices N m 239m 52 baaaon baaaon baaaon 322 baaaon 7n 4 Migvahancampahhimyi e We M gvahanDevmes u M m j I KHH HuHau 4 Jew n migvahan devices seiecled eanee Figure 41 The Device Sem39ngs window Device and Pm Opllnns empiaeemem 1 guayoeeenaneee 1 capaeweiaaama 1 aaaaraeewae Geneva 1 eannamaian I paaawa nee emea pm we We pm vaaaey Speciiy ganmai device apnane These aphans ave nai depenaem an the canhgmahan Scheme npnane ram rmguvan a cieavsh memslaies vsupphed slavi up Din2k LKUSR DEnahie device We ves mumquot DEnahie device We ampm enahie DEVJE DEnahie wumm ampui r Aumusemade HA5 ueey nude 32 m hexadecimai FFFFFFFF Descuvhan Due2A the device in Vestaquot the eanhgmanan waeeeeamamaneaw w a data eum e encaumeved u we Dvhan e tamed artyau must exiemaiiy due2A the device in eaquot We eannamaian i an Ree eanee Figure 42 The Options window 26 ne ceandp om rIs pmmeeemem 1 smmoeeelmeme 1 Eavemlwetaadmg i anemmeeemme Genevai Eanlisuvahan i Piagiamming Fliesi Unused Pms Dual Puipase Pmsl Voltage Speedy me device eamngmenam sememe and me eamngmeimm device Nate Fm macaw H mese settings apply in me FPEA Dialalyve device Eanllguielmn made Eanliguialmn sememe Active Seiial can use Eanliguialmn Device v Eanllguielmn device I A m EPESl EPESO p Eeneiele campiessed hilslieams Epcsso Deseilvlian Speci es me eamngmenam device mein went in use as me meems al eamngmmg me lelgel device e Hemmerquot A l Reset ewe Figure 43 Specifying the con guration device The rest of 39 39 quot 4 4 ahm e for the WM mode Select Tools gt Program mer to reach the window in Figure 38 In the Mode box select Active Serial Programmin 39 e mode from the previously used JTAG mode the po 39 Figure 44 Will appear asking ifyou want to clear all devices Click Yes Now the Programmer window shown in Figure 45 will appear Make sure that the Hardware Setup indicates the USBBlaster If the con guration le is not already listed in the window press Add File The opup box in Figure 46 will appear Select the le lightpofin the directory introtuxoria and click Open As a result the con guration le lightpofwill be listed in the window This is a binary le produced by the Compiler s Assembler module which contains the data to be loaded into the EPCS16 con guration device The extension pof stands for Programmer Object File Upon retuming to the Programmer window click on the ProgramConfigure check box as shown in Figure 47 A yes N Figure 44 Clear the previously selected devices 3 Havdware 52mg USEEINBIIUSB39UI Mode Active Seyial Programming v Plugress I Enable reaHime sp in alluw hackgmund pvugmnm39mg fol MAX u devices Verily Examine Figure 45 The Programmer window with Active Serial Programming selected 1 Program ng Lank w B mtmtutmel v e 1 1 l db My Dnmmenk My Enmpulzl My Nelwulk le name llghl 39 Place les ml wpe PUF Files 119ml V Em Figure 46 Choose the con guration le Quallus I Imlrnlulnnallllgll Ede gum Harassing aals mm Havdwave Setup Ws astevwsa n1 1 ngvess u z 1 Enable veal Mme lSP m allaw hackgmund Dmgvammm rm MAX H dew28 Wu Stan He Lisevcade 4m u Fm Help W255 n firm 1 Figure 47 The updated Programmer window 28


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