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This 11 page Class Notes was uploaded by Shania Cormier on Saturday October 3, 2015. The Class Notes belongs to ECE205 at California State Polytechnic University taught by HalimaEl-Naga in Fall. Since its upload, it has received 17 views. For similar materials see /class/218407/ece205-california-state-polytechnic-university in ELECTRICAL AND COMPUTER ENGINEERING at California State Polytechnic University.
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Date Created: 10/03/15
ECE205 Dr H E1 Naga Homework 1 Solution 1 Refere to Lecture Notes L c z z z z 1 Y D 2fABCP0P2P3P6 lan O A gt 20 1 2 1 3 FABC B gt 2 4 gt 5 2 C gt 2 3 XYiBiDi B i1 P0000 0 0 B B P1001 1 1 I 39 P2010 1 1 I 1 P3011 0 1 I P4100 1 0 0 P5101 0 0 39 P6110 0 0 B Bl P7111 1 1 39 ECE205 Dr H E1 Naga Homework 1 Solution Bi gto o Bi gt1 Di 1 gt1 Bi1 Bi gt2 0 gt2 Bi gt3 B gt3 1 20 I 1 0 39X l D l N ECE205 Dr H E1 Naga Homework 1 Solution ICDU39IAOONAO O 1 2 3 4 5 6 7 ECE205 Dr H E1 Naga Homework 1 Solution E0 ECE205 Dr H E1 Naga Homework 1 Solution ECE205 Dr H E1 Naga Homework 1 Solution 6b ECE205 Dr H E1 Naga Homework 1 Solution ED f 0 module ThreeXElght f In EN 10 1 H 3 x 8 f 1nput0utput declaratlon 12 f4 output 7 0 f 11 input EN 1 input 20 In wire 7 0 f 1N1 1N2 IN3 Wire 20 In Ininot An array of 3 NOT gates not inV20 Ininot In assign IN170 4 InO Inin0t0 assign IN270 2 2 In1 2In7n0t1 assign IN370 4 In2 4 In7n0t2 An array of 8 AND gates and AND70 f 1N3 1N2 1N1 EN endmodule ECE205 Dr H E1 Naga Homework 1 Solution 8 X Cl 4 out Y C2 X Y C1 C2 out x x 0 0 z x 1 0 1 0 H OZ 0 x 1 0 1 L 0Z x 0 0 x H 1 x x 0 L 0 1 x x x 9 a module 1l39UX471out 1n sel output out input 30 1n input 10 sel M39UXZJ Muxl outl 1n01n1 sel0 M39UXZJ Mux2 out2 1n2 1n3 sel0 M39UXZJ Mux3 out out1 out2 sel1 endmodule 10 1 a timescale 1 nsl ns module Fulliadder cout Sum X Y cin output cout output Sum input X Y input cin Wire templ temp2 temp3 temp4 xor 15 xorl templ X Y xor 15 xor2 Sum templ cin nand 10 nandl temp2 X Y nand 10 nand2 temp3 X cin nand 10 nand3 temp4 cin Y nand 10 nand4 cout temp2 temp3 temp4 endmodule timescale 1 nsl ns module Adder74 cout Sum X Y cin output cout ECE2 05 11 a 3 b0 f 8 h65 Dr H E1 Naga Homework 1 Solution output 30 Sum input 30 X Y 39 input cin39 wire 30 ci co assign ci0 cin39 assign ci 3l co20 39 assign cout co339 Fulliadder fadder 30 co Sum X Y ci endmodule timescale l nsl ns module Adder74 cout Sum X Y cin output cout39 output 30 Sum input 30 X Y 39 input cin39 wire col coZ co339 Fulliadder fadderl col Sum0 X0 Y0 Fulliadder fadder2 coZ Suml Xl Yl col Fulliadder fadder3 co3 Sum 2 X2 Y2 endmodule 1 Given the following values what will be the result b 8 bX017102 c 3 bll d 1239bX017102 e 439b1010 g 4 b101 a XaampampbHaampampb Ans X 0 a evaluates to TRUE obviously b evaluates to FALSE because it is nonzero Bits in b which are x or z evaluate to x and are treated as zeros FALSE But there are two ONE bits in b which cause it to evaluate to TRUE It s negation therefore is b Xa0a FALSE TRUE AND ed with FALSE is FALSE The other operand of the OR a ampamp b evaluates to FALSE because a will be zero lled to 8 bits before the AND with b Since the low order bits of a are also zero the AND is FALSE Finally we have FALSE OR ed with FALSE FALSE or zero Ans X 0 3 b0 The bitwise negation ofa is the negation of each bit 3 b111 Since the bitwise XOR of a number with itself is zero X 0 ECE205 Dr H E1 Naga Homework 1 Solution c Xb Ans X 0 b and d look identical but d contains more leading X bits When the case equality operates on different sized operands the shorter operand is padded with leading zeros to the size of the larger operand The padding with zeros causes the equality to fail d Xbd Ans X x An ambiguous bit x or z in either operand causes the inequality operation to return an ambiguous x result eXegtgtlampglfltlt4gtgt4 Ans X 839h05 Parsing the expression we see e gtgt 1 which is 439b1010 shifted right one position with zero lling the vacated bit This gives 4 b0101 This value is AND ed with g 439b101 which gives 4 b0 101 ie AND ed with itself The OR operation is lower in precedence than the parenthesis and shift so the next processing is of f ltlt 4 This shifts 839h65 left 4 bit positions filling the lower 4 bits with zeros The value is now 8 h50 This value is then shifted right 4 bit positions with zeros filling the vacated bits The value is now 8 h05 Finally the OR is performed When a bitwise operation is performed on different sized operands the smaller operand is padded with leading zeros to the size of the larger operand We have 439b0101 839h05 which gets padded to 8 b000070101 839h05 8 h05 8 h05 8 h05 NOTE Ifthese values were assigned to integers instead of to sized registers the left shift of f would not shift bits off the end of the register integers are 32 bits wide and the answer would be 101 8 h65 This would also be true ifX were sized to more than 8 bits since the compiler looks ahead to see the final size available when doing the shifts f X 3 35 0239b0 Bu 2 5th 2 g Ans X 1 This asks for the reduction XOR of a concatenation of replications of numbers The computer will compute the concatenation before doing the XOR but we can be smarter We simplify the computation by distributing the reduction XOR The overall concatenation has three terms ac2 b0 is 1117011700 which has five ones and reduces to one It is replicated an odd number of times and so the reduction XOR remains a one f has an even number of ones so it reduces to zero and no replication can change it The final term is fA 2g famp gig 8 b011071010 A 8 b010170101 8 b001170000 This has two ones and reduces to zero So the final operation is 1 A 0 A 0 1 qed ECE205 Dr H El Naga Homework 1 Solution NOTE There were typos in the problem with curly braces omitted around the rst two replications and a mistake showing X 0 in an earlier version of the answers g X540312 13855 1814 Ans X 3 Working left to right 540 312 228 228 138 90 90 55 35 35 18 l7 l7 l4 3 Remember that the sign ofthe result ofthe modulus is the sign of the rst operand 6 module compare4algoaltb aeqb agtb A B output altb a eqb agtb input 30 A B reg altb wire 30 A always A or B SD eqb agtb w begin altb 0 aeqb 0 agtb 0 if B aeqb 1 else if A gt B agtb 1 else altb 1 end endmodule Alternate ANS module compare4algoaltb aeqb agtb A B output altb aeqb agtb input 30 A B wire altb aeqb agtb wire 30 A B assign altb A lt B 1 assign aeqb A B 1 0 assign agtb A gt B 1 endmodule
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