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Microprocessors and Controllers II

by: Zackary Cronin

Microprocessors and Controllers II CECS 347

Zackary Cronin

GPA 3.89


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This 27 page Class Notes was uploaded by Zackary Cronin on Monday October 5, 2015. The Class Notes belongs to CECS 347 at California State University - Long Beach taught by Staff in Fall. Since its upload, it has received 33 views. For similar materials see /class/218759/cecs-347-california-state-university-long-beach in Computer Science and Engineering at California State University - Long Beach.

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Date Created: 10/05/15
CECS 347 LECTURE 4 82C55 PROGRAMMABLE PERIPHERAL INTERFACE man 820 55A CMOS Programmable June 1998 Peripheral Interface Features Description 0 Pin Compatible with NMOS 8255A The Intersil 82055A is a high performance CMOS version of o 24 P bl quoto P the industry standard 8255A and is manufactured using a r 9ramma e quot 5 selfaligned silicon gate CMOS process Scaled SAJI IV It 0 Fully TTL Compatible is a general purpose programmable O device which may be n used with many different microprocessors There are 24 HO o H39gh Speed No wa39t State operatlon W39th 5MHZ and pins which may be individually programmed in 2 groups of SMHZ 80086 and 80088 12 and used in 3 major modes of operation The high Direct Bit SetReset Capability performance and industry standard configuration of the 82055A make it compatible with the 80086 80088 and 0 Enhanced Control Word Read Capability other microprocessors L7 Process Static CMOS circuit design insures low operating power TTL 25mA Drive Capability on A quot0 ports compatibility over the full military temperature range and bus hold circuitry eliminate the need for pullup resistors The L W Standby Power ICCSB 10HA Intersil advanced SAJI process results in performance equal to or greater than existing functionally equivalent products at ordering Information a fraction of the power PACKAGE RANGE PDIP P LCC Pmouts 82C55A DIP 82C55A CLCC 82C55A PLCC p NW N w EEEEEEHE Eggmggmgl39 quot quot III III 6 5 4 3 2 1 E o 39 RESET GND 38 D0 A1 37 D1 A0 36 D2 PC7 35 D3 34 NC PCG 33 D4 PC5 32 D5 PC4 31D6 PCB 30 D7 IIIIII OGFN QIOGIN NnaxN 1me mmmmmmmmuz uummmgmmmmm lullllllgt nnnnn nnnnn CAUTION These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures File Number 2 httpwwwintersiLcom or 4077279207 Copyright Intersil Corpora ion 1999 82055A Pin Description PIN SYMBOL NUMBER TYPE DESCRIP39ITON V00 26 V00 The 5V power supply pin A 01pF capacitor between pins 26 and 7 is recommended for decoupling GND 7 GROUND D0D7 2734 lO DATA BUS The Data Bus lines are bidirectional threestate pins connected tothe system data bus RESET 35 RESET A high on this input clears the control register and all ports A B C are set tothe input mode with the Bus Holdquot circuitry turned on a 6 CHIP SELECT Chip select is an active low input used to enable the 82C55A ontothe Data Bus for CPU communications W 5 READ Read is an active low input control signal used by the CPU to read status information or data via the data bus W 36 WRITE Write is an active low input control signal used by the CPU to load control words and data intothe 82C55A A0A1 8 9 ADDRESS These input signals in conjunction with the W and Winputs control the selection of one of the three ports or the control word register A0 and A1 are normally connected to the least signi cant bits of the Address Bus A0 A1 PAOPA7 14 3740 lO PORTA 8bit input and output port Both bus hold high and bus hold low circuitry are present on this port PBO PB7 1825 lO PORT B 8bit input and output port Bus hold high circuitry is present on this port PCOPC7 1017 lO PORT C 8bit input and output port Bus hold circuitry is present on this port Functional Diagram 5V IIO POWER PA7PAO SUPPLIES GND BlDIRECTIONAL DATABUS A BUFFER KV k 8Bl39r INTERNAL DATA Bus 82055A Functional Description Data Bus Buffer This threestate bidirectional 8bit buffer is used to interface the 82C55A to the system data bus Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU Control words and status informa tion are also transferred through the data bus buffer ReadWrite and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words It accepts inputs from the CPU Address and Control busses and in turn issues commands to both of the Control Groups CS Chip Select A IoW on this input pin enables the communcation between the 82C55A and the CPU RD Read A IoW on this input pin enables 82C55A to send the data or status information to the CPU on the data bus In essence it allows the CPU to read from the 82C55A WR Write A loW on this input pin enables the CPU to write data or control words into the 82C55A A0 and A1 Port Select 0 and Port Select 1 These input signals in conjunction with the RD and WR inputs control the selection of one of the three ports or the control word register They are normally connected to the least significant bits of the address bus A0 and A1 82C55A BASIC OPERATION INPUTOPERATION A1 A0 RD READ Port A gt Data Bus Port B gt Data Bus Port C gt Data Bus Control Word gt Data Bus OUTPUT OPERATION WRITE Data Bus gt Port A Data Bus gt Port B Data Bus gt Port C Data Bus gt Control DISABLE FUNCTION Data Bus gt ThreeState Data Bus gt ThreeState POWER 5v SUPPLIES GND BlDIRECTIONAL DATA BUS FIGURE1 82C55A BLOCK DIAGRAM DATA BUS BUFFER READNVRITE GROUP A amp B CONTROL LOGIC FUNCTIONS RESET Reset A high on this input initializes the control register to QBh and all ports A B C are set to the input mode Bus hold devices internal to the 82C55A will hold the HO port inputs to a logic 1 state with a maximum hold current of 400uA Group A and Group B Controls The functional configuration of each port is programmed by the systems software In essence the CPU outputs a con trol word to the 82C55A The control word contains information such as mode bit set bit reset etc that ini tializes the functional configuration of the 82C55A Each of the Control blocks Group A and Group B accepts control words from the internal data bus and issues the proper commands to its associated ports Control Group A Port A and Port C upper C7 C4 Control Group B Port B and Port C lower C3 C0 The control word register can be both written and read as shown in the Basic Operation table Figure 4 shows the control word format for both Read and Write operations When the control word is read bit D7 will always be a logic as this implies control word mode information 82055A Ports A B and C The 82055A contains three 8bit ports A B and C All can be configured to a wide variety of functional characteristics by the system software but each has its own special features or personality to further enhance the power and flexibility of the 82C55A Port A One 8bit data output latchbuffer and one 8bit data input latch Both pullup and pulldown bushold devices are present on Port A See Figure 2A Port B One 8bit data inputJoutput latchbuffer and one 8bit data input buffer See Figure 28 Port C One 8bit data output latchbuffer and one 8bit data input buffer no latch for input This port can be divided into two 4bit ports under the mode control Each 4bit port con tains a 4bit latch and it can be used for the control signal output and status signal inputs in conjunction with ports A and B See Figure 28 INPUT MODE MASTER RESET OR MODE CHANGE INTERNAL EXTERNAL DATA IN PORT A PIN INTERNAL DATA OUT LATCHED OUTPUT MODE FIGURE 2A PORTA BUSHOLD CONFIGURATION RESET V5 OR MODE CHANGE P EXTERNAL PORT B C PIN INTERNAL DATA IN INTERNAL DATA OUT LATCHED OUTPUT MODE FIGURE 23 PORT B AND C BUSHOLD CONFIGURATION FIGURE 2 BUSHOLD CONFIGURATION Operational Description MOde Selection There are three basic modes of operation than can be selected by the system software Mode 0 Basic lnputJOutput Mode l Strobed lnputJOutput Mode 2 Bidirectional Bus When the reset input goes high all ports will be set to the input mode with all 24 port lines held at a logic one level by internal bus hold devices After the reset is removed the 82055A can remain in the input mode with no additional ini tialization required This eliminates the need to pullup or pull down resistors in allCMOS designs The control word register will contain QBh During the execution of the system program any of the other modes may be selected using a single output instruction This allows a single 82055A to service a variety of peripheral devices with a simple software maintenance routine Any port programmed as an output port is initialized to all zeros when the control word is written 1 ADDRESS BUS 1 I I 1 CONTROL BUS 1 I I I I 1 DATA BUS 1 CONTROL CONTROL PA7PAO OR IIO OR IIO Bl DIRECTIONAL PB7PBI H 39 PA7PAI CONTROL FIGURE 3 BASIC MODE DEFINITIONS AND BUS INTERFACE CONTROL WORD GROUP B GROUP A MODE SET FLAG 1 ACTIVE FIGURE 4 MODE DEFINITION FORMAT 82055A The modes for Port A and Port B can be separately defined while Port C is divided into two portions as required by the Port A and Port B definitions All of the output registers including the status flipflops will be reset whenever the mode is changed Modes may be combined so that their functional definition can be tailored to almost any lO structure For instance Group B can be programmed in Mode 0 to monitor simple switch closings or display compu tational results Group A could be programmed in Mode 1 to monitor a keyboard or tape reader on an interruptdriven basis The mode definitions and possible mode combinations may seem confusing at first but after a cursory review of the complete device operation a simple logical lO approach will surface The design of the 82C55A has taken into account things such as efficient PC board layout control signal defi nition vs PC layout and complete functional flexibility to sup port almost any peripheral device with no external logic Such design represents the maximum use of the available pins Single Bit SetReset Feature Figure 5 Any of the eight bits of Port C can be Set or Reset using a single Output instruction This feature reduces software requirements in controlbased applications When Port C is being used as statuscontrol for Port A or B these bits can be set or reset by using the Bit SetJReset operation just as if they were output ports CONTROL WORD BIT SETRESET FLAG I ACTIVE FIGURE 5 BIT SETRESET FORMAT Interrupt Control Functions When the 82C55A is programmed to operate in mode 1 or mode 2 control signals are provided that can be used as interrupt request inputs to the CPU The interrupt request signals generated from port C can be inhibited or enabled by setting or resetting the associated INTE flipflop using the bit setJreset function of port C This function allows the programmer to enable or disable a CPU interrupt by a specific lO device without affecting any other device in the interrupt structure INTE FlipFlop Definition BlT SETINTE is SEI39 Interrupt Enable BlT RESETNTE is Reset Interrupt Disable NOTE All Mask flipflops are automatically reset during mode se lection and device Reset Operating Modes Mode 0 Basic lnputJOutput This functional configuration provides simple input and output operations for each of the three ports No handshaking is required data is simply writ ten to or read from a specific port Mode 0 Basic Functional Definitions Two 8bit ports and two 4bit ports Any Port can be input or output Outputs are latched Input are not latched 16 different lnputJOutput configurations possible MODE 0 PORT DEFINITION A B GROUP A GROUP B PORTC PORTC D4 D3 D1 D0 PORTA Upper PORTB Lower 0 0 0 Output Output 0 Output Output 0 0 1 Output Output 1 Output Input 0 1 0 Output Output 2 Input Output 0 1 1 Output Output 3 Input Input 1 0 0 Output Input 4 Output Output 1 0 1 Output Input 5 Output Input 1 1 0 Output Input 6 Input Output 1 1 1 Output Input 7 Input Input 0 0 0 Input Output 8 Output Output 1 0 0 1 Input Output 9 Output Input 1 0 1 0 Input Output 10 Input Output 1 0 1 1 Input Output 11 Input Input 1 1 0 0 Input Input 12 Output Output 1 1 0 1 Input Input 13 Output Input 1 1 1 0 Input Input 14 Input Output 1 1 1 1 Input Input 15 Input Input 82055A Mode 0 Basic Input RD INPUT S A1 A0 D7D0 Mode 0 Basic Output m D7D0 S A1 A0 OUTPUT Mode 0 Configurations CONTROL WORD 0 CONTROL WORD 2 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 l llllllllllll l lllllllllll PAD PAO 82C55A 82C55A PC4 D7 D7 PCO PBD CONTROL WORD 1 CONTROL WORD 3 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 lllllllllll ll PAD PAO 82C55A 82C55A PC4 D7 D7 PCO PBD 82055A Mode 0 Configurations Continued CONTROL WORD 4 D7 D6 D5 D4 D3 D2 D1 D0 82C55A CONTROL WORD 5 D7 D6 D5 D4 D3 D2 D1 D0 82C55A CONTROL WORD 6 D7 D6 D5 D4 D3 D2 D1 D0 82C55A CONTROL WORD 7 D7 D6 D5 D4 D3 D2 D1 D0 82C55A CONTROL WORD 8 D7 D6 D5 D4 D3 D2 D1 D0 82C55A D7 CONTROL WORD 9 D7 D6 D5 D4 D3 D2 D1 D0 82C55A D7 CONTROL WORD 10 D7 D6 D5 D4 D3 D2 D1 D0 82C55A D7 CONTROL WORD 11 D7 D6 D5 D4 D3 D2 D1 D0 82C55A D7 82055A Mode 0 Configurations Continued CONTROL WORD 12 D7 D6 D5 D4 D3 D2 D1 D0 82C55A CONTROL WORD 13 D7 D6 D5 D4 D3 D2 D1 D0 82C55A CONTROL WORD 14 D7 D6 D5 D4 D3 D2 D1 D0 82C55A D7 CONTROL WORD 15 D7 D6 D5 D4 D3 D2 D1 D0 82C55A D7 Operating Modes Mode 1 Strobed lnpufJOutput This functional configura tion provides a means for transferring lO data to or from a specified port in conjunction with strobes or hand shaking signals In mode 1 port A and port B use the lines on port C to generate or accept these hand shaking signals Mode 1 Basic Function Definitions Two Groups Group A and Group B Each group contains one 8bit port and one 4bit controldata port The 8bit data port can be either input or output Both inputs and outputs are latched The 4bit port is used for control and status of the 8bit port Input Control Signal Definition Figures 6 and 7 STB Strobe Input A loW on this input loads data into the input latch IBF Input Buffer FuII FIF A high on this output indicates that the data has been loaded into the input latch in essence and acknowledg ment IBF is set by m input being low and is reset by the rising edge of the W input MODE 1 PORT A PA7PAO CONTROLWORD D7 D6 D5 D4 D3 D2 D1 DD V v v hm nnnnuuu m 00UTPUT gtINTRA N 2 PC6 PC7 1gt IIO MODE 1 PORT B PB7PBD CONTROLWORD D7 D6 D5 D4 D3 D2 D1 D0 nrmrmnnw 553 m AA A A A PC1 gt IBFB gtINTRB N FIGURE 6 MODE1 INPUT 82055A STB INTR INPUT FROM PERIPHERAL FIGURE 7 MODE 1 STROBED INPUT INTR Interrupt Request A high on this output can be used to interrupt the CPU when and input device is requesting service INTR is set by the condition is a one IBF is a one and INTE is a one It is reset by the falling edge of R D This procedure allows an input device to request service from the CPU by simply strobing its data into the port INTE A Controlled by bit setJreset of PC4 INTE B Controlled by bit setJreset of PC2 Output Control Signal Definition Figure 8 and 9 W Output Buffer Full FF The W output will go IOW to indicate that the CPU has written data out to be specified port This does not mean valid data is sent out of the part at this time since W can go true before data is available Data is guaranteed valid at the rising edge of E See Note 1 The W FF will be set by the rising edge of the W input and reset by W input being low W Acknowledge Input A IOW on this input informs the 82C55A that the data from Port A or Port B is ready to be accepted In essence a response from the peripheral device indicating that it is ready to accept data See Note 1 INTR Interrupt Request A high on this output can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU INTR is set when W is a one OBF is a one and INTE is a one It is reset by the falling edge of WR INTE A Controlled by Bit SetJReset of PC6 INTE B Controlled by Bit SetJReset of PC2 NOTE 1 TO strobe data into the peripheral device the user must operate the strobe line in a hand shaking mode The user needs to send W to the peripheral device generates an m from the pe ripheral device and then latch data into the peripheral device on the rising edge MW MODE 1 PORT A PA7PAO 3 CONTROLWORD D7 D6 D5 D4 D3 D2 D1 D0 ll k gt OBFA ACKA 1 INPUT 0 OUTPUT gt INTRA 2 PC4 PC5 1 il MODE 1 PORT B CONTROL WORD PBLPBD D7 D6 D5 D4 D3 D2 D1 D0 iii gt O X W gt INTRB FIGURE 8 MODE1 OUTPUT 82055A PA7PAO gtc PM 4 STBA CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 P C5 gt IIBFA PC3 gt INTRA 2 1 IIO 8 PC6 PC7 P37 P30 PC1 gt OBFB PC2 1 ACKB PC1 gt INTRB PORT A STROBED INPUT PORT B STROBED OUTPUT Combin applicatIo tWB FIGURE 9 MODE 1 STROBED OUTPUT PA7PAO 8 gt mp PC7 gt OBFA CONTROL WORD WA D7 D6 D5 D4 D3 D2 D1 D0 PC 110 V PC3 gt INTRA nnnnlnnm 2 pm pm PC4 PC5 ltgtIlo 1 INPUT o ourpur P37 P30 E c PC2 STBB PC1 gtBFB Pco gt INTRB PORT A STROBED OUTPUT PORT B STROBED INPUT ations of Mode 1 Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed lO 39 ns FIGURE 10 COMBINATIONS OF MODE 1 Operating Modes Mode 2 Strobed BiDirectional Bus IIO The functional configuration provides a means for communi cating with a peripheral device or structure on a single 8bit bus for both transmitting and receiving data bidirectional bus lO Hand shaking signals are provided to maintain proper bus flow discipline similar to Mode 1 Interrupt gener ation and enabledisable functions are also available Mode 2 Basic Functional Definitions Used in Group A only One 8bit bidirectional bus Port Port A and a 5bit control Port Port C Both inputs and outputs are latched The 5bit control port Port C is used for control and status for the 8bit bidirectional bus port Port A BiDirectional Bus IIO Control Signal Definition Figures 11 12 13 14 INTR Interrupt Request A high on this output can be used to interrupt the CPU for both input or output operations Output Operations OBF Output Buffer Full The OBF output will go loW to indicate that the CPU has written data out to port A ACK Acknowledge A loW on this input enables the threestate output buffer of port A to send out the data Oth erwise the output buffer will be in the high impedance state INTE 1 The INTE flipflop associated with OBF Con trolled by bit setJreset of PC4 Input Operations STB Strobe Input A loW on this input loads data into the input latch IBF Input Buffer Full FF A high on this output indicates that data has been loaded into the input latch INTE 2 The INTE flipflop associated with IBF Controlled by bit setJreset of PC4 82055A CONTROL WORD D D6 D5 D4 D3 D2 D1 Do gt INTRA 1 1 10 10 10 gt O BFA Pc2Pco WA 1 INPUT 0 OUTPUT PORTB 51393quot gt 1 INPUT 0 OUTPUT BFA GROUP B MODE gt o MODE 0 1 MODE 1 3 N PCZ39PCquot 174gtIIO FIGURE11 MODE CONTROL WORD FIGURE12 MODEZ DATA FROM CPU TO 82C55A l tAOB gt 4 tAK I tWOB El 5 i INTR gt n x 1 ST gt tSIB i I tPS p AMP tKD PERIPHEEGIS I 1 39 tpH l 39 tRlB gt DATA FROM DATA FROM PERIPHERAL TO 82C55A 82C55A TO PERIPHERAL 31 DATA FRO 82C55A TO CPU NOTE Any sequence where W occurs before ACK and STB occurs before RD is permissible INTR IBF o MASK o STE 0 W B MASK o ACK o W n 0 FIGURE 13 MODE 2 BIDIRECTIONAL 82055A MODE 2 AND MODE 0 INPUT CONTROLWORD 7 D6 D5 D4 D3 D2 D1 D0 nngtxltgtxltgtxltnn PC3 gt INTRA PA7PAO 8 PC7 gt WA PC6 1 WA PC4 A PC5 gt IBFA 3 PC2Pen 1 IIO PB7PBD MODE 2 AND MODE 0 OUTPUT CONTROLWORD D7 D6 D5 D4 D3 D2 D1 D0 nmxoxoxmn PC2PCB 1 INPUT 0 OUTPUT N WR N PC3 PA7PAO PC7 PC6 PC4 PC5 PC2PCB P37 P30 gt INTRA 8 gt WA 1 WA 1 m gt IBFA 1 IIO 3 MODE 2 AND MODE 1 OUTPUT CONTROLWORD D7 D6 D5 D4 D3 D2 D1 D0 llK X El A 11 C3 gt INTRA PA7PAO PC7 gt WA PC6 1 WA PC4 1 A PC5 gt IBFA PB7PBD 3 gt PC1 gt OBFB PC2 1 ACKB PCD gt INTRB MODE 2 AND MODE 1 INPUT CONTROLWORD D7 D6 D5 D4 D3 D2 D1 D0 ll ll PC3 PA7PAO PC7 PC6 PC4 PC5 PB7PBD PC2 PC1 PCD gt INTRA gt OBFA ACKA 1 STBA gt IBFA lt3 4 STBB gt IBFB gt INTRB FIGURE 14 MODE 2 COMBINATIONS 82055A MODE DEFINITION SUMMARY MODE 0 MODE 2 IN OUT IN OUT GROUPA ONLY PAO In Out In Out 4 PA1 In Out In Out 4 PA2 In Out In Out 4 PA3 In Out In Out 4 PA4 In Out In Out 4 PAS In Out In Out 4 D PA6 In Out In Out lt gt PA7 In Out In Out lt gt PBO In Out In Out PB1 In Out In Out PB2 In Out In Out PB3 In Out In Out Mm 0 Dr Mode 1 PB4 In Out In Out Only PBS In Out In Out PBB In Out In Out PB7 In Out In Out PCO In Out INTRB INTRB lO PC1 In Out IBFB W8 lO PC2 In Out B m8 lO PC3 In Out INTRA INTRA INTRA PC4 In Out A lO W PCS In Out IBFA lO IBFA PCB In Out lO m ACKA PC7 In Out lO WA TA SpeCIal Mode Combination ConSIderations INPUT CONFIGURATION There are several combinations of modes possible For any D7 D6 D5 D4 D3 D2 D1 D0 combination some or all of Port C lines are used for control or status The remaining bits are either inputs or outputs as I 0 I V0 I IBFA IINTEAIINTRAI INTEBI IBFB IINTRBI defined by a Set Mode command v v GROUP A GROUP B During a read of Port C the state of all the Port C lines except the W and lines will be placed on the data OUTPUT CONFIGURATION bus In place of the W and line states flag status will D7 D6 D5 D4 D3 D2 D1 D0 appear on the data bus in the PC2 PC4 and PC6 bit positions as illustrated by Figure 17 Through a Write Port C command only the Port C pins programmed as outputs in a Mode 0 group can be written No other pins can be affected by a Write Port C command nor can the interrupt enable fags be accessed To write to any Port C output programmed as an output in Mode 1 group or to change an interrupt enable flag the SetJReset Port C Bit command must be used V th a SetJReset Port Cea Bit command any Port C ine programmed as an output including IBF and w can be written or an interrupt enable flag can be either set or reset Port C lines programmed as inputs including W and lines associated with Port C fare not affected by a SetJReset Port C Bit command Writing to the correspond ing Port C bit positions of the W and lines with the Set Reset Port C Bit command will affect the Group A and Group B interrupt enable flags as illustrated in Figure 17 IOBFAIINTEAI O I O IINTRAIINTEBIOBFBIINTRBI GROUP A GROVUP B FIGURE 15 MODE1 STATUS WORD FORMAT D7 DB DS D4 D3 D2 D1 D0 IOBFAIINTE1I IBFA IINTE2INTRAI X I X I X I GROUP A GROVUP B Defined by Mode 0 or Mode 1 Selection FIGURE 16 MODE 2 STATUS WORD FORMAT Current Drive Capability Any output on Port A B or C can sink or source 25mA This feature allows the 82C55A to directly drive Darlington type drivers and highvoltage displays that require such sink or source current 82055A Reading Port C Status Figures 15 and 16 In Mode 0 Port C transfers data to or from the peripheral device When the 82C55A is programmed to function in Modes 1 or 2 Port C generates or accepts hand shaking signals with the peripheral device Reading the contents of Port C allows the programmer to test or verify the status of each peripheral device and change the program flow accordingly There is not special instruction to read the status information from Port C A normal read operation of Port C is executed to perform this function INTERRUPT ALTERNATE PORT C ENABLE FLAG POSITION PIN SIGNAL MODE INTE B PC2 ACKB Output Mode 1 or STBB Input Mode 1 INTE A2 PC4 STBA Input Mode 1 or Mode 2 INTE A1 PCB ACKA Output Mode 1 or Mode 2 FIGURE 17 INTERRUPT ENABLE FLAGS IN MODES 1 AND 2 INTERRUPT REQUEST I Applications of the 82055A The 82C55A is a very powerful tool for interfacing peripheral equipment to the microcomputer system It represents the optimum use of available pins and flexible enough to inter face almost any lO device without the need for additional external logic Each peripheral device in a microcomputer system usually has a service routine associated with it The routine manages the software interface between the device and the CPU The functional definition of the 82C55A is programmed by the IO service routine and becomes an extension of the stem software By examining the IO devices interface characteristics for both data transfer and timing and matching this information to the examples and tables in the detailed operational description a control word can easily be developed to initialize the 82C55A to exactly fit the application Figures 18 through 24 present a few examples of typical applications of the 82C55A PC3 MODE1 OUTPUT 82C55A MODE1 OUTPUT P36 11 11111111 1111 11111111 PC1 PC2 PCD DATA R EA DY PAPER FEED FORWARDREV DATA READY ACK HIGH SPEED PRINTER HAMMER RELAYS PAPER FEED FORWARDREV IBBON CARRIAGE SEN 111111 1111111111111111 INTERRUPT 4l REQUEST CONTROL LOGIC AND DRIVERS FIGURE 18 PRINTER INTERFACE 82055A INTERRUPT REQUEST DECODED KEYBOARD MODE 1 INPUT 82C55A BURROUGHS SELFSCAN DISPLAY INTERRUPT FIGURE 19 KEYBOARD AND DISPLAY INTERFACE 12BIT AID MODE 0 CONVERTER OUTPUT DAG 82C55A 8BIT DIA CONVERTER ADC MODE 0 INPUT FIGURE 21 DIGITAL TO ANALOG ANALOG TO DIGITAL INTERRUPT REQUEST FULLY DECODED KEYBOARD MODE 1 INPUT 82C55A TERMINAL ADDRESS MODE 0 INPUT FIGURE 20 KEYBOARD AND TERMINAL ADDRESS INTERFACE INTERRUPT REQUEST CRT CONTROLLER o CHARACTER GEN o REFRESH BUFFER o CURSOR CONTROL 82C55A MODE 0 OUTPUT CURSORIROWICOLUMN ADDRESS HampV FIGURE 22 BASIC CRT CONTROLLER INTERFACE 82055A INTERRUPT REQUEST FLOPPY DISK CONTROLLER OUT 82C55A 0quot SENSOR MODE 0 OUTPUT SELECT CRC FIGURE 23 BASIC FLOPPY DISC INTERFACE INTERRUPT REQUEST B LEVEL PAPER TAPE READER MODE 1 INPUT 82C55A MODE 0 INPUT STEP STROBE MODE 0 OUTPUT STEP STROBE ENABLE STOP FIGURE 24 MACHINE TOOL CONTROLLER INTERFACE 82055A Absolute Maximum Ratings TA 25 C Thermal Information Supply Voltage 80V Thermal Resistance Typical Note 1 eJA eJC Input Output or O Voltage GND05V to VCC05V woeW ESD Classification Class 1 MOOW PDIP Package 50 CW NA Operating Conditions PLCC Package 46 CW NA Voltage Range 45v to 55V mm f ggfnmijgtuurjange 65 Ct 150 0 o t39 T t R paragsgsimpera re ange 0 C to 70 C CDIP Package 175 C o I82C55A 4oocto 85 C PDIP Package 150 C M82C55A 550Cto12soc Maximum Lead Temperature Soldering 10s 300 C PLCC Lead TIps Only Die Characteristics Gate Count 1000 Gates CAUTION Stresses above those listed in Absolute Maximum Ratingsquotmay cause permanent damage to the device This is a stress only rating and operation m 4 39 5 quot A u 39 439 439 39 I 39 39 L39 quot39 quot is not implied NOTE 1 eJA is measured with the component mounted on an evaluation PC board in free air Electrical Specifications VCC 50V 10 TA 0 C to 70 C C82C55A TA 40 c to 85 C 82C55A TA 55 c to 125 c M82C55A LIMITS SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS VIH Logical One Input Voltage 20 V 82C55A C82C55A 22 M82C55A VIL Logical Zero Input Voltage 08 VOH Logical One Output Voltage 30 V IOH 25mA VCC 04 IOH 100JA VOL Logical Zero Output Voltage 04 V IOL 25mA II Input Leakage Current 10 10 uA VIN VCC or GND DIP Pins 5 6 8 9 35 36 IO O Pin Leakage Current 10 10 uA VO VCC or GND DIP Pins 27 34 IBHH Bus Hold High Current 50 400 pA VO 30V Ports A B C IBHL Bus Hold Low Current 50 400 pA VO 10V Port A ONLY IDAR Darlington Drive Current 25 Note 2 4 mA Ports A B C Test Condition 3 ICCSB Standby Power Supply Current 10 uA VCC 55V VIN VCC or GND Output Open ICCOP Operating Power Supply Current 1 mAMHz TA 25 C VCC 50V Typical See Note 3 NOTES 2 No internal current limiting exists on Port Outputs A resistor must be added externally to limit the current 3 ICCOP 1mAMHz of Peripheral ReadWrite cycle time Example 10us O ReadWrite cycle time 1mA 4 Tested as VOH at 25mA Capacitance TA 25 C SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS CIN Input Capacitance 10 pF FREQ 1MHz All Measurements are referenced to device GND CO O Capacitance 20 pF 82055A AC Electrical Specifications VCC 5v10 GND W TA 55 c to 125 c M82055A M82055A 5 TA 4o c to 85 C l82055A l82055A5 TA 0 C to 7o c 082055A 082055A5 82C55A5 82C55A TEST SYMBOL PARAMETER MIN MAX MIN MAX UNITS CONDITIONS READ TIMING 1 tAR Address Stable Before R 0 0 ns 2 tRA Address Stable A er 0 0 ns 3 tRR W Pulse Width 250 150 ns 4 tRD Data Valid From W 200 120 ns 1 5 tDF Data Float A er 10 75 10 75 ns 2 6 tRV Time Between ms andor Ms 300 300 ns WRITE TIMING 7 tAW Address Stable Before R 0 0 ns 8 tWA Address Stable A erm 20 20 ns 9 tVVW W Pulse Width 100 100 ns 10 tDW Data Valid to W High 100 100 ns 11tWD Data Valid A er W High 30 30 ns OTHER TIMING 12 tva W 1 to Output 350 350 ns 1 13th Peripheral Data Before R 0 0 ns 14 tHR Peripheral Data A er 0 0 ns 15 tAK ACK Pulse Width 200 200 ns 16tST STB Pulse Width 100 100 ns 17 tPS Peripheral Data Before STB High 20 20 ns 18 tPH Peripheral Data A er STB High 50 50 ns 19 tAD ACK 0 to Output 175 175 ns 1 20 tKD ACK 1 to Output Float 20 250 20 250 ns 2 21tWOB W1toOBF0 150 150 ns 1 22 tAOB ACK 0 to OBF 1 150 150 ns 1 23tSIB STB0toBF 1 150 150 ns 1 24tRB 1tolBF0 150 150 ns 1 25tRT 0tolNTR 0 200 200 ns 1 26 tSIT STB 1 to INTR 1 150 150 ns 1 27 tAlT ACK 1 to INTR 1 150 150 ns 1 28 thT W 0 to INTR 0 200 200 ns 1 29 tRES Reset Pulse Width 500 500 ns 1 Note NOTE Period ofinitial Reset pulse a er poweron must be at least 50usec Subsequent Reset pulses may be 500ns minimum 82055A Timing Waveforms RR 3 RD NR 13 HR 14 INPUT D7D0 RD 4 tDF 5 FIGURE 25 MODE 0 BASIC INPUT D7D0 EA1Ao OUTPUT FIGURE 26 MODE 0 BASIC OUTPUT IBF INTR INPUT FROM PERIPHERAL tPS 17 FIGURE 27 MODE1 STROBED INPUT 82055A Timing Waveforms Continued twoa 21 tWB 12 FIGURE 28 MODE 1 STROBED OUTPUT DATA FROM CPU TO 82C55A NOTE 1 tAOB gt i 22 4 STB NOTE IBF tAD 19 I I tKD 20 PERIPHEEGIS 39 tPH 18 gt 39 tRIB 24 ATA FRO DATA FROM PERIPHERAL TO 82C55A 82C55A TO PERIPHERAL DATA FROM 82C55A TO CPU FIGURE 29 MODE 2 BIDIRECTIONAL NOTE Any sequence where W occurs before ACK and STB occurs before W is permissible INTR IBF o MASK o STB o W 0 BF 0 MASK 0 ACK 0 E 82055A Timing Waveforms Continued A0A1 E X L tAw 7 I L qNA 8 L tARu L tRAa DATA tRR3 quotRD gt h tDF5 DATA BUS VALID MW 9 FIGURE 30 WRITE TIMING HIGH IMPEDANCE FIGURE 31 READ TIMING AC Test Circuit V1 R1 OUTPUT FROM TEST DEVICE UNDER Pom TEST R2 c1 SEE NOTE NOTE Includes STRAY and JIG Capacitance AC Testing Input Output Waveforms INPUT OUTPUT VIH 04V VOH 15V 15V VIL 04V VOL AC Testing A AC Parameters tested as per test circuits Input RISE and FALL times are driven at 1ns TEST CONDITION DEFINITION TABLE BurnIn Circuits M D82C55A CERDI P F6 1 m F11 F7 a 3 F12 F8 9 m F13 F9 1 F14 F4 a an F2 F3 3 EE F5 GND in F15 F0 3 E F11 F1 E E2 F12 F10 m in F13 F6 m in F14 F7 m E F15 F8 E a F11 F9 in E F12 F10 m E V F6 in E F13 c1 F7 2 F14 g F8 m E F15 F9 m 2 F11 F10 an m F12 NOTES 1 VCC 55vo5v 2 VIH 45V 10 3 VIL o2v to 04V 4 GND 0v M R82C55A CLCC NOTES 1 C1 001uF minimum 2 All resistors are 47kg 5 3 f0 100kHz r 10 4 f1 f02f2f1 2f15f142 82C55A Die Characteristics DIE DIMENSIONS GLASSIVATION 95 X100 x 19 i1 mils Type Si02 Thickness 8kA i1kA METALLIZATION Type Silicon Aluminum WORST CASE CURRENT DENSITY Thickness 11kA i1kA 078 x 105 Acm2 Metallization Mask Layout 82055A W PAO PA1 PA2 PA3 PA4 PA5 PA6 PA7 W d H k 1 24 I1 o I o a o m z 2 llllllllllllllllllllllllll 39 a d f a RESET non GND 0393 D0 A1 39 D1 A0 D2 PC7 4 3 P06 D4 PC5 D5 PC4 DG PCO D7 PC1 VCC Ba 3quot at E B E I I I O l I 39 m 5 a H I I I M PCZ PD3 PBO PB1 PBZ PB3 PB4 PB5 PBS PB7 22 82055A DualInLine Plastic Packages PDIP PLANE I I II I SEATING PLANE I 9A lt C 93 NOTES com 6 E and I lt9 1 Controlling Dimensions INCH In case ofcon ictbetween English and Metric dimensions the inch dimensions control Dimensioning and tolerancing per ANSI Y145M1982 Smbols are de ned in the MO Series Symbol Listquot in Section 22 of Publication No 95 4 Dimensions A A1 and L are measured with the package seated in JEDEC seating plane gauge GS3 5 D D1 and E1 dimensions do not include mold ash or protrusions Mold ash or protrusions shall not exceed 0010 inch 025mm are measured with the leads constrained to be per to datum pen dicu eB and e0 are measured at the lead tips with the leads uncon strained ec must be zero or greater 8 B1 maximum dimensions do not include dambar protrusions Dambar protrusions shall not exceed 0010 inch 025mm N is the maximum number of terminal positions 0 Corner leads 1 N N2 and N21for E83 E163 E183 E283 E426 will have a B1 dimension of 0030 0045 inch 076 114mm E406 JEDEC MS011AC ISSUE B 40 LEAD DUALlNLINE PLASTIC PACKAGE SYMBOL 82C55A Plastic Leaded Chip Carrier Packages PLCC m 0042 107 48 3922 0056 142 PIN 1 IDEN11FIER lt N4465 JEDEC MS018AC ISSUE A an 44 LEAD PLAS11C LEADED CHIP CARRIER PACKAGE 0025 064 R 0045 114 SYM BOL NOTES 0026 066 0032 081 0013 033 10021 053 E0025 064 MIN VIEW A TYP 0045 114 Ml NOTES Controlling dimension INCH Converted millimeter dimensions are not necessarily exact Dimensions and tolerancing per ANSI Y145M1982 Dimensions D1 and E1 do not include mold protrusions Allow able mold protrusion is 0010 inch 025mm per side Dimen sions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line can 5 U I Centerline to be determined where center leads exit plastic body 6 N is the number of terminal positions 82055A Ceramic DualInLine Frit Seal Packages CERDIP c1 LEAD FINISH F406 MlLSTD1835 GDIP1T40 05 CONFIGURATION A 40 LEAD CERAMIC DUALlNLINE FRIT SEAL PACKAGE 1 n n n I BASE c E METAL I SYMBOL NOTES SECTION AA p523 Ia SEATING E A PLANE1 L of I A A Egquot 6 lt in NOTES 1 Index area Anotch or a pin one identi cation mark shall be locat ed adjacent to pin one and shall be located within the shaded area shown The manufacturer s identification shall not be used as a pin one identification mark The maximum limits oflead dimensions b and c or M shall be measured at the centroid of the nished lead surfaces when solder dip ortin plate lead nish is applied N p U a t J L t M applies to lead plating and nish thickness Corner leads 1 N N2 and N21 may be con gured with a partial lead paddle For this con guration dimension b3 replaces dimension b2 This dimension allows for offcenter lid meniscus and glass overrun 39 Dimension 4 U m Dimension Q shall be measured from the seating plane tothe base plane Measure dimension S1 at all four corners N is the maximum number ofterminal positions Dimensioning and tolerancing per ANSI Y145M 1982 Controlling dimension INCH oomxi All lntersil semiconductor products are manufactured assembled and tested under ISOSOOO quality systems certification L I Accordingly he reader is cautioned to verify that data sheets are current before placing orders Information furnished by lntersil is believed to be accurate and reli able However no responsibility is assumed by lntersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which m y u I A o Iquot r a Pn E39quot v39 For 39 39 39 39 see web site Sales Of ce Headquarters NORTH AMERICA EUROPE ASIA lntersil Corporation lntersil SA lntersil Taiwan Ltd Box 883 Mail Stop 53204 Mercure Center Taiwan Limited Melbourne FL 32902 100 Rue de la Fusee 7F6 No 101 Fu Hsing North Road TEL 407 7247000 1130 Brussels Belgium Taipei Taiwan FAX 407 7247240 TEL 32 27242111 Republic of China FAX 32 27242205 TEL 886 2 2716 9310 FAX 886 2 2715 3029 82055A Ceramic Leadless Chip Carrier Packages CLCC J44A MlLSTD1835 CQCC1N44 C5 44 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE SYM BOL NOTES jx45quot gtlt g on o T PLANE 1 E NOTES Metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals 2 Unless otherwise specified a minimum clearance of 0015 inch 038mm shall be maintained between all metallized features eg lid castellations terminals thermal pads etc Fquot Symbol N is the maximum number of terminals Symbols ND and NE are the number ofterminals along the sides of length D and respectively The required plane 1 terminals and optional plane 2 terminals if used shall be electrically connected The corner shape square notch radius etc may vary at the manufacturer s option from that shown on the drawing 4 U m Chip carriers shall be constructed of a minimum of two ceramic layers Dimension A controls the overall package thickness The maxi mum A dimension is package height before being solder dipped 1 9 Dimensioning and tolerancing per ANSI Y145M1982 lt9 Controlling dimension INCH


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