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Advanced Logic Design

by: Lilliana Hilll

Advanced Logic Design CPE 166

Lilliana Hilll

GPA 3.52

Jing Pang

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Jing Pang
Class Notes
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This 32 page Class Notes was uploaded by Lilliana Hilll on Monday October 5, 2015. The Class Notes belongs to CPE 166 at California State University - Sacramento taught by Jing Pang in Fall. Since its upload, it has received 28 views. For similar materials see /class/218800/cpe-166-california-state-university-sacramento in Computer Engineering at California State University - Sacramento.


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Date Created: 10/05/15
i Verilog Handout Dr Pang a Data Values Dara Formaf size base value Possible Values 0 logic 0 false 1 logic 1 True X undefined logic value Z High impedance sfa re Ja cllqunnbers A Single bit l bO 3239b0 4 ha 5 h5 4 hz A 4 bit hex number A 5 bit hex number zero value 32 bits all zeros OOOOOOOOOOOO uuu ZZZZ g Forms of AND amp is a bitwise AND ampamp is a logical AND truefalse 4 blOOO amp 4 bOOOl a 439blOOO ampamp 4 bOOOl b 4 bOOOO l bO H Um rms of OR 9 Fquot 75D H H is a bitwise OR II is a logical OR truefalse 4 b1000 4 blOOO I 439bOOO 4 bOOO r r rm 4 blOOl l bl Equality Operators is logical equality have an unknown x result if any of the compared bits are x or 2 is case equality looks for exact match of bits including X s and 2 s and return only true or false a Not equal operators lt2gtopposite to ltgt opposite to Verilog can be used to describe storage elements and sequential circuits as well So far continuous assignment statements are used in a behavioral description A continuous assignment in Verilog is a statement that executes every time the right hand side of the an assignment changes executes here means executing in simulation Hardware counterpart already simulates that behavior a Continuous assignment The continuous assignment is used to assign a value onto a wire in a module It is the normal assignmentoutside of always blocks Continuous assignment is done with an explicit assign statement or by assigning a value to a wire Note that continuous assignment statements are concurrent and are continuously executed during simulation The order of assign statements does not matter Any change in any of the right hand side inputs will immediately change a left hand side output Continuous statements Wire 10 3 assign a 2 b 01 assign b C amp d using assign statement assign c1 X l y c b gt lt The order fohe assign statements does not nzatfer Structural Model A gel a 317 16 i LI 1 3 I7 591 b T module muxltOUT A B SEL Output OUT input AB m not I5 ltsel n BEL ulslancc narnc and 6 welfaW B V and I7 selib sel n A or I4 OUT selia selib endmoc lul e s Two M UXes module mux2 OUT output IL Ci input 1 0 input SEL AB OUTl OUTEDJI mux hi mu l o endmodul e A OUT AEZL AEO 3 I I SEL BEl BED r SEL SELlI S39I39r39ucfur39al Module examplel module halfadder39 s a b co inpu l39a b ou l39pu l39 5 co wire w0 w1 w2 assign IO a amp b II w0 wZ a I b s 541 amp w2 co 0 endmodule S39I39r39ucfur39al Module examplel module fulladder39 s a b co inpu l39 a b Ci ou l39pu l39 s co wire w0 w1 w2 assign co w1 I w2 halfadder39 i0 cow1 sw0 aa halfadder39 i1 cow2 ss aw0 endmodule ci bb bci i0 a a co HA b b 5 W0 H a co HA ci b s w1 w2 S39I39r39ucfur39al Module examplel Ci a0 module odder 4 s a b co ci inpu f 30 0 b inpu f ci oufpu f 30 5 ou fpufco aquot Wire w0 w1 w2 fullodder39 i0 b l COCWO SSO OOO bb0 C39CI39 fullodder39 i1 COCWl SE11 001 bb1 CI39W0 fullodder39 i2 cow2 ss2 oo2 bb2 ciw1 a2 fullodde i3 C C l SS3 003 bb3 CI39W2 endmodule a3 b3 a Process A process can be viewed as a replacement for continuous assignment statement hat permits considerably greater descriptive power Multiple processes may execute concurrently and a process may execute concurrently with continuous assignment statements ie we can have a continuous statement X outside of the procedure Y executing concurrently with Y a Process Within a process procedural assignment statements which are not continuous assignments are used Because of this the assigned values need to be retained over time This can be achieved by using reg type regStertype rather than wire type a Procedural Assign ments Procedural assignments are assignment statements used within Verilog procedures always blocks Only reg variables can be placed left of the assignment expression in procedures The right hand side of the assignment is an expression which may use any of the operator types we have seen earlier a Process begin procedural assignment statements end assignment statements can be blocking or non blocking Assign ment statements Blocking assignment Uses Next statement has to be executed after the current statement completed sequential execution of statements Non Blocking assignment Uses lt Next statement executes at the same time with the current statement parallel execution of statements a Assignment statements Example Process Exa mple Process begin begin A B lt A C B C lt B end end Example Run Example Run A 1 B 3 C 7 A1B3c7 Begin a Assignment statements i Example Process Example Process begin C B c lt B B A B lt A end end Example Run 1 B 3 C 7 ExampleRun A1B3C7 A A1B1C3 1 C 3 Order does not matter A1B Order matters Process With the always keyword you can make a process like a continuous statement module cir2 w X y module cir1 w X y output W output w input X y input X y reg w assign W X amp y always X or y begin endmodule w X amp y end end module 5 Sequential Design In sequential design that includes flip flops registers etc we will usually use non blocking assignments g Verilog code D flip flop module dffv CLK RESET D Q event control input CLK RESET D statement output Q reg Q always posedge CLK or posedge RESET begin if RESET Q lt process else Q lt D Verilog In the body of a process additional Verilog conditional statements can appear For example if else if condition begin procedural statements end else if condition begin procedural statements end else begin procedural statements end g Seq uence Detector Present Next State Output State x O x 1 x O x 1 A A B O O B A C O O C D C O O D A B O 1 g Seq uence Detector module seqrecv CLK RESET X Y input CLK RESET X output Y reg 10 currentstate nextstate parameter A Z bOO B 2 b01 C 2 b10 D 2 b11 reg Y Seq uence Detector implements state storage always posedge CLK or posedge RESET begin if RESET currentstate lt A else currentstate lt nextstate Seq uence Detector next state functionality implementation always X or currentstate begin case currentstate if X nextsate lt B else nextstate lt A B if X nextstate lt C else nextstate lt A C if X nextstate lt C else nextstate lt D 39 if X nextstate lt B else nextstate lt A Seq uence Detector output functionality implementation always X or currentstate begln case currentstate A Y lt 0 B Y lt 0 C Y lt 0 D ifX1 b1 Y lt 1 b1 else Y lt 1 bO endcase end end module Writing amp Reading SRAM Example 32K x8 SIMI we 09 Function f o 1 Wl39ilt SRAM 1 lout70 1 0 Rem mun140 11 No operation Assume CS0 Outputs welwel uel ue2 swapllone idle 511111 start l stalt 1 mm l start 1 Swap two SRAM contents at address location 15 h66 assign address 15 h 66 alwaysposedge swapisw or negedge swapdone begin if swapdone0 stait lt l bO else stait lt l bl end alwayssta1t or cistate egin if start 0 n7stateltidle else begin case cistate idle nistate lt readil readil nistate lt swap2tol swap2tol nistate lt write72 write72 nistate lt readyff readyff nistate lt idle default nistate lt idle endcase end end alwayscistate begin case cistate idle begin weil ltl b l we72ltl b l oeillt l b l 0e72lt lb 1 swapdonelt lb 1 end readil begin weil lt l b l we72lt l b l oeil lt l39b00e72ltl b l swapdonelt lb 1 end swap2tol begin weillt l 39b0we72lt l b l oeil lt lb 1 0e72lt l 39b0swapd0neltl b 1 end write72 begin weillt l b l we72lt l 39b00eil lt lb 1 0e72lt l b l swapdoneltl b 1 end readyff begin weil ltl b l we72ltl b l oeillt l b l 0e72lt lb 1 swapdonelt l 39b0end default begin weillt l b l we72lt lb 1 oeil ltl b l 0e72lt l b l swapdonelt l b 1 end endcase end alwaysnegedge clk begin if cistate readil templatch lt temp end assign temp cistate readil databus 839b00000000 assign databus cistate readil l cistate swap2t0 l l cistate idle l cistate ready 839bZZZZZZZZ templatch endmodule


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