Digital Logic Design
Digital Logic Design CPEN 214
Christopher Newport University
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Haskell Heaney DVM
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This 40 page Class Notes was uploaded by Haskell Heaney DVM on Monday October 5, 2015. The Class Notes belongs to CPEN 214 at Christopher Newport University taught by Costa Gerousis in Fall. Since its upload, it has received 12 views. For similar materials see /class/219470/cpen-214-christopher-newport-university in Computer Engineering at Christopher Newport University.
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Date Created: 10/05/15
Memory and Programmable Logic Memory Device Device to which binary information is transferred for storage and from which information is available for processing as needed Memory Unit is a collection of cells capable of storing a large quantity of binary information In digital systems there are two types of memories 1 RAM 2 ROM Memory and Programmable Logic 1 RandomAccess MemoryRAM RAM is the place in a computer where the operating system application programs and data in current use are kept so that they can be quickly reached by the computer39s processor 2 Read Only MemoryROM ROM is a type of memory that is as fast as RAM but has two important differences It can not be changed and it retains its contents even when the computer is shutoff It is generally used to start your computer up and load the operating system Using a ROM as a PLD A programmable logic device or PLD is an electronic component used to build digital circuits Before the PLD can be used in a circuit it must be programmed Examples of PLDs programmable logic array PLA programmable array logic PAL and eldprogrammable logic gate array FPGA PAL Program AND fixed OR PLA Program ANDOR RandomAccess Memory Memory unit Stores binary information in groups of bits called words Memory word group of 1 s and 0 s and may represent a number characters instruction or other binarycoded information Most computer memories use words that are multiples of 8 bits byte 32bit word 9 4 bytes 1 data mput lines k addrelts line a Mcmury nml Read a 1 wortls V n hil per VOI39kl NI IlC gt In dam outpul lines Fig 772 Block Diagram 0121 Memory Urut RandomAccess Memory Each word in memory is assigned an address 0 up to 2k 1 k of address llnes Memory address Binary decimal 11100000001 1 100000011111 1 101111111 100010111 0000000010 2 0000110101000110 1111111101 1021 lOlllllUUXXllOlUU 1111111111 1022 lllllillllljl llllllll 1111111111 1023 11011110001011101 Fig 7 Content ofa 1024 X 16 Memory How many bytes is this memory module 2KB RAM Write and Read Operations k mdrcxx m Mcmun um 1le 4 mm H m pm imnl N am mumquot in mg 77 am Dmgmmnfn umurj Um To transfer a new word to be stored into memory 1 Apply the binary address of the word to address lines 2 Apply the data bits that must be stored in memory to the data input lines 3 Activate the write input To transfer a stored word out of memory 1 Apply the binary address of the word to address lines 2 Activate the readinput Memory Types Integrated circuit RAM units are available in two possible operating modes static and dynamic Static RAM SRAM consists of of internal latches that store the binary information The stored information remains valid as long as power is applied to the unit Dynamic RAMDRAM stores the binary information in the form of electric charges on capacitors provided by the MOS transistors The charge on the capacitors tends to decay with time and the capacitors must be periodically recharged by refreshing of the dynamic memory every few milliseconds DRAM offers reduced power consumption large integration of units on chip SRAM is faster has shorter read and write cycles SRAM is used in cache Disadvantages high power consumption low density expensive Memory Hierarchy physical s39ze ofmemory decreases memory access lime Increases Volatile vs NonVolatile Memory RAM static and dynamic is said to be volatile since information is lost when power is turned off Nonvolatile memory retains its information even when power is turned off Magnetic disks stored data is represented by the direction of magnetization CD compact disc is a piece of polycarbonate a type of plastic on which a spiral track has been impressed This spiral track is a series of indentations quotpitsquot separated by flat areas quotlandquot ROM The internal storage elements are set to their values once and after that are only read N W EPROMS and PROMS Erasable Programmable ReadOnly Memory EPROM is a special type of memory that retains its contents until it is exposed to ultraviolet light To write to EPROM you need a special device called a PROM Programmeror PROM burner programmer An EPROM differs from a PROM in that a PROM can be written to only once and cannot be erased EPROMs are widely used in personal computers since they enable the manufacturer to change the contents of the PROM before the computer is actually shipped This means that bugs can be removed and new versions installed shortly before delivery EEPROMS and FLASH Electrically Erasable Programmable ReadOnly Memory EEPROM is like EPROM except that the previously programmed connections can be erased with an electrical signal Flash memory is a type of EEPROM Information stored in ash memory is usually written in blocks rather than a byte or word at a time Virtual Memory With virtual memory the computer can look for areas of RAM that have not been used recently and copy them onto the hard disk This frees up space in RAM to load the new application Because it does this automatically you don39t even know it is happening and it makes your computer feel like is has unlimited RAM space even though it has only 1 GB installed RAM Memory Cell sum R T RcJJ Wmc Rum 39 rile m Loglc diagixim b Block diagram rip5 Mummy mi The storage part of the cell is modeled by an SR latch with associated gates A 1 in the readwrite input provides the read operation by forming a path from the latch to the output A 0 in the readwrite input provides the write operation by forming a path from the input to latch our m mg 7 hangan 1 a mu WRITE operation the data available in the input lines are transferred into the four binary cells of the selected word The memory cells that are not selected are disabled READ Operation the four bits of the selected word go through OR gates to the output terminals Commercial RAM Commercial RAM 9 thousands of words with each word 1 64 bits A memory with 2 words of n bitsword requires kaddress lines that go into a k x 2 decoder mm a m mm u mu Rcud Wm Two Dimensional Decoding L m t M M4 404 rm 1 Vllnll1l0 naminysmmwimamvmhiMLHmH The idea of twodimensional decoding is to arrange the memory cells in an array that is as close as possible to square Use two k2input decoders instead of one k input decoder One decoder performs the row selection and the other the column selection in a two dimensional matrix configuration How many words can be selected ReadOnly Memory ROM Readonly memory is a memory device in which permanent binary information is stored A inputsltaddress a 3quot X quot ROM a u output dala Fig7 ROM Block Diagram The number of words in a ROM is determined from the kaddress input lines needed to specify the 2quot words Why doesn t the ROM have any data inputs ReadOnly Memory ROM A 32 X 8 ROM consists of 32 words of 8 bits each The ve input lines are decoded by into 32 distinct outputs memory addresses using a 25 X 8 decoder Each OR gate has 32 input connections 9 32 X 8 ROM has internal connections 32 X 8 In general a 2k X 7 ROM will have kgtlt 2k decoder and 17 OR gates with 2kgtlt 17 internal connections Fig 740 lnicrnui Lnglc of n 32 x x ROM ReadOnly Memory crosspoth 256 programmable m m lmcrml l Wm zz xgt mm A programmable connection a crosspoint between two lines is logically equivalent to a switch that can be be closed two lines are connected or open two lines are disconnected A switch can be a fuse that normally connects the two points but can be opened by blowing the fuse using a high voltage pulse Programming ReadOnly Memory 1 1 address 3 0 0 4 memory 0 content 0 Fig 77H Programming lie ROM According to Table 773 Output16 can be expressed in sum of minterms as A61413121110 222930 Construc 9 256K X 8 RAM similar to 78 1 How many 64K x 8 RAM chips are needed to provide a memory capacity of 256KB w man lines of the address must be us d t 3 How many lines must be decoded for the chip select inputs of an chips 64K X 8 RAM ch39 Capacty 64K Words of 8 bth eacn How many chwps are needed to construct 256K x 87 wnat S the swze of the decoder 256K X 8 RAM Threestate outputs are connected together to form 8 data output lines mm mm Just one chip select CS will be active at any time R m m RAM requires 18 bit address 16 LSB address are applied to the inputs of each RAM 2 MSB are applied to 2to4 decoder Address bits 16 and 17 are used for chip selection WM m M W 32 X8 ROM cm Fig 740 lnlumal Logic of a 32 X 8 ROM 128 X 8 ROM chi similar to 7 15 In uts 2 x 4 Decoder Outpgs 8 Programmable Logic Device PLD Programmable logic devices PLD are designed with con gurable logic and flipflops linked together with programmable interconnect PLDs provide speci c functions including Devicetodevice interfacing Data communication Signal processing Data display Timing and control operations and almost every other function a system must perform PLDs continued pmgmnunnhlc Inmus OR my ompm in Programmable Icadrnnly mcmmy mm M prugldmmxlble mm 0 l quotmuquot AND army on may MPquot b Prugxummzmle army logic PAL I l prognmmmm programmame 0 I V 39 AND army 0R Army P c Programmable log army FLA product terms Fig 743 Ram Con guralmn nf39l39hree FLU sum terms for Boolean functions for Boolean functions Programmable Logic ARRAY PLA 1 4 crosspoint connected I 4W I I crosspoint disconnected blown fuse C quot B39 A A39 g 744 FLA with 3 lnpul Produm l39crnm and z Ouipuk PLA Programming Table product Inpuw Outputs term B A F1 F2 1 1 0 1 2 1 1 1 1 3 1 1 1 4 0 1 0 1 F11 7714 FLA 111111 3 1111111 4 11111111111 Terms 11111 2 Oulpuls PLA Programming example Implement the following function with a PLA F1 Z0124 Ixc 3 EC 3 FZZ0757677 4 110 111 11 1o 10 111 11 111 391111 l1l11l111 11 11 14111 1 111111 411 Al 7 A B C 1 A R 1 B 3939 FLApm 0111111115 Produm 11111111 10 13911 10111 A I c n Fr 1111 1 1 1 7 1 1 1c 2 1 7 1 1 1 B 3 7 1 1 1 7 1 B L39 1 11 11 o 7 1 F1g 7715 51111111111111 Example 772 Programmable Array Logic PAL The programmable array logic PAL is a logic device with fixed OR array and a programmable AND array It is easier to program but not as flexible as PLA WWW Fwdm m Boolean functions must be simplified to fit into each section 9 product term cannot be shared among two or more gates 390 39 Outputs Inputs 7D I D If w m Fig 74 PAL mm Four Inputs Four 0mm mi 39rliwwac ANDVOR Shucmm Sequential Programmable Logic Devices Simple or Sequential Programmable Logic Device SPLD Includes flipflops and ANDOR array within the IC chip ANILOR army ompms PAL m FLA Fliprl39lops Fig 74 s Sequcmml Prngl ammuhlc Logic Devicc Seguential Programmable Logic A microcell is a section of a SPLD that contains a sumof product combinational logic and a flipflop A commercial SPLD contains 8 10 microcells in an IC package Fig1 Basic Macmcell Logic Complex Programmable Logic Device CPLD Complex Programmable Logic Device CPLD The design of a complete digital system using PLD requires the use of several PLD s in a Complex Programmable Logic Device CPLD integrated on a single chip 10 block provides the interconnections to the IC pins Fig 77 Genuml L my unl lgumuon sW1tch matrix received inputs from 10 and directs them to the individual microcells FieldP 39 39 Gate Array FPGA FieldProgrammable Gate Array FPGA is a VLSI circuit whose function is defined by a user39s program rather than by the manufacturer of the device CPEN431 Depending on the particular device the program is either 39burned39 in permanently or semipermanently as part of a board assembly process or is loaded from an external memory each time the device is powered up The FieldProgrammable Gate Arrays provide the benefits of custom CMOS VLSI while avoiding the initial cost and time delay S nchronous Se uentialLo ic A digital system has combinational logic as well as sequential logic The latter includes storage elements Inpuls Oulpuls Combinationul Circuit cry elements feedback path Fig 571 Block Diagram 0 Sequential Circuil I The binary information stored in the memory elements at any given time defines the state of the sequential circuit at that time I The sequential circuit receives binary information from the external inputs These inputs together with the present state of the storage elements determine the binary value of the outputs Synchronous Seguential Logic A synchronous sequential circuit employs signal that affect the storage elements only at discrete instants of time Synchronization is achieved by a time deVice called clock that provides a periodic train of pulses Storage elements that are used in clocked sequential circuits are called ip ops A ip op is a a binary storage deVice capable of storing one bit of information S nchronousCHockedSe uen alLo k Ompuls 0mm cum pulw a Block mm m liming Lliugmmul am pm Mg 57 3ynchronmus lockcd chucnmlCncm LATCHES The most basic types of ip ops are the latches that operate with signal levels Latches are the building blocks of all ip ops 1 J i if rcsel S R Q Q39 Q 1 n 1 0 0 0 U MlerS l R U 1 u I 0 l 0 U a I anal5 LR 1 I S sel Q l l 0 0 lt unde ned state 3 Logic diagram b Function table Fig 53 SR Latch with NOR Gales Under normal conditions both inputs of the latch remain 0 unless the state has to be changed When S 19 latch to set state Q 1 Q 0 Before R is reset to 1 S must go back to 0 to avoid the occurrence of an undefined state with both outputs 0 S R LATCH with NAND o 5551 3 R 1Q Q Q I n 1 1 1 0 1 aflerS1R0 I i 7 0 1 1 0 i 1 1 0af1erSOR1 l R reset Q 0 U 1 lt unde ned state 11 Logic diagram b Funciion able Fig 374 SR Latch with NAND Gates 0 SR latch with NAND gates requires a 0 signal to change its state 0 The inputs signals for the NAND latch are the complement values used for the NOR latch D LATCH flip op c D Nexl stale of Q 125013131 1 Logic diagram bFunct1un able Fig 56 D Latch How is D latch structurally different than the SR latch D latch eliminates the undesirable condition of the indeterminate state that occurs in the SR latch Q Q 1 IfD 1 Q 19 set state IfD 0 Q 0 9 reset state Symbols for Latches E Fig 577 Graphic Symbols or Latches FlipFlops A ip op is a state of a latch that can be switched by momentary change in the control input This momentary change is called a trigger and the transition it causes is said to trigger the ip op The Dlatch is a ip op that is triggered every time the pulse goes to a high or logic level 1 EdgeTriggered FlipFlop r0 1 latch masxcrl Fig 50 MailerSlave D FlipFlop The circuit samples the D input and changes its output at the negative edge of the clock CLK When the clock is 0 the output of the inverter is 1 The slave latch is enabled and its outpth is equal to the master output Y The master latch is disabled CLK 0 When the CLK changes to highD input is transferred to the master latch The slave remains disabled as long as C is low Any change in the input changes Y but not Q 9 The output of the ip op can change When CLK makes a transition 1 9 0 Po tiveEd eTri ered Fli Flo Fig 5410 DType PosiIiVeAEdgeATriggered FlipFlop IfD Owhen CLK l R 9 0 Q 0 reset state IfD changes While CLK is high 9 ip op Will not respond to the change When CLK R 9 1 ip op Will be in the same state no change in output IfD 1 When CLKI S 9 0 Q 1 set state Gatelevel Minimization I The procedure of simplifying Boolean expressions in 24 is dif cult since it lacks speci c rules to predict the successive steps in the simpli cation process I Alternative Karnaugh Map Kmap Method Kmap method can be seen as a pictorial form of the truth table y 0 1 m0 m1 0 x39y39 x39y m2 quot13 x 1 xy 30 Two variable map Twovariable K MAP L 0 l x 0 xyyy xyy x 1 xy xy y y y 0 l 0 l x a 0 0 1 x 1 1 xll 1k 1 F1xy F2m139 2 m3 Two variable K MAP The three squares can be determined from the intersection of variable x in the second row and variable y in the second column Three Variable K Map How is this map useful I Any two adjacent squares differ by only one variable I From the postulates of Boolean algebra the sum of two minterms in adjacent squares can be simplified to a simple AND term ThreeVariable K Map Examplel F 2m2m3m4m5 x39yz 39 x yzxy39z39xy z x39yz Z39 xy39z Z39 VZ x O 0 O 1 Ej Hg 34 Map for Example 3 FLY y z 22 3 4 5 v xy39 ThreeVariable K Map mm Simplify Fx y z 23467 390 LI 4 Fig 35 Map for Example 32 F39 v z 23 4 67 yr xz ThreeVariable K Map Example 3 Simplify Fx y z Z02456 m0 m1 m3 m2 m4 m5 m7 m6 y y r 0 U 0 I 1 I 10 Fig376 Map for Example 373Fx y z 02416 xy ThreeVariable K Map Example 4 Given FABC A39CA39BAB39CBC a Express F in sum of minterms b Find the minimal sum of products using KMap A39CB B39 A39BC A39B39C A39BCC39A39BCA39BC39 AB39C BCAA39 ABC A39BC a FABC A39B39C A39BC39A39BC AB39C ABC Z12357 ThreeVariable K Map Example 4 continued FA B C ZL2357 m0 m1 m3 m2 m4 m5 m7 m6 BC 3 A00 01 11 10 C Fig3 7 Map for Example 34 A C A7 AB C BC C A B Threevariable K Map Observations Encircling one square represents one mintenn 9 A term of how many literals Two adjacent squares II Four adjacent squares I Eight adjacent squares 9 function equals to FourVariable K Map y y W 0 J U 1 1 1 10 00 w39x y39f w39x39y39 nquotquotyz m Hi my I712 01 nquotrquot39 w xy39 w xyz I1quot39vz39 nu 715 m7 nu 11 wxy39z39 wxy39z wxyz w393939 mm ml ml m 0 wx39y39z39 wx39y39 M39y wx yZ39 I71 714 1111 mm c b Fig 378 Fomrvariable Map FourVariable K Map Example 5 Simplify Fwxyz 201245689121314 v 00 01 ll IO F y w z xz W 00 1 Fig 379 Map for Example 35 Fw x y Z 0L2456s0121314 y w39z39 xz39 FourVariable K Map Example 6 simplify FABCD A B C B CD A BCD AB C F B39D B39C39A39CD Cl C M 00 01 11 10 1 D Fig3710 Map for Example 376 A39B39C39 B39CD A BCD AB C B39D39 B C A39CD39 Fourvariable K Map Observations 0 One square represents one minteim 9 a term of 4 literals 0 Two adjacent squares 9 a term of 3 literals 0 Four adjacent squares 9 a term of 2 literal 0 Eight adjacent squares 9 a term of 1 literal sixteen adjacent squares 9 the function equals to 1 Registers and Counters A register consists of a group of ip ops and gates that affect their transition An nbit register consists of 11bit ip ops capable of storing 11 bits of binary information In addition to ip ops a register may have combinational gates that perform certain data processing tasks A counter is essentially a register that goes through a predetermined sequence of states The gates in the counter are connected in such a way to produce the prescribed sequence of states BINARY RIPPLE COUNTER 7 I 4 I A binary ripple counter consists of a series connection of complementing l ip ops 9 the output of i I each ip op is connected to c the C input of the neXt I higherorder ip op l V 1 Cuunl L I l x Lnum Rutl Ilmcl mum T mummy mwm D nipuups Mg M JBu Binary Ripple Counter 4Bit Register I The common clock input triggers all ip ops on the positive edge of each pulse 9 the binary data available at the 4 inputs are transferred into the register I The four outputs can be sampled to obtain the binary information stored in the register I When the clear input R goes to zero all ip ops are reset register is cleared to 0 s Cluck Clem FM 43 Register Register with Parallel Load When load input 1 9 data transferred into register with neXt clock edge When load input 0 9 outputs of FlipFlops are connected to their inputs Q Why do we want to connect the outputs to the inputs when load input 7 g 672 Hill Rigmermm Pdecl ant Register with Parallel Load Example Design a register with parallel load based on the circuit in Fig 62 that operates according to the following function table t N N V V L glad gap 2 pgmj gm clear gt 0 0 A No change I gaj Dii 4 0 l 0 Clear to 0 7 l X 10 Load input Shift Registers A Shi Register is a register that is capable of shifting its binary information in one or both directions Clack On the leading edge of the first clock pulse the signal on the dataiin is latched in the fust ip op On the leading edge of the next clock pulse the contents of the first ip op is stored in the second ip op and the signal which is present at the dataiin is stored is the first ip op etc Serial Shift Registers Timing Diagram Clock Serial Transfer prevents loss of informationgt Shin wnnol a Block diagram determines when and h w many c39 ck fU fL f 1W7 7 times the registers are shifted Sh comm CLK 7 a 7i T1 T T n Each rising edge thxming diagram OfPulse causes a Fig 64 5mm Tmmmrmm Registerl mregister 3 shift in both registers 8 Serial Transfer Example 1 Register A Register B Initial Value 1 0 1 1 0 0 1 0 After T1 After T2 After T3 7 7 After T4 7 7 Serial Transfer Example 1 contined Register A Register B b a In1t1al Value 1 0 1 0 0 1 0 gt AfterTl 1101 c 1001 c AfterT2 1110 1100 AfterT3 0111 0110 AfterT4 1011 1011 With the rst pulse T1 a the rightmost bit of A is shifted into the leftmost bit of B and b also circulated into the leftmost position ofA At the same time c all bits of A andB are shifted one position to the right Serial Transfer Example 2 Example 2 The content of a 4bit register is initially 1101 The register is shifted 4 times to the right with the serial input being 101101 What is the content of the register after four shifts Ans 1101 SerialParallel Computation Communication between a computer and a peripheral device is usually done serially while computation in the computer itself is usually performed with parallel logic circuitry Computations in the computer are done in parallel because this is a faster mode Serial operations are slower but require less devices Serial Addition Slum u so comrnl a sum mgmm A LK f mm quotmm in Senleer Initially Reg A holds the augend to which another is added B holds the addend the that is added Shift control enables both Reg s and carry Flip Flop so that at the next FL both Reg s are shifted once to the right the sum bit from S enters the leftmost FlipFlop ofA a new carry is transferred to Q and both registers are shifted once to the right Thus the sumis transferreds one at a time into Reg A Parallel Adder vs Serial Adder w w 1 rm Ade Vul lmclm 1 Parallel adder uses parallel loading whereas the serial adder uses shift registers 2 Number of full adder circuit in the parallel adder is equal to the number of bits in the binary numbers Serial adder requires only one full adder and a carry Flip Flop 3 The parallel adder is a combinational circuit whereas the serial adder is a sequential circuit that consists of a full adder and a Flip Flop Universal Shift Register A universal shift register is a bidirectional shift register with parallel load capabilities A A Parallel culpuls At All scml lnpul lor shillrriglll Parallel inputs mm 4Bll Universal Slnfl Regiser W S1 S0 Register Operation 0 0 No change 0 l Shi right 1 0 Shift le l 1 Parallel load When S1 S0 11 the binary information on the parallel input lines is transferred into the register simultaneously at the next clock edge When S1 S0 00 the present value ofthe register is applied to theD inputs ofthe FFs This forms a conductionpath from the output to the input of each FF When S1 S0 01 terminal 1 of the multiplexer inputs has a path to theD inputs of the FFs which causes a shiftright operation with serial input transferred into FFA3 When S1 S0 10 a shiftleft operation results with serial input going into FFAO 15 COUNTERS Why do we need counters Counters in digital circuits may used for 3 functions Timing Building a precision digital clock is an example where a low frequency 10 Hz clock cannot be achieved with a crystal oscillator Sequencing Starting of a rocket motor is an example where the energizing of lel pumps ignition etc must follow a critical sequence Counting Measuring the ow of traf c on a road is an application in which the total number of vehicles passing a certain point needs be counted COUNTERS continued A counter is a register that goes through a sequence of states Counter categories 1 2 Ripple counters Synchronous counters Ripple counters The ip op s output transition triggers other ip ops Synchronous counters A common clock triggers all ip ops simultaneously rather than one at a time in succession as in ripple counters BINARY RIPPLE COUNTER I A binary ripple counter consists of a series connection of complementing ip ops 9 the output of each ip op is connected to the C input of the neXt higherorder ip op Rum mum T mm bl nhD1IpHops Fig 6K 4Brl Binary Ripple Counter BINARY RIPPLE COUNTER L9 0L9 9 Hoooooooo Ot t t t OOO Ot t OOt t OO Ot Ot Ot Ot O 0 l 2 3 4 5 S 7 0 Q0 is complemented with the count pulse Since Q0 goes from 1 to 0 it triggers Q1 and complements it As a result Q1 goes from 1 9 0 which in turn complements Q2 changing it from 0 9 1 Q2 does not trigger Q3 because Q2 produces a positive transition The ip ops change one bit at a time in succession and the signal propagates through the counter in a ripple fashion from one stage to the next PROBLEMS WITH RIPPLE COUNTERS I Asynchronous or ripple counters are airanged in such a way that the output of one ip op changes the state of the next In a long chain of ripple counter stages the last ip op changes its state considerably later than the rst FF due to propagation delays in each stage Problems occur if this delay is longer than the response time of other logic elements connected to the circuit I Synchronous counters overcome the problems of propagation delay and erroneous intermediate states In this type of counter all the FF clock inputs are wired together so the transitions of all stages occur simultaneously SYNCHRONOUS COUNTERS Synchronous counters are different from ripple counters in that the clock is applied to the inputs of all ip ops which triggers all ip ops at the same time If T 0 or J K 0 the ip op does not change state If T 1 or J K 1 the ip op complements Suppose for a 4bit counter 1413121le 0011 the next count is 0100 A0 is always complemented A1 is complemented because the present state of A0 1 A2 is complemented because the present state ofA 1AO 11 A3 is not complemented because the present state ofAzAlA0 011
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