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Computer Architecture

by: Earlene Cremin III

Computer Architecture CPSC 5155G

Earlene Cremin III

GPA 3.91

Edward Bosworth

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Edward Bosworth
Class Notes
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This 97 page Class Notes was uploaded by Earlene Cremin III on Sunday October 11, 2015. The Class Notes belongs to CPSC 5155G at Columbus State University taught by Edward Bosworth in Fall. Since its upload, it has received 20 views. For similar materials see /class/221207/cpsc-5155g-columbus-state-university in ComputerScienence at Columbus State University.


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Date Created: 10/11/15
Modern Computers Circa 2007 Computing machines are very common in a modern industrialized society The number of functions performed by these devices is almost endless Here is a partial list 1 General numerical computation involving both integers and real numbers Device automation and control Message switching including routers and rewalls on the Internet Computer generated graphics Graphics based computer games 9959quot Computer enhanced video How about those extra lines superimposed on football elds Computers come in two broad classes General purpose these are adaptable to a Wide variety of programs Special purpose these are designed for one purpose only 6 g routers Special purpose computers are usually limited to high volume markets It is often easier to adapt a general purpose computer to do the job General Purpose Computers This course will focus on general purpose computers also called Stored Program Computers or Von Neumann Machines In a stored program computer a program and its starting data are read into the primary memory of a computer and then executed Early computers had no memory into which programs could be stored The rst stored program computer designed was the EDVAC designed by John Von Neumann hence the name John Mauchley and J Presper Eckert The Electronic Discrete Variable Automatic Computer was described in a paper published on June 30 1945 with Von Neumann as the sole author The rst stored program computer to become operational was the EDSAC Electronic Delay Storage Automatic Computer completed May 6 1949 This was developed by Maurice Wilkes of Cambridge University in England The rst stored program computer that contained all of the components of a modern computer was the MIT Whirlwind rst demonstrated on April 20 1951 It was the rst to use magnetic core memory Components of a Stored Program Computer The four major components of a modern stored program computer are Jaws The Central Processing Unit CPU The Primary Memory also called core memory or main memory The Input Output system One or more system busses to allow the components to communicate System Level Bus ALU Arithmetic Lngic Unit Major Components De ned The system memory of which this computer has 512 MB is used for transient storage of programs and data This is accessed much like an array with the memory address serving the function of an array index The Input Output system IO System is used for the computer to save data and programs and for it to accept input data and communicate output data Technically the hard drive is an IO device The Central Processing Unit CPU handles execution of the program It has four main components 1 2 3 4 The ALU Arithmetic Logic Unit which performs all of the arithmetic and logical operations of the CPU including logic tests for branching The Control Unit which causes the CPU to follow the instructions found in the assembly language program being executed The register le which stores data internally in the CPU There are user registers and special purpose registers used by the Control Unit A set of 3 internal busses to allow the CPU units to communicate A System Level Bus which allows the top level components to communicate Reality Intrudes Part 1 of Many The design on the previous slide is logically correct but IT WON T WORK IT IS TOO SLOW Problem A single system level bus cannot handle the load Modern gamers demand fast video this requires a fast bus to the video chip The memory system is always a performance bottleneck We need a dedicated memory bus in order to allow acceptable performance Here is a refinement of the above diagram Main Memor Memory Bus CPU Video Display Video Bus System Level Bus This design is getting closer to reality At least it acknowledges two of the devices requiring high data rates in access to the CPU Reality Intrudes Part2 of Many We now turn to commercial realities speci cally legacy 10 devices When upgrading a computer most users do not want to buy all new 10 devices expensive to replace older devices that still function well The 10 system must provide a number of busses of different speeds addressing capabilities and data widths to accommodate this variety of 10 devices Main Memor Memory Bus CPU Video Display Video Bus Here we show the main 10 bus connecting the CPU to the 10 Control Hub ICH which is connected to two 10 busses one for slower older devices one for faster newer devices The Memory Component The memory stores the instructions and data for an executing program Memory is characterized by the smallest addressable unit Byte addressable the smallest unit is an 8 bit byte Word addressable the smallest unit is a word usually 16 or 32 bits in length Most modern computers are byte addressable facilitating access to character data Logically computer memory should be considered as an array The index into this array is called the address or memory address A logical View of such a byte addressable memory might be written in code as Const MemSize byte MemoryMemSize Indexed O MemSize l The CPU has two registers dedicated to handling memory The MAR Memory Address Register holds the address being accessed The MBR Memory Buffer Register holds the data being written to the memory or being read from the memory This is sometimes called the Memory Data Register The Simplistic Physical View of Memory I call this the linear vievrf as memory is still modeled as one large linear army N bits 2 N Lines 2 x M MAR Nm2N 39 Decoder MBR M bits The Nihit address selects one of the 2N entities numbered 0 through 2N7 1 Read sequence First address to MAR command a READ then copy the contents of the MBR Write sequence First address to MAR data to the MBR then command a WRITE This is logically correct but dif cult to implement at an acceptable price Multi Level Memory What we want is a very large memory in which each memory element is fabricated from very fast components But fastmeans expensive What we can afford is a very large memory in which each memory element is fabricated from moderately fast but inexpensive components Modern computers achieve good performance from a large moderately fast main memory by using two levels of cache memories called Ll and L2 These work due to an observed property of programs called the locality principle A typical arrangement would have a large L2 cache and a split Ll cache The Ll cache has an Instruction Cache and a Data Cache Level 1 amp Level 2 Main Cache I Memory MB 16KB lorZ I Cache Each Note that the Instruction Cache I Cache does not write back to the L2 cache Organization of Primary Memory We turn our attention again to the primary memory When we left it we had a linear View with an N to 2N decoder We shall study decoders in a later class At present it should be obvious that construction of a 32 to 4294967296 decoder would be very difficult Memory on all modern computers is obViously built from smaller chips Each of these chips will be constructed from a number of smaller chips For example a 1 GB memory might have four 256 MB memory modules Cl C EDDUEDD IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII Connector Each 32 MB chip would be organized as eight 32 Mb chips Each 32 Mb chip is organized as an 8192 by 4096 array 32MB memory chip Primary Memory 9 4 Also called core memory store or storage Beginning with the MIT Whirlwind and continuing for about 30 years the basic technology for primary memory involved cores of magnetic material ImpHumanssnnarzamnsenmmemnryhrml Virtual Memory All modern computer systems use virtual memory At various times in the course we shall give a precise de nition but here is the common setup Main Memory 4 Kb SRAM buffer 16 Mb chip 4K Rows of 4Kb each 64 bit 8way interleaved byte addressable memory 16 MB Databurst System Disk DRAM Cache 320 GB SATA Drive In M87Windows the area of the system disk that handles virtual memory is called the paging le My system has a 768 MB paging le The Central Processing Unit CPU Traditionally the CPU is considered as having four main components Instruction Register Register Set Control Signals Control Unit The Arithmetic Logic Unit The three bus structure that feeds the ALU and accepts its results The control unit that interprets the machine language The register set containing both general purpose user registers and special purpose registers The latter include the Memory Address Register MBR the Memory Buffer Register PC the Program Counter pointing to the next instruction lR the Instruction Register holding the current instruction hmmH Memory Creeps onto the CPU Chip Modern computers such as the P4 have placed both L1 caches and the L2 cache on the CPU chip itself Here is a picture of the P4 chip annotated by Intel In older computers the main difference between CPU registers and memory was that the registers were on the chip and memory was not This no longer holds Memory on the CPU Chip Part 2 With two Ll caches the I cache and the D cache and the L2 cache on the CPU chip we look for another difference to distinguish user registers from memory The main difference is historical It has to do with the way that the assembly language program accesses the device There are register speci c instructions and memory speci c instructions A modern computer Pentium series excepted will have between 8 and 32 user registers These store temporary results for computations The Pentium register set EAX EBX ECX and EDX is rather unusual and would be cheerfully ignored were the Pentium not such an important design Modern computer architecture usually involves a series of design tradeoffs Question Should we place more general purpose registers on the CPU chip or have a larger Ll Data Cache Answer Each provides about the same improvement in performance Flip a coin or use some other criterion The ALU Arithmetic Logic Unit The ALU performs all ofthe arithmetic and logical operations for the CPU These include the following Arithmetic addition subtraction negation etc Logical AND OR NOT Exclusive OR etc B1 B2 B3 This symbol has been used for the ALU since the mid 1950 s It shows to inputs and one output The reason for two inputs is the fact that many operations such as addition and logical AND are dyadic that is they take two input arguments Historical Summary Re ecting on the last 60 years of the history of computing machines we see a development constrained by the available technology and economics We see a constant move towards devices with less cost and physical size more performance and reliability longer time between failures As an example the ENIAC seldom functioned for more than a few hours continuously before it suffered a failure Memory technology is a good example We have four stages 1 No memory ENIAC 2 Very unreliable memory such as mercury delay lines and Williams tubes 3 Very reliable memory specifically magnetic core memory 4 Very reliable and inexpensive memory specifically solid state devices We now begin a look at the computer from a logical view The Fetch Execute Cycle This cycle is the logical basis of all stored program computers Instructions are stored in memory as machine language Instructions are fetched om memory and then executed The common fetch cycle can be expressed in the following control sequence MAR PC The PC contains the address of the instruction READ Put the address into the MAR and read memory IR MBR Place the instruction into the MBR This cycle is described in many different ways most of which serve to highlight additional steps required to execute the instruction Examples of additional steps are Decode the Instruction Fetch the Arguments Store the Result etc A stored program computer is often called a von Neumann Machine after one of the originators of the EDVAC This Fetch Execute cycle is often called the von Neumann bottleneck as the necessity for fetching every instruction from memory slows the computer Avoiding the Bottleneck In the simple stored program machine the following loop is executed Fetch the next instruction Loop Until Stop Execute the instruction Fetch the next instruction End Loop The rst attempt to break out of this endless cycle was instruction prefetch fetch the next instruction at the same time the current one is executing As we can easily see this concept can be extended Instruction Level Parallelism Instruction Prefetch Break up the fetchrexecute cycle and do the two in parallel This dates to the IBM Stretch 1959 The prefetch buffer is implemented in the CPU with onrchip registers The prefetch buffer is implemented as a single register or a queue The CDC76600 buffer had a queue oflength 8 I think Think of the prefetch buffer as containing the IR Instruction Register When the execution of one instruction completes the next one is already in the buffer and does not need to be fetched Any program branch loop structure conditional branch etc will invalidate the contents of the prefetch buffer which must be reloaded Instruction Level Parallelism Pipelining Better considered as an assembly line SI 82 83 S4 85 Instruction Instruction Operand Instruction Write fetch gt decode gt fetch execution gt back unit unit unit unit unit s1IEIIEI 82 E 83 Equot 842 IE 85 12 3 4 5 6 7 8 9 Time gt A 039 V Note that the throughput is distinct from the time required for the execution of a single instruction Here the throughput is ve times the single instruction rate What About Two Pipelines St 82 83 S4 85 Instruction Operand Instruction Write gt decode gt fetch gt execution gt back Instruction unit unit unit unit fetch Un39t Instruction Operand Instruction Write gt decode gt fetch gt execution gt back unit unit unit unit Code emitted by a compiler tailored for this architecture has the possibility to run twice as fast as code emitted by a generic compiler Some pairs of instructions are not candidates for dual pipelining C A B D A 0 C Need the new value of C here This is called a RAW Read After Write dependency in that the value for C must be written to a register before it can be read for the next operation Stopping the pipeline for a needed value is called stalling Superscalar Architectures Having 2 4 or 8 completely independent pipelines on a CPU is very resource intensive and not directly in response to careful analysis Often the execution units are the slowest units by a large margin It is usually a better use of resources to replicate the execution units 81 Instruction Instruction fetch decode unit unit What Is Executed The Idea of Multilevel Machines In discussing the fetch execute cycle we claimed that each instruction is fetched and executed We now ask about the type of instruction In order to answer this question more precisely we introduce the idea of a multilevel machine and multiple levels of computer languages We begin this discussion by discussing three levels of languages High Level Language English like statements Z X Y Assembly Language Mnemonic codes Load X Add Y Store Z Machine Language Binary numbers 0X1 100 Here shown in 0X3 101 hexadecimal form 0X2102 The machine language used in this example is the MARIE design CPSC 2105 The Multilevel Machine Following Andrew Tanenbaum we de ne a four level machine Each level of the machine corresponds to a language level Machine Language Language Type M3 L3 High level language such as C or Java M2 L2 Assembly language M l L l Binary machine language M0 Control Signals Microarchitecture level Following Tanenbaum we de ne a virtual machine as a hypothetical computer that directly executes language at its level For example M3 as a virtual machine directly executes high level language programs The student should be aware that there is another very important use of the term virtual machine with an entirely different de nition We use that later 1 Structured Computer Organization 5th Edition by Andrew S Tanenbaum ISBN 0 l3 148521 0 Dr Tanenbaum de nes six levels Options for Executing a High Level Language Program There are three options for executing a L3 program Each has been tried Direct Execution Translation Interpretation Example This has been tried with the FORTH and LISP languages This is much less exible than the other two approaches much more dif cult to implement and less ef cient Translate the L3 program to a lower level language such as L2 or L1 The lower level languages are much more based on the computer hardware and easier to execute For a HLL this step is called compilation Write a program in a lower level language either L2 or L1 that takes the L3 program as input data and causes the computer to achieve the desired effect The J VM Java Virtual Machine is a virtual machine that appears to execute the Java program directly In actual fact it translates the Java code into byte code and interprets that byte code Levels from the Bottom Up The lowest levels of the computer were not shown on the above diagram These are the digital logic level and the analog devices upon which the level is based The microarchitecture level the rst real level shows all of the components of the CPU ALU Control Unit internal busses user registers control registers the set of control signals as well as the method of generating these signals At this level the registers are connected to the ALU to form a data path over which the data ow registers to ALU then ALU back to a register At this level the basic design question is how to build the control unit The ISA Instruction Set Architecture the next level up describes the binary machine language instructions their mnemonic representations and the general purpose registers that can be accessed by a machine language program The Higher Level Language level the top level represents the view of the Instruction Set Architecture as seen through the compiler or interpreter for the higher level language How Does the Control Unit Work The binary form of the instruction is now in the IR Instruction Register The control unit decodes that instruction and generates the control signals necessary for the CPU to act as directed by the machine language instruction The two major design categories here are hard wired and microprogrammed Hardwired The control signals are generated as an output of a set of basic logic gates the input of which derives om the binary bits in the Instruction Register Microprogrammed The control signals are generated by a microprogram that is stored in Control Read Only Memory The microcontroller fetches a control word from the CROM and places it into the uMBR from which control signals are emitted The microcontroller can almost be seen as a very simple computer within a more complex computer This simplicity was part of the original motivation How to Handle Complexity in a HLL Modern computer design practice is driven by the fact that almost all programs including Operating Systems are written in a HLL High Level Language For interpreted programs the interpreter itself is written in a HLL Almost everything executing on a modern computer is thus the output of a compiler We now adjust the ISA to handle compiler output But where do we put the complexity associated with processing a modern HLL We could have a straightforward compiler that emitted complex machine language instructions for execution at the microarchitecture level This approach requires a very sophisticated control unit which is hard to design We could have a very complex compiler still easy to write that emitted more machine language instructions each of which was very simple This approach allows a very simple control unit which is easy to design and test A hard wired control unit for the complex ISA of the rst approach was found to be very dif cult to design and test For that reason a simpler micro control unit was designed and microprogrammed Modern Design Realities Some assumptions that drive current design practice include 1 2 The fact that most programs are written in high level compiled languages The fact that all modern compilers are designed to emit fairly simple machine language instructions assuming a simple ISA The fact that a simpler instruction set implies a smaller control unit thus freeing chip area for more registers and on chip cache The fact that current CPU clock cycle times 025 050 nanoseconds are much faster than memory devices either cache or primary memory The considerable experience in writing sophisticated compilers that can handle very complex constructs and emit very ef cient machine code NOTE The appearance of a new memory technology with signi cantly enhanced performance would require a completely new design approach This would be welcome but quite a challenge Sequential Circuits We have spent some tame eonsrolerrng eombrnatronal erreurts We now eonsroler sequentral t th M v A 39 By feedback we mean applylng the output of a erreurt back to rts rnput We eompare the two types ofclrcults Cnmhlnau39nnal Circuits Segumual Cueurts No Memory Memory o lpr ops Fllpr ops may be useol only eombrnauonal gates Combrnauonal gates may be useol No feedback Feedbackls alloweol Output for aglven set of The oroler oflnput ehange Inputs ls molepenolent of ls qurte rmportant and may oroler m whreh these rnputs prooluee srgm eant dlfferences were ehangeol alte the the output output stabrlrzes The followlng gure shows away to eonsroler sequentral erreurts Input Output Cnmlulnnnlnl Lngzo Menan The mput ls fedlnto the eombrnatronal logre AND gates OR gates and NOT gates The eombrnatronal logre on the next uek othe clock The elneklnputrs yery rmportantto the eoneept ofa sequenual erreurt At eaeh ask othe Y 1quot We wateh the state ofthe erreurt ehange from QCT to QCT 1 as the eloekueks We have two topics about sequential circuits to be covered in this section 1 Analysis of sequential circuits 2 Design synthesis of sequential circuits Circuit analysis begins with a circuit diagram or a black box and ends with an identi cation of the sequential circuit implemented by the device 7 normally a truth table The steps are 1 Identify the inputs and the outputs 2 Express each output as a Boolean function of the inputs and the present state QT 3 Identify the circuit if possible Circuit design begins with a complete description of the circuit and ends with a design There are two types of sequential circuits 7 39 an a 39 A 39 circuits do not have a common clock they are faster and harder to design As should be inferred from the previous discussion we shall focus on synchronous circuits The basic building blocks of synchronous circuits are ip ops which should be considered as single bit memory elements each ip op can store either a 0 or a l Flip ops have inputs outputs and state QT QT 0 or QT l The outputs of a ip op at any given time are the present state and its complement QT and Q T There are two standard ways to describe a ip op the characteristic table and the excitation table A characteristic table is a truth table that determines the next state of the ip op in terms of the input and present state An excitation table specifies the input required to produce a desired next state at QT 1 given the present state at QT There are four basic types of ip ops SR JK D and T We shall specify each ip op by the characteristic and excitation tables and ignore the details of its construction The SR ip op has two inputs S and R The clock input is always present and shown here just to be complete We first give the characteristic s Q table as a truth table R QT 1 0 0 QT R Q 0 1 0 l 0 l l 1 Not allowed 7 error Clock The excitation table for the ip op is shown at QT QT l S R the right Note that the table shows what 0 0 0 d inputs are required to get the desired next 0 l l 0 state given the existing present state 1 0 0 1 NOTE We have some new terminology l l d 0 to explain Conslder 1 0 1 QCT0 ands0 andR 1 wlll force QT 1 0 Whatwe are saylnglsthat 50 and R ear be ether 0 or 1 Thus we say 5 0 andR d don39t eare The use 1 hr o deslgn real lrcult to be a 0 or 1 dependlng on whlch ls easler to generate at the tlme Note thatfor an SR lpa op the lnput s 1 andR 1 ls not allowed We shall reserve SR 1 the J39K AJKls an stnh lnputs 11 andK 1 allowed The amh table for aJ39K ls as follows I Q 1 0 0 0 T 0 1 J O 1 0 1 1 1 QTT K Thus 11andK 1eauses the next state to be the complement othe present 0 C state Thls ls more useful Agam uslng the d don39t eare notatlon we de ne the excltatlon table of the QCT QCT 1 J39K lpr op Note that eaeh llne has a 0 don39t eare 1h 11 glvlng us eohsrderable 0 exlblllty rh deslgn wlth J39K39s For thls 1 reason they ar 1 J 0 1 d e my favonte lpr op d O AQ Q W to be QCT 1 1 Ihave two lnput ehorees J I 1 ath 1 forces QCT1QC1quot39039 K 0 forces QCT 1 0 as deslred also as deslred lpr op andthe T Toggle lpr op The tables forthls lpr op are qulte slmple Q Charactenstlc Excltatlon D D ow 1 ea ow 1 D u u u 1 2 l l papa papa u Clad 1 Agmn the ehmetensue and excitation tables fonhls lpr op me quue sunple T T QltT 1 20 em 1 0v o 20 o 0 Clock 1 Q T T 0 0 1 1 1 0 1 1 1 0 As an aside we note that a 1K lpr op can be used to synthesize both a D and a T lps op Masterslave FlipsFlog n r s r r hunt ftom a 1K and an SR lpr op Note that the Inputs to the SR lpr op axe nevex 1 1 e clock signal goes high the e e rm y wthlsasone lpr op a h E 9 quotE1 ths snangement of lps ops So fax all suggesuons have been suly cucults When gwen a eueut diagram the fouowmg steps axe used to begin the analysis z Detenmne the Inputs and outputs ofthe ips ops 4 prosslble1dmufy me cucuIL There are no goodrules fomns step Considex the following enemt taken from Figure 2 18 on page 94 of the textbook Ia39er 39Y L r 39rrY soLL r L circuit The rst step is to deteiniine the equations for z the output and D the input to the ip op By inspection we oletennine the following for the equations Z X 0 Y X 0 Y D X Y NotingthatQY L 39r r39 39 39 tiieuip oph A L 39 39 D ip op X QT D mm 0 0 0 0 hit ea 1 1 1 0 1 1 1 1 1 The output table is similarly constructed x QT z 0 0 1 1 0 1 1 0 hit ea These two tables are combined to fonn the transition table X QT QT 1 z 0 0 0 1 11 1 0 11 1 1 10 The nal step m the proeess may be the ereauon othe state dAagram 10 Atthrs pornt we have a eornp1ete desenpuon othe erreurt Itrnay be possrb1e to proeeed from thrs dAagram to obtarn an understandmg ofwhat the erreurt does 0 from the start unul a 1 15 1nput at whxch urne 1ttransmons to state 1 andremams there Input Q0 Output 0 0 0 For Q0 0 the output 15 x 1 0 1 0 1 1 For Q0 1 the output 15 x39 1 1 0 A verbal A 1 H Mk V m nr nt At the eornp1ernent of a nurnber Frrsteonsro1er a nurnber endmg m 1 say xnxn X2X11 The ones eornp1ernent ofthrs numbens x e 39 z39xr39o ddmg 1 to thrs produees the nurnberxn39xnrr X239X1391 m whreh the 1east srgnr eant 1 15 eopred andthe terrnrnates m a one or more zeroes 1 e rts 1east srgnr eantbrts are 10 0 where the eount rnportant The one39srcomplement ofthrs number wru end wrth 01 1 ero m the ongmal has turnedto a1 But 01 any out ofthe addmon thatprodueed the nghtrmost 1 s v t o the rernam er ofthe cxrcuxt 1t 15 a senal two39srcomplementer Design of Seguential Circuits Having seen how to analyze digital circuits we now investigate how to design digital circuits We assume that we are given a complete and unambiguous description of the circuit to be designed as a starting point At this level most design problems focus on one of two topics moduloN counters and sequence detectors A sequence detector accepts as input a string of bits either 0 or 1 Its output goes to 1 when a target sequence has been detected There are two basic types overlap and non overlap In an sequence detector that allows overlap the nal bits of one sequence can be the start of another sequence Our example will be a 11011 sequence detector It raises an output of 1 when the last 5 binary bits received are 11011 At this point a detector with overlap will allow the last two 1 bits to serve at the first of a next sequence By example we show the difference between the two detectors Suppose an input string 11011011011 11011 detector with overlap X 11011011011 Z 00001001001 11011 detector with no overlap Z 00001000001 The sequence detector with no overlap allowed resets itself to the start state when the sequence has been detected Write the input sequence as 11011 011011 After the initial sequence 11011 has been detected the detector with no overlap resets and starts searching for the initial 1 of the next sequence The detector with overlap allowed begins with the final 11 of the previous sequence as ready to be applied as the first 11 of the next sequence the next bit it is looking for is the 0 Here is an overview of the design procedure for a sequential circuit Derive the state diagram and state table for the circuit 2 Count the number of states in the state diagram call it N and calculate the number of ip ops needed call it P by solving the equation 21quot1 lt N S 2P This is best solved by guessing the value of P 3 Assign a unique Pbit binary number state vector to each state Often the first state 0 the next state 1 etc 4 Derive the state transition table and the output table 5 Separate the state transition table into P tables one for each ip op WARNING Things can get messy here neatness counts 6 Decide on the types of ip ops to use When in doubt use all JK s 7 Derive the input table for each ip op using the excitation tables for the type 8 Derive the input equations for each ip op based as functions of the input and current state of all ip ops 9 Summarize the equations by writing them in one place 10 Draw the circuit diagram Most homework assignments will not go this far as the circuit diagrams are hard to draw neatly V We now do the 11011 sequence detector as an example We shall break some of the above big steps into substeps to make things easier We begin with the formal problem statement Problem Design a 11011 sequence detector using JK ip ops Allow overlap Step 1 7 Derive the State Diagram and State Table for the Problem The method to be used for deriving the state diagram depends on the problem I show the method for a sequence detector At this point in the problem the states are usually labeled by a letter with the initial state being labeled A etc Step 1a 7 Determine the Number of States It can be proven that an Nbit sequence detector requires at least N states to function correctly It can also be shown that a circuit with more than N states is unnecessarily complicated and a waste of hardware thus an Nbit sequence detector has N states We are designing a sequence detector for a 5bit sequence so we need 5 states We label these states A B C D and E State A is the initial state Step 1b 7 Characterize Each State by What has been Input and What is Expected St e at Has Awaiting A 11011 B 1 1011 C 11 011 D 110 11 E 1101 1 Step 1c 7 Do the Transitions for the Expected Sequence Here is a partial drawing of the state diagram It has only the sequence expected Note that the diagram returns to state C after a successful detection the nal 11 are used again Note the labeling of the transitions X Z Thus the expected transition from A to B has an input of 1 and an output of 0 10 The transition from E to C has an output of 1 denoting that the desired 0 0 sequence has been detected 1 Step 1d 7 Insert the Inputs That Break the Seguehee Eaeh state has two 1thes out Me for a 0 The rtote s bel ow 3pr am A State A ts the thttaat state Itts wattartg ort a1 Ktt gets a 0 the rhaehtrte rerrtatrts trt state A and eorttartue o rerrtatrt there wht1e as are thput B If state B gets a 0 the last two btts thputwere 10quot ts does not begtrt the sequertee so the maehtrt oes baekto state A and watts rt the rtext 1 n re 3 our 5 0 a U m a gets a 0 the last four btts thput were 1100 These 4 btts are rtotpart of the sequertee so we start o If state E gets a 0 the last we btts thputwere now These ve btts are not part of the sequertee so start over 21 y 111the we stay at c At E getartg a sequence new we rtote that the lrbtt sutrtx ts a 0 whteh ts not a pre x of the destred sequertee the zrbtt sutrtx ts 10 a1so not a pre x ete Step 1e 7 Generate the State Table wtth Outgut Step 2 7 Determine the Number of FlipFlops Reguired We have 5 states so N 5 We solve the equation 21quot1 lt 5 S 2P by inspection noting that it is solved by P 3 So we need three ip ops Step 3 7 Assign a unique Pbit binarv number state vector to each state The simplest way is to make the following assignments A000 B001 C010 DOll E100 Occasionally a better assignment can be detected by inspection of the next state table I note that the next states in the table cluster into two disjoint sets for X 0 and X 1 For X 0 the possible next states are A and D For X l the possible next states are B C and E For this reason I elect to give even number assignments to states A and D and to give odd number assignments to states B C and E Being somewhat traditional I want to assign the state numbers in increasing order so that we don t get totally confused The assignment is B 001 C 011 Note that states 010 110 and 111 are not used D 100 E 101 Step 4 7 Generate the Transition Table With Output Note that in many designs such as counters the states are already labeled with binary numbers so the state table is the transition table We shall label the internal state by the three bit binary number YzYlYo and use the threebit vectors de ned above Step 4a 7 Generate the Output Table and Equation The output table is generated by copying from the table just completed The output equation can be obtained from inspection As is the case with most sequence detectors the output Z is l for only one combination of present state and input Thus we getZ X 0 Y 0 Y1 0 Y0 This can be simpli ed by noting that the state 111 does not occur so the answer is Z X 0 Y2 0 Y0 0 0 0 0 0 0 0 0 0 0 0 1 Step 5 7 Separate the Transition Table into Three Tables One for Each FlipFlop We shall generate a present state next state table for each of the three ip ops labeled Y2 Y1 and Y0 It is important to note that each of the tables must include the complete present state labeled by the three bit vector YzYlYo PS Next State PS Next State Next State Match Y1 YZOYo 0 Y0 0 1 Before trying step 6 I shall note a quick but often messy implementation We look at an implementation using D ip ops only For each ip op we have the desired next state for each combination of present state and input Remember that the D ip op equation is D QT l ie input to the ip op whatever the next state is to be Thus this design is D2 X OYI X0Y20Y0 D1 X 0Y0 D0 X While this may be an acceptable implementation it is important to complete the original design problem using JK ip ops What we want is input equations for J2 K2 J1 K1 J 0 and K0 Inspection of the above gives little clue for the rst two ip ops but any student recalling the use of a JK ip op to implement a D ip op will see immediately that the input equation for ip op 0 is J 0 X and K0 X Step 6 7 Decide on the tvpe of ip ops to be used The problem stipulates JK ip ops so we use them As an aside we examine the difficulties of designing the circuit with D ip ops Step 7 7 Derive an Input Table for Each FlipFlop using its Excitation Table and Step 8 7 Produce the Input Eguations for Each FlipFlop It is at this point that we rst use the fact that we have speci ed JK ip ops for the design We have already considered a D ip op implementation Because we are using JK ip ops we show the excitation table for a JK ip op QT QT l J K 0 0 d We shall see shortly how the presence of the l d d Don t Care state simpli es design d l d 0 D IOl O 0 l 1 It is at this point that neatness counts For each ip op we shall write out the complete present state and the next state of the speci c ip op We then use the present state and next state of the speci c ip op to determine its required input The problem here is comparing the next state of the ip op to the correct present state First we do Y2 Probably the easiest way to generate this table is to do all of the 0 to 0 transitions rst then the 0 to 1 etc For this ip op be sure to refer back to the Y2 part ofthe PS We now try to produce the input equations for J2 and K2 by simplifying the above columns The best way is to consider rst the X 0 columns then the X 1 columns and nally to combine the two There are formal ways to do this but Itry simple matching 1 If a column has only 0 and d it is matched by 0 2 If a column has only 1 and d it is matched by l 3 Ifthis does not work try a match to one of Y2 Y1 or Y0 Remember the d entries do not have to match anything Consider X 0 In the above for J2 we have only 001 as a real pattern These copy the pattern seen in Y1 so we make the assignment that for X 0 J2 Y1 For X 0 the only pattern seen is a pair of 1 s so for X 0 we set K2 0 X0 Xl J2Y1 J20 thus J2X 0Y1 K2 1 K2 Y0 thus K2 X X0Y0 X Y0 Note the combination rule X oexpression for X 0 Xoexpression for X 1 Applied to J2 the rule gives J2 X oYl X00 X oYl The second simpli cation uses the absorption law X XoY X Y for any X and Y We now derive the input equations for ip op l The patterns are detected rst for X 0 and X l separately and then combined X 0 X 1 J1 0 J1 Y0 K1 1 K1 0 thus J1 XOYO and K1 X We now derive the input equations for ip op 0 YYY X0 Xl The patterns are detected as above X0 Xl J00 J0l K0 1 K0 0 thus J0 X and K0 X as expected Step 9 7 Summarize the Eguations Z XOYZOYO J2 X 0Y1 and K2 X Y0 J1 XOYO and K1 X J0 XandKo X Step 10 7 Draw the Circuit I usually do not ask for this step as it tends to be messy and is always hard to grade The gure on the next page has been added to show a typical drawing of this circuit as implemented by JK ip ops Here 15 the c1rcu1t for the 11011 sequmce detecwr as1mplanented mm J39K 1pr ops Kn X Hae 1 the same 0165191 mpmemed mm D mp 7110p The equauons for 1m 0165191 are D2 D1 IY XI IZI IUY Yu Du More on the Combination Rule Some students have trouble with the combination rule I quote it again give an example and then give a theoretical underpinning for it The rule for combining expressions derived separately for X 0 and X l is X oexpressi0n for X 0 Xoexpressi0n for X 1 The origin of the combination rule is the following observation Consider the Boolean expression J X oA XoB where A and B are any Boolean expressions When X 0 this becomes J loA 00B A and when X 1 this becomes J 00A 10B B We then see that J X oA XoB if and only ifJ A when X 0 and J B when X 1 This simple observation is the source of the combination rule It will always produce a correct result and usually produce the simplest result Suppose we had derived the following patterns for K2 in a problem with three ip ops WhenX 0 K2 l and whenX 1 K2 Y0 The result ofthe combination law is that K2 X ol XoYo X XoYo We shall show in a moment that this expression can be simpli ed to K2 X Y0 The simplest expression obtainable is when the results from the two sides X 0 and X l are the same Then we have the expression X oA XoA X XoA A Two other cases A0 JXOB B 0 J X oA The Absorption Theorem T4a on page 22 can lead to simpli cations that are useful This occurs when either A l or B 1 Thus we can have the two following variants 81 J X XoB simplifies to J X B SZ JX 0AX simplifies to JAX We provide proofs for both of these claims 81 X X0BX B IfX 0 we have 0 00B 0 B or 1 l B which is true IfX lwe have 1 10B l B or0 10B 0 B which istrue S2 X oAXAX IfX 0 we have O oA 0 A 0 or loA 0 A which is true IfX lwe have l oA l A l or lA lwhichistrue Using the first ofthese theorems we find that K2 X ol XoYo X XoYo X Y0 It may be possible to produce a counterexample to the claim that the combination rule produces the simplest result but this author is not able to construct one More on oyecla rW39hat ltls and What 1t 15 not Atths pomt F or an extenlled examplehee we shall use a 1011 sequence detector from state D are not specl ed ths 15 lntmhonal Here we focus on state c and the X0 on system sta s ate c the lasttwo blts were 10 state D the last Lhreeblts were 101 Ifthe systems In stateD and gets a o ourblts elOlon th deslred sequence Ifthe last four bltswec elasttwow e107 1011Seqll meDd l39 go to state c The deslgl rnust reuse Pamal Design Lacluug Final Transmon asmany btts as posstble hmeyennent l detector 7 one alloyylng overlap and one not allowlng oy eclap 00 1011 Sequence Detector W39thout Overlap 1011 Sequence Detector With Overlap partlal results 7 only what to do when the flnall m the sequence 1011 IS detected A Word Ab out Counters and Nurnbenng therr States For thrs example we eonsr ermodulor4 eounters both uprcounters and downrcounters ModuloA uprcounters eount 0 1 2 3 0 1 2 3 0 ete ModuloA downrcounters eount 0 3 2 1 0 3 2 1 0 ete Sequence deteetors sueh as that just studed haye rnpute spem cally represenung the strearn ofbxts to be deteeted Pure eounters do nothaye rnput spemfxcally nerther an uprcounternor a downrcounter has rnput An uprdown eounter does have a smgle rnput table ofa modulor4 down eounter The state table shows the present state and next state PS NS PS Present State 0 3 NSNext State 1 0 2 1 3 2 1n thrs and all eounters the assoeratron of state yeetors to the states 15 formed 0 001 01 2 1o 3 11 Any other assrgnrnent yre1ds a ddfferent eounter Here are the state dagram and state tab1e of arnodu1oA uprdown eounter Here the state tab1e depends on xethe rnput used to spemfy trn PS the eoun g dreetron ext State x 1 0 3 1 2 0 2 3 1 3 Agam the assrgnrnent ofbmary numbers follows a xed and spem c pattern RnTvan TNT 1n um r In any rnodu1oA unt r 1 2 and3 n p hum to rts representatron as an unsrgned bmary number For a modulor4 eounter these assrgnrnents rnust be as follows 7 00 1 01 710 311 Any other assrgnrnentyre1ds a dfferent eounter desrgn t n u r 39 L L 39 39 oftwo roads L and one EW running EastWest The light should be considered as two coupled tra ic lights one called L1 and the other L2 Each ofthe lights or pairs oflights displays the standard sequence Red Green Yellow More complext ic lig ts suc 39 h ignals or advanced green lights can be similarly modeled abut let s keep it simple the wnn ullei Jul We see that there are six states in the system In line with standard binary notation I begin the labeling with state 0 It will be convenient to have state 0 be aRed Red state Thus ht 39 in t d i in 0 and3 with the alias RR We use this fact to comment on an alternate design one which I decline to use A Sixrslale Design A Fiverslale Design At rst look the design on the right appears simpler only having ve states The diagran at right hides one speci c di iculty e the state that follows RR Is it GR or RG7 The design at right calls for the transition RR gt RG to alternate with the transition RR gt GR thus we would need a ip op to rememberwhich transition ms t en last time Each ofthe two designs requires at least three ip ops We go with the easier design on the left At this point r39 r 1 won 39 39 39 39 39 39 39 quot the L circuit v L inpnuaunxeth l r The table at right is the state table with the state number and alias given for both the present and next state We keep the alias for convenience only as we have not resolved the duplicate RR alias At this point we note that we have siX states and are ready for Step 2 Count the FlipFlops We need to use three ip ops P 3 YR Step 3 Assign a Binarv Number to Each State The solution here is obvious 7 we treat each number as a threebit unsigned integer and assign the binary numbers 000 001 010 01 l 100 and 101 At this point we have two binary patterns that are not assigned 110 state 6 and 111 state 7 Although these states are supposedly unreachable in our design I propose to handle them anyway as we are designing a device that is safetycritical This design specifies that the next state following either state 6 or state 7 will be state 0 As a safety consideration we further specify that both states 6 and state 7 display Red on each of the two lights as we consider these to be failure states Following our standard design practice we label the ip ops with the integers 2 l and 0 and call the outputs of the ip ops Q2 Q1 and Q0 as Y is taken to stand for Yellow Step 4 Derive the State Transition Table and Output Table The first step in deriving the output table is to define the output The design calls for two coupled traffic lights each with the standard colors Red Green and Yellow The circuit will thus have siX outputs Rl Gl Yl R2 G2 and Y2 7 the first three outputs to light 1 and the second three outputs to light 2 The output table is somewhat complicated It may seem that we have siX signals to generate based on the three binary values Y2 Y1 and Y0 but we take a shortcut We note that each light is either Red Green or Yellow and when it is not either Green or Yellow it must be Red Thus the only signals we generate directly are Gl Yl G2 and Y2 Here are the output equations G1 Q2 Q1 Q0 G2 Q2 Q1 Q0 Y1Q2 Q1 Q0 Y2Q2 Q1 Qo Rl G1 Yl R2 G2 Y2 If we wanted to provide extra fault tolerance we would demand that when one light is either green or yellow the other must be red thus generating the equations R1 G1 Yl G2 Y2 and R2 G2 Y2 G1 Y1 A bit of re ection will show that even with this design it is possible for one light to show more than one color Here we assume a person seeing both red and green on a traffic light would assume something is very wrong We now consider the state transition table expressed in terms of Q2 Q1 and Q0 Before breaking this into three tables one for each ip op we note the handling of the supposedly nonreachable states 6 and 7 The design here is based on fault tolerance the idea that the circuit should have some ability to restore itself from faulty operation Admittedly the strategy re ected in this design may not be realistic It is shown mostly to draw the student s attention to the concepts and not to present an optimal solution 000 Step 5 Separate the Table into Three Tables One for Each FlipFlop Remember that each table must have a complete description of the present state PS NS PS NS PS Step 6 7 Select the FlipFlop Type and Copy Its Excitation Table Since the JK ip ops seem to be the QT QT 1 most useful type I have selected to use JK s in the design As a reminder 0 I have written the excitation table for 1 this ip op to the right 1 0794171 J 0 l d d D IOl O Step 7 7 Derive the Input Table for Each FlipFlop 2 l Step 8 7 Derive the Input Equation for Each FlipFlop J2Q139Q0 J1Q2quotQ0 J0Q2 Q1 K2Q1Q0 K1Q2Qo K01 Step 9 7 Summarize the Eguations Not needed 7 there are no other equations Step 10 7 Draw the Circuit The circuit is shown on the next page of the notes The diagram has three parts 1 The middle part is the design from steps 8 and 9 of the above work It shows the design of what is essentially a modulo6 counter 2 The top part contains the circuits that implement the equations for R1 Yl G1 etc as found in the first part of step 4 of the design This is essentially the output of the circuit 7 six signals that control six traffic lights 3 The bottom part of the circuit is what provides clock pulses to the modulo6 counter Note that the circuit is a shift register used to provide a clock pulse at irregular intervals at T l T 6 and T 8 providing for unequal length of light phases 5 DQ DQ DQ DQ DQ DQ DQ DQ CLKICLKICLKICLKICLKICLKICLKICLK In this design the mput CLOCK 1s a regular 519131 say onetlck per second The t t m 1 CLOCK Y2 shx causmg an output at T 1 T 6 and T 8 or o It s ths negular output that causes the modulor begms m state 0 RR and moves as follows Regrsters of xpr ops usually D xpr ops To store Nbrts aregrster must have N xpr ops one for T T m3 OUTS Ln thrs example the be regrsterrs rmplemented by four D xpr ops Note the mput CLK eomes from an AND gate that puts 111 out the 1ogrea1 AND ofthe OUT system e1oek Clock andthe LOAD srgna1 When LOAD D Q CLK D Q CLK the n u des e 1 m for LOAD to be 1 for almost D Q OUTl one eloekpulse so that the system e1oek and LOAD are both hrgh for 12 clock cycle Atmrstrmeuneregrsterrs CLK loaded D Q CLK OUT0 LOAD Clark 1113 0 4 4 The gure at nght shows a short hand notauon used when drawrng regrsters that eontarn a number of xpr ops rdentreany con gured It should be obvrous that the L0 gure represents a Aebrt regrster Cluck We now consldex a shgh y more geneml but far mote common case Agam we consldex a Very simple case to make the design a 1m mom obvlous Consldex a xegstex box contammg two 471 mglstexs The mglstexs WI be named R0 and 121 a o calledK 111 selects R1 39 L Tnnd and Select signal IfSelect o neither Ieglstex WI be acuve IfSelect 1 the selected Ieglstex WI be loaded 1fLoad 1 and Read 1fLoad o two connol 5191815 as there me three options fox a Ieglstex 1 Do oth 7 save the cunent contents 2 Copy the m tto the xegastex and possibly change Its contents 3 Copy the xegastex contents to the output Also save the contents We now eonslderthe ldea ofa reglster boxquot thls author39s termlnology Thls ls a eolleeuon e Suppose N 2Kreglsters eaeh holdmg M blts The reglster box has MlnputllneslabeledDT M output n a K reglster seleetllnes labeled Ram Load Seleet and Cloek slgnals For example eonslder a set of 16 reglsters eaeh 324m slnee 2 lo we wouldrepresent Thls ldea ofareglsterbox ls lntrodueedln orderto slmpllfy the logle dlagrams and focus on th hlghrlevel aspeets othe eomputer arehlte draw at lelt wlth basle lpr ops would requlre lpr ops for eaeh of the 16 reglsters or lo 32 2 Clock lpr ops ln all Select Load h w p but we shall eonslder an enabledrhlgh 371078 deeoder as an example R In thls dlagram when Enable 0 all 2 outputs are set to o wlthout reference to the R1 lnputRa Rl and Ru R0 When en bl a e l the seleeted outputls set to l and the others to 0 For example lf Enab Enable 1 R2 0 Rl 0 and Ru 0then Output 0 ls setto l and the others setto 0 box ls eonneetedto the Enable lnput ofa deeoderusedto seleetthe reglster KSeleet 0 then the deeoder ls not enabled and no reglster ls aeuve KSeleet 1 then the deeoderls enabled and the seleetedreglsterls aeuve An alternate deslgn usedln thls textbook ls to dlsallow reglster 0 so that no reglsterls seleeted and aeuve when all reglster seleetlnputs are 0 Register S me Miscellan us Remarks 39 Sincethe u i i we consider a 1bit register Consider the following design The input to this circuit is X When Load 1 output of the and K X as desired The problem arises when the register is to keep its contents and Load The output of K The ip op is cleare the autoforget option input to the ip op is Load JXandKX as de sired a 0 input to the ip op is J 0 and K and the ip op maintains its current state now consider the use of histate buffers to control in ut When Load 1 the circuit operates as desired But consider Load 0 Both 0we aveJ1 and K 1 and that is trouble The bottomline tristates cannot be used on input shrft Regrster We no w eonsrder the followmg erreurt burlt from four D lpr ops rnXar the clock pulse rs glven by Q3T 1 x and QKCT 1 21910 for 0 SK 2 The rnput brts en to be shrlted aeross the four lpr ops henee the name Srnee we don39tlrke to drawtoo many lpr ops we have a symbol for shlftreglsters 33 Y 2 Y1 Y0 The shrltregrsterhas both serral rnputandparallelrnput The X parallel rnput rs through the lrnes Serial labeledby the Y39s anotauo we output ha only Clock n e normally used for output Two eommon modes e parallel m serral out an serral rn parallel out one brt at aume Consrderthe ease ofa eharaeter B39 eomrng rn on a serral rnputlrne The ASCH eharaeter eode for B39 rs 42 hexad y mals t ebrnaryrnputrsoloooolo Thrsrnput After 8 l k l 7 0 lY70Yo0Y30Y20Yl1an rnto the CPU as parallel data For output the eharaeter eoder d Yu 0 Thrs rs then transferred s transferred rn parallel rnto the trCode L e micrormemory for each conkol signal generated We have illustrated mas wim a small MEL c m 1quot 1 c u L A quot quot quot dismte conhol39 39 39 39 39 39 Amn39 39 quot 39 39 39 39 39 L 39 quot 39 39 Isigmls r wider microimemories We just noce the which requirement function m L 39 39 39 m lofbusBl code quot 39 39 39 39 39 130275 Code Signal 000 001 PCgtB1 010 MARgtB1 011 R 1 100 IRgtB1 101 SPgtB1 39 quot a optionthatno quot 39 39 39 39 39 39 Y L39 quot0min onbus 01 39etc quot quot 1 4 39 quot Admin In quot 39 39 39 MianMcmory 105 nun 106 7M 37078 m Decoder 1 PCB1 2 MARB1 3 R131 4 IR OB s SP131 Figure Sample of Vernon N crocoding In his revised example word 105 generates MAR gt B1 and word 105 generates R gt B1 One advantage of encoding the control signals is the unique de nition of the signal for each function As an example consider both the horizontal and vertical encodings for bus B1 In the veibit horizontal encoding we were required to have at most one 1 per microiword An examination of that gure will show that the microiword 10100 would assert the two control signals PC gt B1 and R gt B1 simultaneously causing considerable dif culties In the vertical microcoding example the threeibit microiword with contents 011 causes the control signal R gt B1 and only that control signal to be asserted To be repetitive the code 000 is reserved for not specifying any source for bus B1 in which case the contents of the bus are not speci ed In such a case the ALU cannot accept input from bus B1 The design chosen for the microcode will be based on the fact that four of the CPU units bus B1 bus B2 bus B3 and the ALU can each have only one function For this reason the control signals for these units will be encoded There are seven additional control signals that could be asserted in any combination These signals will be represented in horizontal microcode with one bit for each signal Structure of the Boz S Microcode As indicated above the Boz75 microcode will be a mix of horizontal and vertical microcode The reader will note that some of the encoded elds require 37bit codes and some require 47bit codes For uniformity of notation we shall require that each eld be encoded in 4 bits The requirement that each eld be encoded by a 47bit binary number has no justi cation in engineering practice Rather it is a convenience to the student designed to remove at least one minor nuisance from the tedium of writing binary microcode and converting it to hex Consider the following example taken from the common fetch sequence MBR gt B2 tra2 B3 gt IR A minimaliwidth encoding of this sequence of control signals would yield the following 0 000 110 100 010 000 0000 0000 0000 0000 0000 Conversion of this to hexadecimal requires regrouping the bits and then rewriting 0000 1101 0001 0000 0000 0000 0000 0000 0000 or 0x0 D100 0000 The fouribit constant width coding of this sequence yields the following 0000 0000 0110 0100 0010 0000 0000 0000 0000 0000 0000 This is immediately converted to 0x006 4200 0000 without shuf ing any bits Dispatching the Microcode In addition to microiwords that cause control signals to be emitted we need microiwords to sequence the execution of the microcode This is seen most obviously in the requirement for a dispatch based on the assembly language opicode Let s begin with an observation that is immediately obvious If the microprogrammed control unit is to handle each distinct assembly language opcode differently it must have sections of microprogram that are unique to each of the assembly language instructions The solution to this will be a dispatch microoperation one which invokes a section of the microprogram that is selected based on the 57bit opcode that is currently in the Instruction Register But what is called and how does it return The description above suggests the use of a microisubroutine which would be the microprogramming equivalent of a subroutine in either assembly language or a higher level language This option imposes a signi cant control overhead in the microprogrammed control unit one that we elect not to take The where to return issue is easily handled by noting that the action next after executing any assembly language instruction is the fetching of the next one to execute For reasons that will soon be explained we place the first microoperation of the common fetch sequence at address 0x20 in the micromemory each execution phase ends with go to 0x20 The structure of the dispatch operation is best considered by examination of the control signals for the common fetch sequence F T0 PC gt Bl tral B3 gt MAR READ MAR PC F Tl PC gtBl l gtB2 add B3 gtPC PC PCl F T2 MBR gt B2 traZ B3 gt IR IR MBR F T3 Do something specific to the opcode in the IR In the hardwired control unit the major and minor state registers would play a large part in generation of the control signals for F T3 and the major state register would handle the operation corresponding to dispatch that is selection of what to do next Proper handling of the dispatch in the microprogrammed control unit requires an explicit micrompcode and a slight resequencing of the common fetch control signals Here is the revised sequence F T0 PC gt Bl tral B3 gt MAR READ MAR PC F Tl PC gtBl l gtB2 add B3 gtPC PC PCl F T2 MBR gt B2 traZ B3 gt IR IR MBR Dispatch based on the assembly language opcode F T3 Do something specific to the opcode in the IR The next issue for our consideration in the design of the structure of the microprogram is a decision on how to select the address of the microiinstruction to be executed next after the current microiinstruction In order to clarify the choices let s examine the microprogram sequence for a specific assembly language instruction and see what we conclude The assembly language instructions that most clearly illustrate the issue at hand are the registeritoiregister instructions We choose the logical AND instruction and arbitrarily assume that its microprogram segment begins at address 0x80 a new design to be developed soon will change this and see what we have Were we to base our control sequence on the model of assembly language programming we would write it as follows 0x20 PC gt Bl tral B3 gt MAR READ MAR PC 0x21 PC gt B1 1 B2 add B3 gt PC PC PC 1 0x22 MBR gt B2 traZ B3 gt IR IR MBR 0x23 Dispatch based on the assembly language opcode 0x80 R gt Bl R gt B2 and B3 gt R 0x81 Go to 0x20 While the above sequence corresponds to a coding model that would be perfectly acceptable at the assembly language level it presents several signi cant problems at the microcode level We begin with the observation that it requires the introduction of an explicitly managed microprogram counter in addition to the microimemory address register The second and most signi cant drawback to the above design is that it requires two clock pulses to execute what the hardwired control unit executed in one clock pulse One might also note that the present design calls for using two microiwords addresses 0x80 and 0x81 where one microiword might do This is a valid observation but the cost of memory is far less signi cant than the time cost to execute the extra instruction The design choice taken here is to encode the address of the next microinstruction in each 39 39 uctiou in the 39 r This removes the complexity of managing a program counter and the necessity of the timeiconsuming explicit branch instruction Recasting the example above in the context of our latest decision leads to the following sequence Address Control Signals Next address 0x20 PC gt Bl tra1 B3 gt MAR READ 0x21 0x21 PC gt B1 1 gt B2 add B3 gt PC 0x22 0x22 MBR gt B2 tra2 B3 gt IR 0x23 0x23 Dispatch based on IR3171R27 7 We decide later 0x80 R gt Bl R gt B2 and B3 gt R 0x20 Note that the introduction of an explicit next address causes the execution phase of the logical AND instruction to be reduced to one clock pulse as desired The requirement for uniformity of microcode words leads to use of an explicit next address in every microiword in the micromemory The only microinstruction that appears not to require an explicit next address in the dispatch found at address 0x23 A possible use for the next address eld of the dispatch instruction is seen when we consider the effort put into the hardwired control unit to avoid wasting execution time on a Branch instruction when the branch condition was not met The implementation of this decision in a microprogrammed control unit is to elect not to dispatch to the opcodeispeci c microcode when the instruction is a branch and the condition is not met What we have is shown below Address Control Signals Next address 0x20 PC gt Bl tra1 B3 gt MAR READ 0x21 0x21 PC gt B1 1 gt B2 add B3 gt PC 0x22 0x22 MBR gt B2 tra2 B3 gt IR 0x23 0x23 Dispatch based on IR3171R27 0x20 0x80 R gt Bl R gt B2 and B3 gt R 0x20 The present design places the next address for dispatch when the condition is not met in the eld of the microiword associated with the next address for two reasons 1 This results in a more regular design one that is faster and easier to implement 2 This avoids hard coding the address of the beginning of the common fetch At this point in the design of the microprogrammed control unit we have two distinct types of microoperations a type that issues control signals and a type that dispatches based on the assembly language opcode To handle this distinction we introduce the idea of a micro opcode with the following values at present Micro Op Function 0000 Issue control signals 0001 Dispatch based on the assembly language opcode We have stated that there are conditions under which the dispatch will not be taken There is only one condition that will not be dispatched the assemblyilanguage opcode is 0x0F and the branch condition is not met Before we consider how to handle this situation we must first address another design issue that presented by indirect addressing Handling Defer Consider the control signals for the LDR Load Register assembly language instruction LDR Op Code 01100 Hexadecimal 0x0C F T0 PC gt Bl tral B3 gt MAR READ MAR PC F Tl PC gtBl l gtB2 add B3 gtPC PClt PC1 F T2 MBR gt B2 tra2 B3 gt IR IR MBR F T3 IR gt Bl R gt B2 add B3 gt MAR Do the indexing Here the major state register takes control 1 If the Iibit bit 26 is 1 then the Defer state is entered 2 If the Iibit is 0 then the E state is entered D TO READ Address is already in the MAR D Tl WAIT Cannot access the MBRjust now D T2 MBR gt B2 tra2 B3 gt MAR MAR MBR D T3 WAIT Here the transition is automatic from the D state to the E state E TO READ Again address is already in the MAR E Tl WAIT E T2 MBR gt B2 tra2 B3 gt R E T3 WAIT The issue here is that we no longer have an explicit major state register to handle the sequencing of major states The microprogram itself must handle the sequencing it must do something different for each of the two possibilities indirect addressing is used and indirect addressing is not used Assuming a dispatch to address 0x0C for LDR as it will be done in the final design the current design calls for the following microinstruction at that address Address Control Signals Next address 0x0C IR gt Bl R gt B2 add B3 gt MAR Depends on IR25 Suddenly we need two next addresses one if the defer phase is to be entered and one to be used if that phase is not to be entered This last observation determines the final form of the microprogram each microiword has length 44 bits with structure as shown below In this representation of the microprogram words we use D 0 to indicate that the defer phase is not to be entered and D l to indicate that it should be entered This notation will be made more precise after we explore the new set of signals used to control the sequencing of the microprogram Here we assume no more than 256 microiwords in the control store Microiop B1 B2 B3 ALU M1 M2 D 0 D l 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 8 bit 8 bit Notes 1 The width of each eld is either four or eight bits The main reason for this is to facilitate the use of hexadecimal notation in writing the microcode N The use of four bits to encode only two options for the micrompcode may appear extravagant This follows our desire for a very regular structure 3 The use of D 0 and D l is not exactly appropriate for the dispatch instruction with microiopcode 0001 We shall explain this later 4 The bits associated with the M1 eld are those specifying the shift parameters Bit 3 L R l for a left shift 0 for a right shift Bit 2 A l for an arithmetic shift Bit 1 C l for circular shift Bit 0 Not used 5 The bits associated with the M2 field are Bit 3 READ Indicates a memory reference Bit 2 WRITE Unless READ 1 Bit 1 extend Signiextend contents of IR when copying to B1 Bit 0 0 gt RUN Stop the computer 6 For almost every microiinstruction the two next addresses are identical For these we cannot predict the value of the generated control signal branch and do not care since the next address will be independent of that value 7 The values for next addresses will each be two hexadecimal digits It is here that we have made the explicit assumption on the maximum size of the micromemory Seguencing the Boz S Microprogrammed Control Unit In addition to the assembly language opcode we shall need two new signals in order to sequence the microprogrammed control unit correctly We call these two control signals 1 and S2 because they resemble the control signals 81 and 82 used in the hardwired control unit but are not exactly identical In the hardwired control unit the signal 81 was used to determine whether or not the state following Fetch would again be Fetch This allowed completion of the execution of 14 of the 22 assembly language instructions in the Fetch phase In the microprogrammed control unit the signal 81 will be used to determine whether or not the dispatch microinstruction is executed The only condition under which it is not executed is that in which the assembly language calls for a conditional branch and the branch condition is not met This leads to a simple statement de ning this sequencing signal S1 0 if and only ifthe assembly language opcode 0x0F andbranch 0 where branch 1 if and only if the branch condition is met The sequencing signal S2 is used to control the entering ofthe defer code for those instructions that can use indirect addressing Recall that the assignment of opcodes to the assembly language instructions has been structured so that only instructions beginning with 01 1 can enter the defer phase Even these enter the defer phase only when 1R 1 Thus we have the following definition ofthis signal S2 1 if and only if IR31 0 IR30 1 1R2 1 and IR 1 In away this is exactly the definition of the sequencing control signal S2 as used in the hardwired control unit The only difference is that in this design the signal S2 must be used independently of the signal S1 so we must use the full definition The figure below illustrates the circuitry to generate the two sequencing signals S1 and S2 S1 1231 1230 1229 R28 1227 branch 52 13314330 IRZ9 IR26 branch Given these circuits we have the final form and labeling of the microiwords in the microi memory Note that there are no micrordata words only microinstructions Microiop B1 B2 B3 ALU M1 M2 S2 0 S21 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 8 bit 8 bit The form ofthe type 1 instruction is completely defined and can be given as follows Microiop B1 B2 B3 ALU M1 M2 D 0 D 1 0001 0x0 0x0 0x0 0x0 0x0 0x0 0x20 0x20 Butwhat exactly does this dispatch instruction do The question becomes one ofdefining the dispatch table which is used to determine the address of the microcode that is invoked explicitly by this dispatch We now address that issue The design of the B0275 uses a dispatch mechanism copied from that used by Andrew S Tanenbaum in his textbook Structured Computer Organization Fifth Edition published by PearsonPrentice7Hall in 2006 ISBN 0 7 13 7 148521 7 0 It is apparent that this dispatch mechanism is commonly used in many commercial implementations of microcode The solution is to use the opcode itself as the dispatch address As the B0275 uses a five bit opcode the sequencer unit for the microprogrammed control unit must expand it to an 87bit address by adding three high order 0 bits so that the dispatch address is 000 IR31727 As an example the binary opcode for LDR is 01100 its dispatch address is 0000 1100 or 0x0C The Boz75 uses five7bit opcodes with range 0x00 through 0x1F It then follows that addresses 0x00 through 0x1F in the micromemory must be reserved for dispatch addresses It is for this reason that the common fetch sequence begins at address 0x20 that is the next available address We now see that this structure works only because the address of the next microinstruction is explicitly encoded in the microinstruction This dispatch mechanism works very well on the 14 of 22 assembly language instructions that complete execution in one additional clock pulse As examples we examine the control signals for the first 8 opcodes 0x00 7 0x07 along with the common fetch microcode Address Micro Control Signals Next Address Opcode S2 0 S2 1 0x00 0 0 gt RUN 0x20 0x20 0x01 0 IR gt B1 extend tral B3 gt R 0x20 0x20 0x02 0 IR gt B1 R gt B2 and B3 gt R 0x20 0x20 0x03 0 IR gt B1 R gt B2 extend add B3 gtR 0x20 0x20 0x04 0 NOP 0x20 0x20 0x05 0 NOP 0x20 0x20 0x06 0 NOP 0x20 0x20 0x07 0 NOP 0x20 0x20 0x20 0 PC gt B1 tral B3 gt MAR READ 0x21 0x21 0x21 0 PC gt B1 1 gt B2 add B3 gt PC 0x22 0x22 0x22 0 MBR gt B2 tra2 B3 gt IR 0x23 0x23 0x23 1 Dispatch based on opcode 0x20 0x20 At this point our design continues to look sound Note that the unused opcodes those at microprogram addresses 0x04 through 0x07 simply do nothing and return to the common fetch sequence at address 0x20 This allows for future expansion of the instruction set The only problem left to be addressed is the proper handling of instructions that require more than one clock cycle following the common fetch in which to execute The first such instruction is the GET assembly language instruction The control signals for the GET assembly language instruction as implemented in the hardwired control unit are shown below Note that F T3 here does nothing as the instruction cannot be completed in Fetch and I decided not to make the F T3 signal generation tree more complex when I could force the execution into E T0 and E T2 GET Op Code 01000 Hexadecimal 0x08 F T0 PC gt Bl tral B3 gt MAR READ MAR PC F Tl PC gtBl l gtB2 add B3 gtPC PClt PC1 F T2 MBR gt B2 tra2 B3 gt IR IR MBR F T3 WAIT E T0 IR gt Bl tral B3 gt IOA Send out the IO address E Tl WAIT E T2 IOD gt B2 tra2 B3 gt R Get the results E T3 WAIT Noting that the WAIT microoperations in this sequence are used only because there is nothing that can be done during those clock pulses we can rewrite the sequence as follows GET Op Code 01000 Hexadecimal 0x08 T0 PC gt Bl tral B3 gt MAR READ MAR PC Tl PC gtBl l gtB2 add B3 gtPC PClt PC1 T2 MBR gt B2 tra2 B3 gt IR IR MBR T3 IR gt Bl tral B3 gt IOA Send out the IO address T4 IOD gt B2 tra2 B3 gt R Get the results This ts into the structure of the microcode fairly well except that it seems to call for two instruction to be placed at address 0x08 The solution to the problem is based on the fact that each microinstruction must encode the address of the next microinstruction Just select the next available word in micromemory and place the rest of the execution sequence there What we have is as follows Address Micro Control Signals Next Address Opcode S2 0 S2 1 0x08 0 IR gt Bl tral B3 gt IOA 0x24 0x24 0x20 0 PC gt Bl tral B3 gt MAR READ 0x21 0x21 0x21 0 PC gt B1 1 gt B2 add B3 gt PC 0x22 0x22 0x22 0 MBR gt B2 tra2 B3 gt IR 0x23 0x23 0x23 1 Dispatch based on opcode 0x20 0x20 0x24 0 IOD gt B2 tra2 B3 gt R 0x20 0x20 In software engineering such a structure is called spaghetti code and is highly discouraged The reason is simple one writes a few thousand lines in this style and nobody including the original author can follow the logic The microprogram however comprises a small number fewer than 33 independent threads of short less than 12 instructions For such a structure even spaghetti code can be tolerated Assignment of Numeric Codes to Control Signals We now start writing the microcode This step begins with the assignment of numeric values to the control signals that the control unit emits The next table shows the numeric codes that this author has elected to assign to the encoded control signals these being the controls for bus Bl bus B2 bus B3 and the ALU While the assignment may appear almost random it does have some logic The basic rule is that code 0 does nothing The bus codes have been adjusted to have the greatest commonality thus code 6 is the code for both MBR gt B2 and B3 gt MBR Code Bus 1 Bus 2 Bus 3 ALU 0 1 PC gt B1 1 gt B2 B3 gtPC tral 2 MAR gt B1 7 l gtB2 B3 gt MAR tra2 3 R gt Bl R gt B2 B3 gtR shift 4 IR gt B1 B3 gt IR not 5 SP gt B1 B3 gt SF add 6 MBR gt B2 B3 gt MBR sub 7 IOD gtB2 B3 gt 10D and 8 B3 gt 10A or 9 xor 10 Other assignments may be legitimately defended but this is the one we use Example Common Fetch Seguence We begin our discussion of microprogramming by listing the control signals for the rst three minor cycles in the Fetch major cycle and translating these to microcode We shall mention here and frequently that the major and minor cycles are present in the microcode only implicitly It is better to think that major cycles map into sections of microcode For this example we do the work explicitly Location 0x20 F T0 PC gt B1 B1 code is l tral ALU code is 1 B3 gt MAR B3 code is 2 READ M2Bit 3 1 so M2 8 Micro4p 0 B2 code and M1 code are both 0 Address MicroOp B1 B2 B3 ALU M1 M2 820 821 0x20 0 l 0 2 l 0 8 0x21 0x21 Location 0X21 F T1 PC gt B1 B1 code is 1 1 gt B2 B2 code is 1 add ALU code is 5 B3 gt PC B3 code is 1 Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0X21 0 1 1 1 5 0 0 0X22 0X22 Location 0X22 F T2 MBR gt B2 B2 code is 6 Hal ALU code is 2 B3 gt IR B3 code is 4 Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0X22 0 0 6 4 2 0 0 0X23 0X23 Location 0X23 Dispatch on the opicode in the machine language instruction For this we assume that the Micro4p is 1 and that none of the other elds are used Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0X23 1 0 0 0 0 0 0 0X20 0X20 Here is the microprogram for the common fetch sequence Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0X20 0 1 0 2 1 0 8 0X21 0X21 0X21 0 1 1 1 5 0 0 0X22 0X22 0X22 0 0 6 4 2 0 0 0X23 0X23 0X23 1 0 0 0 0 0 0 0X20 0X20 Here is the section of microprogram for the common fetch sequence written in the form that would be seen in a utility used for debugging the microcode Address Contents 0X20 0x010 2108 2121 0X21 0x011 1500 2222 0X22 0x006 4200 2323 0X23 0X100 0000 2020 We now have assembled all of the design tricks required to write microcode and have examined some microcode in detail It is time to nish the microprogramming The Execution of Op Codes 0x00 through 0x07 The rst four of these machine instructions 0x00 70x00 use immediate addressing and execute in a single cycle while the last four 0x04 70x07 are NOP s also executing in a single cycle The microcode for these goes in addresses 0x00 through 0x07 ofthe microimemory The next step for each of these is Fetch for the next instruction so the next address for all of them is 0x20 HLT Address 0x00 LDI Address 0x01 ANDI Address 0x02 ADDI Address 0x03 We are now in a position to specify the rst eight microiwords ddress 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 Op Code 00000 MicroOp 0 Op Code 00001 MicroOp 0 Op Code 00010 MicroOp 0 Op Code 00011 MicroOp 0 B1 0 B1 4 B1 4 B1 1 0 gt RUN B2 B3 ALU M1 M2 S2 0 0 0 0 0 1 0x20 IR gt B1 extend tral B3 gt R B2 B3 ALU M1 M2 S2 0 0 3 1 0 2 0x20 IR gt B1 R gt B2 and B3 gt R B2 B3 ALU M1 M2 S2 0 3 3 7 0 0 0x20 IR gt B1 R gt B2 extend add B3 gt R B2 B3 ALU M1 M2 S2 0 3 3 5 0 2 0x20 B2 B3 ALU M1 M2 S2 0 0 0 0 0 1 0x20 0 3 1 0 2 0x20 3 3 7 0 0 0x20 3 3 5 0 2 0x20 0 0 0 0 0 0x20 0 0 0 0 0 0x20 0 0 0 0 0 0x20 0 0 0 0 0 0x20 Based on the tables above we state the contents of the rst eight microiwords MicroOp B 1 0 0 0 4 0 4 0 1 0 0 0 0 0 0 0 0 Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 Contents 0x 000 0001 2020 0x 040 3102 2020 0x 043 3700 2020 0x 013 3502 2020 0x 000 0000 2020 0x 000 0000 2020 0x 000 0000 2020 0x 000 0000 2020 S2 1 0x20 S2 1 0x20 S2 1 0x20 S2 1 0x20 S21 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 For the moment let s skip the next eight opcodes and nish the simpler cases LLS Op Code 10000 R gt B2 shift LR 1 A 0 C 0 B3 gt R Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0X10 0 0 3 3 3 8 0 0X20 0X20 LCS Op Code 10001 R gt B2 shift LR 1 A 0 C 1 B3 gt R Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0X11 0 0 3 3 3 9 0 0X20 0X20 RLS Op Code 10010 R gt B2 shift LR 0 A 0 C 0 B3 gt R Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0X12 0 0 3 3 3 0 0 0X20 0X20 RAS Op Code 10011 R gt B2 shift LR 0 A 1C 0 B3 gt R Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0X13 0 0 3 3 3 4 0 0X20 0X20 NOT Op Code 10100 R gt B2 not B3 gt R Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0X14 0 0 3 3 4 0 0 0X20 0X20 ADD Op Code 10101 R gt Bl R gt B2 add B3 gt R Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0X15 0 3 3 3 5 0 0 0X20 0X20 SUB Op Code 10110 R gt Bl R gt B2 sub B3 gt R Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0X16 0 3 3 3 6 0 0 0X20 0X20 AND Op Code 10111 R gt Bl R gt B2 and B3 gt R Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0X17 0 3 3 3 7 0 0 0X20 0X20 OR Op Code 11000 R gt Bl R gt B2 01 B3 gt R Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0X18 0 3 3 3 8 0 0 0X20 0X20 XOR Op Code 11001 R gt Bl R gt B2 xor B3 gt R Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0X19 0 3 3 3 9 0 0 0X20 0X20 We have now completed the microprogramming for all but eight of the instructions The table on the next page shows what we have generated up to this point ddress 0X00 0X01 0X02 0X03 0X04 0X05 0X06 0X07 0X08 0X09 OXOA OXOB OXOC OXOD OXOE OXOF 0X10 0X11 0X12 0X13 0X14 0X15 0X16 0X17 0X18 0X19 OXIA OXIB 0X1C OXID 0X1E 0X1F 0X20 0X21 0X22 0X23 h4icrop 0 0000000 b OOOOOOOOOOOOOOOOOOO E OOOOt IAAO OOt It IOOOOOOUJUJUJUJUJOOOOO DJ N OOOOUJUJOO OCNt OOOOOOOUJUJUJUJUJUJUJUJUJUJ UIJ U OOOOUJLAUJO Obt NOOOOOOUJUJUJUJUJUJUJUJUJUJ 3 c OOOOUI t IO ONUIt OOOOOOWOOQONUIAUJLALAUJ OOOOOOOOK OOOOOOOOOOOOOOOOAOWOO N OOOONONt Iz OOOOOOOOOOOOOOOOOOOOO 820 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X21 0X22 0X23 0X20 8211 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X20 0X21 0X22 0X23 0X20 Note that instructions OXIA through 0X1F are not yet implemented so they show as NOP s We now move to those instructions that require Defer and Execute for completion Due to the ordering of the opwodes we rst investigate those instructions that cannot enter Defer GET Op Code 01000 F T3 E T0 E T1 E T2 E T3 Hexadecimal 0x08 WAIT IR gt B1 tra1 B3 gt IOA Send out the IO address WAIT IOD gt B2 tra2 B3 gt R Get the results WAIT As noted above we can ignore any WAIT signal that is not required by considerations of memory timing The rst of two microoperations is associated with the dispatch address for the GET instruction and the second one at the rst available micromemory word IR gt B1 tral B3 gt IOA Address 0X08 IOD gt B2 tra2 B3 gt R Address 0X24 PUT Op Code 01001 F T3 E T0 E T1 E T2 E T3 MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0 4 0 8 1 0 0 0X24 0X24 MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0 0 7 7 2 0 0 0X20 0X20 Hexadecimal 0x09 WAIT R gt B2 tra2 B3 gt IOD Get the data ready WAIT IR gt B1 tra1 B3 gt IOA Sending out the address WAIT causes the output of data R gt B2 tra2 B3 gt IOD Address 0X09 IR gt B1 tral B3 gt IOA Address 0X25 RET Op Code 01010 F T3 E T0 E T1 E T2 E T3 MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0 0 3 7 2 0 0 0X25 0X25 MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0 4 0 8 1 0 0 0X20 0X20 Hexadecimal 0x0A WAIT SP gt B1 71 B2 add B3 gt SP SP gt B1 tra1 B3 gt MAR READ WAIT MBR gt B2 tra2 B3 gt PC Decrement the SP Get the return address Put return address into PC Here we have three noniwaiting instructions plus a WAIT that is necessary for the memory access As a result we must allocate four microimemory words to the execution SP gtB171 gtB2 add B3 gtSP Address MicroOp B1 B2 B3 ALU M1 M2 S20 S21 OXOA 0 5 2 5 5 0 0 0X26 0X26 SP gt B1 tral B3 gt MAR READ Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0X26 0 5 0 2 1 0 8 0X27 0X27 WAIT Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0X27 0 0 0 0 0 0 0 0X28 0X28 MBR gt B2 traZ B3 gt PC Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0X28 0 0 6 1 2 0 0 0X20 0X20 RTI Op Code 01011 Hexadecimal 0x0B Not yet implemented This is encoded as another NOP until time to develop the details of interrupt handling The link Address MicroOp B1 B2 B3 ALU M1 M2 B 0 B 1 OXOB 0 0 0 0 0 0 0 0X20 0X20 We now turn to the four instructions that use both Defer and Execute One might be tempted to write a common Defer subroutine to be called by each of the Execute sections While this would reduce duplication of microicode we opt for infline coding In each of the following four instructions the step corresponding to F T3 issues control signals These will be issued by the link microioperation We must also introduce a new micromp to account for conditionally entering or not entering the Defer section The next four assembly language instructions LDR STR J SR and BR are the only that possibly use indirect addressing As discussed in our presentation of the sequencing control signals for the microprogram the defer phase will be entered if and only if 82 l The template for the DEFER state is shown below It has one essential WAIT state X READ X l WAIT X 2 MBR gt B2 traZ B3 gt MAR X 3 Code for E T0 Due to this structure the address for 2 0 will be 3 more than that for 2 l LDR Op Code 01100 Hexadecimal 0x0C F T3 IR gt Bl R gt B2 add B3 gt MAR Do the indexing D TO READ Address is already in the MAR D Tl WAIT Cannot access the MBRjust now D T2 MBR gt B2 traZ B3 gt MAR MAR MBR D T3 WAIT E TO READ Again address is already in the MAR E Tl WAIT E T2 MBR gt B2 traZ B3 gt R E T3 WAIT IR gt Bl R gt B2 add B3 gt MAR Address MicroOp B1 B2 B3 ALU M1 M2 82 0 2 l OXOC 0 4 3 2 5 0 0 0X2C 0X29 READ Address MicroOp B1 B2 B3 ALU M1 M2 SZ 0 2 1 0X29 0 0 0 0 0 0 8 0X2A 0X2A WAIT Address MicroOp B1 B2 B3 ALU M1 M2 SZ 0 2 l 0X2A 0 0 0 0 0 0 0 0X2B 0X2B MBR gt B2 traZ B3 gt MAR Address MicroOp B1 B2 B3 ALU M1 M2 SZ 0 2 l 0X2B 0 0 6 2 2 0 0 0X2C 0X2C READ Address MicroOp B1 B2 B3 ALU M1 M2 SZ 0 2 l 0X2C 0 0 0 0 0 0 8 0X2D 0X2D WAIT Address MicroOp B1 B2 B3 ALU M1 M2 SZ 0 2 l 0X2D 0 0 0 0 0 0 0 0X2E 0X2E MBR gt B2 traZ B3 gt MAR Address MicroOp B1 B2 B3 ALU M1 M2 82 0 2 l 0X2E 0 0 6 2 2 0 0 0X20 0X20 STR Op Code 01101 Hexadecimal 0x0D F T3 IR gt B1 R gt B2 add B3 gt MAR Do the indexing D TO READ Address is already in the MAR D T1 WAIT Cannot access the MBRjust now D T2 MBR gt B2 tra2 B3 gt MAR MAR MBR D T3 WAIT E T0 WAIT E T1 R gt B1 tral B3 gt MBR WRITE E T2 WAIT E T3 WAIT IR gt B1 R gt B2 add B3 gt MAR Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0x0D 0 4 3 2 5 0 0 0x32 0x2F READ Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0x2F 0 0 0 0 0 0 8 0x30 0x30 WAIT Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0x30 0 0 0 0 0 0 0 0x31 0x31 MBR gt B2 tra2 B3 gt MAR Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0x31 0 0 6 2 2 0 0 0x32 0x32 R gt B1 tral B3 gt MBR WRITE Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0x32 0 3 0 6 1 0 4 0x33 0x33 WAIT Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0x33 0 0 0 0 0 0 0 0x20 0x20 Note here that we must have a WAIT state following the last WRITE of the execute phase This allows the memory to complete the instruction before the next instruction is fetched J SR Op Code 01110 Hexadecimal 0x0E F T3 IR gt B1 R gt B2 add B3 gt MAR Do the indexing D TO READ Address is already in the MAR D T1 WAIT Cannot access the MBRjust now D T2 MBR gt B2 tra2 B3 gt MAR MAR MBR D T3 WAIT E T0 PC gt B1 tral B3 gt MBR Put return address in MBR E T1 MAR gt B1 tral B3 gt PC Set up for jump to target E T2 SP gt B1 tral B3 gt MAR WRITE Put return address on stack E T3 SP gt B1 1 gt B2 add B3 gt SP Bump SP IR gt B1 R gt B2 add B3 gt MAR Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 OXOE 0 4 3 2 5 0 0 0X37 0X34 READ Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0X34 0 0 0 0 0 0 8 0X35 0X35 WAIT Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0X35 0 0 0 0 0 0 0 0X36 0X36 MBR gt B2 traZ B3 gt MAR Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0X36 0 0 6 2 2 0 0 0X37 0X37 PC gt B1 tral B3 gt MBR Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0X37 0 1 0 6 1 0 0 0X38 0X38 MAR gt B1 tral B3 gt PC Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0X38 0 2 0 1 1 0 0 0X39 0X39 SP gt B1 tral B3 gt MAR WRITE Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0X39 0 5 0 2 1 0 0 0X3A 0X3A SP gt B11 gt B2 add B3 gt SP Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0X3A 0 5 1 5 5 0 0 0X20 0X20 BR Op Code 01111 Hexadecimal 0x0F F T3 IR gt B1 R gt B2 add B3 gt MAR Do the indexing D TO READ Address is already in the MAR D T1 WAIT Cannot access the MBRjust now D T2 MBR gt B2 tra2 B3 gt MAR MAR MBR D T3 WAIT E T0 WAIT E T1 WAIT E T2 WAIT E T3 MAR gt B1 tral B3 gt PC Remember that the microcode at address 0X23 will not dispatch to address OXOF if the branch condition is not true This avoids wasted time and incorrect execution IR gt B1 R gt B2 add B3 gt MAR Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 OXOF 0 4 3 2 5 0 0 0X3E 0X3B READ Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0X3B 0 0 0 0 0 0 8 0X3C 0X3C WAIT Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0X3C 0 0 0 0 0 0 0 0X3D 0X3D MBR gt B2 traZ B3 gt MAR Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0X3D 0 0 6 2 2 0 0 0X3E 0X3E MAR gt B1 tral B3 gt PC Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0X3E 0 2 0 1 1 0 0 0X20 0X20 This completes the derivation of the microprogram for the B0275 Here now is the complete microprogram of the B0275 shown in two pages of tables Address MicroOp B1 B2 B3 ALU M1 M2 S2 0 S2 1 0X00 0 0 0 0 0 0 1 0X20 0X20 0X01 0 4 0 3 1 0 2 0X20 0X20 0X02 0 4 3 3 7 0 0 0X20 0X20 0X03 0 1 3 3 5 0 2 0X20 0X20 0X04 0 0 0 0 0 0 0 0X20 0X20 0X05 0 0 0 0 0 0 0 0X20 0X20 0X06 0 0 0 0 0 0 0 0X20 0X20 0X07 0 0 0 0 0 0 0 0X20 0X20 0X08 0 4 0 8 1 0 0 0X24 0X24 0X09 0 0 3 7 2 0 0 0X25 0X25 OXOA 0 5 2 5 5 0 0 0X26 0X26 OXOB 0 0 0 0 0 0 0 0X20 0X20 OXOC 0 4 3 2 5 0 0 0X2C 0X29 OXOD 0 4 3 2 5 0 0 0X32 0X2F OXOE 0 4 3 2 5 0 0 0X37 0X34 OXOF 0 4 3 2 5 0 0 0X3E 0X3B 0X 10 0 0 3 3 3 8 0 0X20 0X20 0X1 1 0 0 3 3 3 9 0 0X20 0X20 0X 12 0 0 3 3 3 0 0 0X20 0X20 0X 13 0 0 3 3 3 4 0 0X20 0X20 0X 14 0 0 3 3 4 0 0 0X20 0X20 0X15 0 3 3 3 5 0 0 0X20 0X20 0X 16 0 3 3 3 6 0 0 0X20 0X20 0X 17 0 3 3 3 7 0 0 0X20 0X20 0X18 0 3 3 3 8 0 0 0X20 0X20 0X 19 0 3 3 3 9 0 0 0X20 0X20 0X 1 A 0 0 0 0 0 0 0 0X20 0X20 0X 1B 0 0 0 0 0 0 0 0X20 0X20 0X 1C 0 0 0 0 0 0 0 0X20 0X20 0X 1 D 0 0 0 0 0 0 0 0X20 0X20 0X IE 0 0 0 0 0 0 0 0X20 0X20 0X 1F 0 0 0 0 0 0 0 0X20 0X20 0X20 0 1 0 2 1 0 8 0X21 0X21 0X21 0 1 1 1 5 0 0 0X22 0X22 0X22 0 0 6 4 2 0 0 0X23 0X23 0X23 1 0 0 0 0 0 0 0X00 0X00 ddress 0X24 0X25 0X26 0X27 0X28 0X29 0X2A 0X2B 0X2C 0X2D 0X2E 0X2F 0X30 0X31 0X32 0X33 0X34 0X35 0X36 0X37 0X38 0X39 0X3A 0X3B 0X3C 0X31 0X3E h4icrop 0 OOOOOOOOOOOOOOOOOOOOOOOOOO E NOOOUIUINt IOOOOUJOOOOOOOOOOOUIAO DJ N OONOOt OOOONOOOOONOOONOOONOOONOOOQ UIJ U t nNCOUINt IONNOOOONNOONOONOOt ONOON AllJ D INCOUIl D Il NOOOl NOONOONOONOl D IN OOOOOOOOOOOOOOOOOOOOOOOOOOOK Z N OOOOOOOOOOOOOOAOOOOOOOOOOOOOOOOOO 820 0X20 0X20 0X27 0X28 0X20 0X2A 0X2B 0X2C 0X2D 0X2E 0X20 0X30 0X31 0X32 0X33 0X20 0X35 0X36 0X37 0X38 0X39 0X3A 0X20 0X3C 0X3D 0X3E 0X20 8211 0X20 0X20 0X27 0X28 0X20 0X2A 0X2B 0X2C 0X2D 0X2E 0X20 0X30 0X31 0X32 0X33 0X20 0X35 0X36 0X37 0X38 0X39 0X3A 0X20 0X3C 0X3D 0X3E 0X20 The last address is 0X3E 62 in decimal The microprogram has used 63 of the available 256 addresses it is an 87bit address for a 25 usage With 63 addresses used we could have opted for a 67bit address We chose an 87bit address for the sake of simplicity The reader will note that this leaves plenty of unused microprogram space for possible implementation of any new instructions The Seguencer for the Microprogrammed Control Unit We now discuss the microwontrol unit which is responsible for sequencing the control unit itself which is microprogrammed Recall that there are no microdata in the microprogram but only microinstructions Based on this observation the only function of the micrwcontrol unit is the selection of the next address to place into the micrwmemory address register MMAR There are four sources for this address 1 the assembly language opcode 2 the 52 0 field of the microinstruction 3 the 52 1 field of the microinstruction and 4 a constant register 0x20 which is used only when the computer is started Here is the circuit for the microwontrol unit omitting only the constant register Micro Memory Chapter 3 Additional Pages Truth Tables and Associated Tables with Don t Care Conditions At this point we mention a convention normally used for writing large truth tables and associated tables in which there is signi cant structure This is called the don t care condition denoted by a d in the table When that notation appears it indicates that the value of the Boolean variable for that slot can be either 0 or 1 but give the same effect Let s look at two tables each of which to be seen and discussed later in this textbook We begin with a table that is used to describe control of memory it has descriptive text RW 0 not The two control variables are Select and R W But note that when Select 0 the action of the memory is totally independent of the value of R W For this reason we may write RW not Similarly consider the truth table for a twoitoifour decoder with Enable The complete version is shown rst it has eight rows and describes four outputsY0 Y1 Y2 and Y3 The more common description uses the don t care notation 1 This latter to not considering the d as an algebraic value What the first row says is that if Enable 0 then I don t care what X1 and X0 are even if they have different values all outputs are 0 The next section will discuss conversion of a truth table into a Boolean expression The safest way to do this is to convert a table with don t cares back to the full representation Page 6A Chapter 3 Addstaonai Pages Here is the AND gate as rrnpiernented from two NAND gates X Y Figure Twn NAND Gates tn Make an AND Gate XoY 1n orderto rrnpiernent an OR gate we rnust make use ofDeMorgan39s law As stated above DeMorgan39s law is usuany given as XY i Y We use straightforward algebraic vs a rnanrpuiataon to an ta vanant staternent of DeMorgan39s 1aw Using this strange equality a direct result of DeMorgan39s law we have the OR erreuit X Y Figure Three NAN39D Gates Used tn Make an OR Gate Circuits and Truth Tables We now address an obvious problem ihowto relate eireuits to Boolean expressions The best way to do tins is to work some examples Here is the rst one Questinn Follows Page 19 Replaces pages 207 28 chapter 3 Additional pages The rnethod to get the answer is to label each gate and deterrnine the output ofeaeh The on l u u ullu r o ugm 5 1 XY 5 F 12 Veal Z 3 g 4 XY Z The outputs ofeach gate are as follows The output of gate 1 is x v z and The output of gate 5 is x v 9 xi v e 2 We now produce the truth table for the function Lets give a sirnpler representation Follows Page 19 Replaces pages 20 a 28 Chapter3 AddmonalPages We now produce both the SOP and POS representattohs ofthts funottoh For the SOP we look at the four 1 ofthe funottoh forthe POS we 00k at the four zero FX Y ZX IY ZY X IY OZ JrXIY lZY XIYIZ O O O O O 1 O 1 1 FXYZXY zxY z x Yz x Y Z 010 O 1 1 1 110 To slmp 1fy m SOP we wnte the ruhouoh h a shgatly more Complex Xt form 392 XIYWZ X39Y39Z Y 39Z XYZ X Y YWZ X39Y39Z To slmp lfy m POS we agam wnte the fuhottoh m a shgatly bizarre form Y ZXY z X Y nX Y ZIXY OY X YZ Y 2 mnum u H mm M FYZ2lto147 th Y Z Ha 3 5 6 Question F2A B C Kolac A C ABE ABC 52ABcABcABEA cKBc The answerhere IS Justw draw the clrcults The general rule 15 stmple SOP he OR gate conneotmg the output ofanumberofAND g POS he AND gate oohneotmg the output ofanumberofOR gates 11ows Page 19 Replaces pages 20 728 Chapter 3 Addltlonal Page Here lsthe clrcult for F2A B c It can be simplified F2ABc Kolac A c ABE ABC Here IS the clrcult for G2A B c It can be simplified 52A B c ABcABEA cKBc The NoannVerLing Buffer enow funcuons w r O m a pa ll ll Logloallyuoulllu u m mcally A loglcl voltage m the range 2 0 7 5 0 volts wlll be output asS 0 volts A loglc 0 voltage m the range 0 0 7 0 8 volts wlll be output as 0 0 volts consldereda u uu uuputl v u v M l l dlum al Integrated cueults ln a future chapter Follows Page 19 ReplacespagesZOrl Z chapter3 Addrtronal Page More Unusual Circuits Up to thrs pornt Wehave been rnostly consldenng loglc gates In therr abrlrty to lmpl the functlons ofBoolean algebra We now tum our attentron to a few crrcurts that depend as uent unp We begrnwrth a fundarnental property ofall electronrc gates called gale delayquot Thls ops property Wlll becorne slgnlflcant when we consrder lpr We begrnwrth consrderatron ofa slmpleNOT gate wrth Y E as shown below X Y ll r n NOT ectronrc crrcurts wehaye another lssue Thls lssue called gate delayquot rellects the fact 6 out uL always lags the rnput by an rnteryal oftlmethat ls the gate delay For standard TTL crrcurts such astheMLSOA that rrnplernents the NOT functlon the gate delay ls about ten u t utput ttalt In the next gure we postulate a NOT gate wrth a gate delay of lonanoseconds wrth an rt tr OW quotd r r r r r r H l and also an rnteryal oflOnanoseconds durrngwhrchxo and E 0 Thls ls nota fault ofthe crrcurt rt ls Just a WellAmdersLood physlcal realrty p putal an The source of r r r r u butthatthenurnbers tend to be about lo onanoseconds ln ur dlscusslons that follow we shall make the assurnptron that all loglc gates dlsplay the sarne delay lee Whlch we shall call a H gate delay Whlle we should understand thatthrs trrne yalue ls about lo nanoseconds we shall not rely on rts preclse yalue Follows Page 19 ReplacespagesZOrZEZ Chapter 3 Addluonal Pages There are a number of des1gns that call for 1ntroduc1ng a xed delay In slgaal propagatlon so that the slgaal TL L Man n L Luu butjust note them The most stra1ghtforward delay clrcult 1s based on the Boolean 1dent1ty i X Th1s slmple Boolean 1dent1ty leads to the delay ctrcult X4gtoY gt0 Z The delay 1s shown In thet1m1ngd1agrambelow1n whlch Z lags X by 20 nanoseconds Z F43 Y XLIM The rule for apphcatlon of gate delays 1s stated slmply below The output of a gate is stable one gate delay after all of its inputs are stable t t m e pr t t t We no t t t t 1s less and 1tusually serves a dlfferentpurpose 1n the deslga It should be clear that the output ofa gate changes one gate delay after any of 1ts 1nputs change To elaborate on th1s statement let us conslder an excluswe or XORch1p The truth mble for an XOR gate 1s shown In the follow1ng mble We now lUl dn eneunundet 1n1t1ally bothX O and Y O FlrstX changes to l and sometlme later so does Y Here 1s the clrcult by Y Follows Page 19 Replaces pages 207 28 chapter3 Addrtronalpages Here ls the trmrng dragram z Y delay a er rnput Y changes Thls unusual dlagrxds shown only to make the pomt that the an than lnlput all n o a t mp one u Boolean rdentrty Speclflcally we kno that for all Boolean yanables x X39X 0 rdentrcally 0 Such a consrderatron does not account for gate delays X Z Y Suppose that mput x goes hrgn and stays hrgn for some trme posslbly a number of gate delays The outputz ls based on the fact thatthe output Y lags xby one gate delay z Y t t t t l nan nu tla at d la At T lo the value ofX changes Nelther Y nor z changes ALT 20 theyalues of each on andz change Theyalue on re ects theyalue ofX atT lo so Y becomes 0 The value on re ects theyalue ofboth x and Y atT lo T lo wehadbothxl and Y 1 sozbecomes l atTzo ALT 3o theyalue on changes agaln to re ect theyalues ofX and Y atT 20 omes o What we have m the above crrcurt ls a deslgn to produce a Very short pulse of me duratron edgetnggered lpr ops m a future chapter Follows Page 19 Replaces pages 20 728 Chapter 3 Addlbonal Pages T State Buffers We have now seen all of the logle gates to be usedln thls course There ls one more gate L slate buffer lnpul eulpul lnpnl eulpul Enable Enable Enabled ngh Enabled Law The dlfference between these two elteults relates to how the elteults are enabled Note that the enabledrlow mestate buffer shows the standard use of the NOT dot on lnpnt The followlng gure shows two ways o EnabledeLow Tn estate buffer one uslng an Enabledengh anStat wlth aNCT gate on the Enable llne The slgnlfleanee ofthe oyetbat on the Enable lnpnt ls that the gate ls aetlye when the eonbol ls logle 0 X Output X Output Enable Enable Figure Twn Views at an Enableeruw TrirStzte Buffer flmplementmg an A to the standard 1 4 lt Agate 1 l b b state A F A F A lgt F C 0 e C c 1 Figure Circuits Equivalent In an Enabled Trirstzte and 3 Disabled Trirstzte V l output h ealled a hlghez statequot by englneets who use the symbol Z for lmpedanee when lt ls not enabled g for all practlcal pnlposedlt does not assert anythlng on lts output Follows Page 19 Replaces pages 207 28 Chapter 3 Additional Pages The Third State The de nition of this third state in a triistate buffer is both obvious and subtle Compare the two circuits in the gure below One is a bulTer the other is a triistate buffer AgtF Ang For the circuit on the left either F 0 0 volts or F l 5 volts There is no other option For the circuit on the right when C 1 then F A and takes a value of either 0 volts or 5 volts depending on the value of the input When C 0 F is simply not de ned One of the better ways to understand the tristate bulTer is to consider the following circuit with two Boolean inputs A and B one output F and an enable signal C A F C0 A F C C1 B F B Note that the two triistate buffers are enabled differently so that the top buffer is enabled if and only if the bottom buffer is not enabled and vice versa The design insures that at no time are both of the triistate buffers enabled so that there is no con ict of voltages C 0 Only the top buffer is enabled F A C 1 Only the bottom buffer is enabled F B The reader will note that the above circuit is logically equivalent to the one that follows A F C B Given only this simple example one might reasonably question the utility of triistate buffers It appears that they offer a novel and complex solution to a simple problem The real use of these buffers lies in placing additional devices on a common bus a situation in which the use of larger OR gates might prove dif cult Before addressing the standard uses of the triistate buffer we must review some of the basics of direct current electricity voltage current and resistance Follows Page 19 Replaces pages 20 7 28 Chapter 3 Adduonal Pages Review 113sz Electrnnics A tradmonal presentauon of tlus rnatenal rnrght have begun with a review ofthe basil unul this polntrn the eourse at which urne rtrs needed asie Circuit We begin our dseussron wth a simple example the Brits eall it This has three basic eornponen erreurt ashlight or electnc torehquot as ts r t e a abattery a svvrteh and al gh bulb For on and off U A I l Lightis or Lightis On In the both figures we see alight bulb eonneetedto abattery vratvvo Wires and a svvrteh The gure above uses afew ofthe following basic erreurt elernents L 4 single Cell Battery Light Switch switch Grnund Open Clnsed The rst Ml u h b A and ealls a battery these eorne in various sizes including AA AAA c andD Eae of these eells is rated at l 5 volts due to a eornrnont hnlcal basis for Lhelrmanufacture suretly speaking abattery is a eolleetron of eells so that atypreal ashlight eontains one or battery being built from a nurnber of leadracld eells vvhreh allows one to pass only when open Follows Page 19 Replaces pages 207 28 Chapter 3 Adduonal Pages The Idea nl39 Grn Consider the above erreuit whlch suggests atworwlre design one Wire from the battery to e rnetalhe ease that also eonduets eleetnerty Metal Case at t the Flashligh Physical Cunneetinn Equivalent Circuit Consider the erreurt at left whlch shows the physlcal eonneetron postulated When the swrteh ls open o eunent ows w en the swrt h ls elosed eunent ows from the battery through the synteh andlrght bulb to the rnetallre ease ofthe ashlight whlch seryes as a m r l rnueh rnore ofrt andrt will eornplete the erreurt Wth no problern H vw L that the elern one ean conslder all ground elernents to be eonneeted by awrre thus eornpleung the ra o e an l body of the ear ltself as the ground Although iron and steel are not eneellent eonduetors ofelectxlclty the sheer size ofthe ear body allows for the eleetnerty to ow easlly L 0 To eonelude the erreurt at lelt will be ourrepresentauon ofa ashlight The battery provides the eleetnerty whlch ows thr the synteh when the synteh ls elosed nally to the ground through whl eh it returns to the attery s a eonyentron all swrtehes in dlagrams wlll be shown in the open posruon unless there ls agoodreason not to open but whlch rnrghtbe closedln orderto allow the ow ofelectnclty The eonyentron of drawlng a synteh in the open position ls due to the fact that it ls easier to spot in a dlagram Follows Page 19 Replaces pages 207 28 chapter3 AdditionalPages Vollagg Current and Resistance Itts now ttrnetobecorne a bttrnoreprectse tn our dtscusston ofelectrtctty We need to er lr u t t t t t t1 wean t t t t t t t and atcllul tll atel ll ill latltll fl l ateltll l atel are o en called currents blocks of atorns While electrons are not the only basic particles that have charge and are all rnore interesled in the ow ofposltlvely charged ions r n m ttral Within an d th mom neutron has no charge In normal life we do not see the interior ofawms so our experience l ll Hwt t Ht orl a ar ult L few electrons becoming aposttwe ion For the purposes ofthls course we watch only the electrons and ignore the ion An electric charge usually denoted by the symbol Q IS usually associated with a large them all ul a l l l l l l t t tguum posttwe Laminal to the negatwe Laminal Absent any pumping the electrons in the t t t t W pl llt that battery lt Hbulb part ofa larger complete circuit a Inside the battery the electrons are pumped irom the positive region to the negative region In the circuit outside the battery the electrons ow irom negative to positive Follows Page 19 Rep aces pages 20 728 Chapter3 Addrtronal Pages types ofmaterlals Conducwr A conductor ls a substance such as copper or srlver through whlch electrons can ow falrly easlly Insulator An msulator ls a substance such as glass orvvood that offers srgnr cantresrstancetothetlovvotelectrons lnman ofour clrcult dlagrams we assume that lnsulators do not transmlt electnclty at all althougT they all do vuth some resrstance The voltage ls amount ofpressure In the voltage pump lt ls qurte slmllar to water pressure In that t ls the pressure on the electrons that r a ovethr a nduc cusesthemtom ougn co tor Consroleragarnour ashllght example The battery prov rules a pressure on the electrons to ethernto ow oughthecrrcur enthesvutchrsopen l ls closed the electrons move In res onse tothrs pressure voltage and ow througa the llghtbulb The llghtbulb offers a speclflc reslsLance tothese electrons rt heats up and glows approachng 0 Tn rte t tor reslstor Tn a h ht bulb l l r t t r r r r Current does not ow Summary mun lat Wenow Charge Thls refers to an unbalanced collectlon of electrons The term used for denotrng charge ls Q The unrt of charge ls a coulomb Current Thls refers totherate at whlch a charge ows througa a conductor Voltage Thls refers to a force on the electrons that causes them to move Thls force can be due to a number of causes 7 electrochemrcal reactrons ln battenes and Changlng magnetrc elds In generators The term used for olenotrng voltage lsV orE forElectmmotiVe Force The unrt ofculrent ls a volt Resistance Thls ls ameasure ofthe degreeto whlch a substance opposes the ow of electrons Thetenn forreslstance ls R Theunrt ofreslsLance ls an ohm Follows Page 19 Replacespageszoezg Chapter 3 Adduohal Pages m aw he aw One way of statmg Ohm39 l w named for Georg Slmon Ohm a German teaeher who dlscoveredthe law m 1827 ls yerbally as follows ws thr ugh a rreurt elemehtrs dlrecdy propomonal to the The eurrehtthat o e eurt element and myersely proporuohal to the resrstahee t o yoltage aeross the Elr of that erreurt el emer Tun few 4 912mm he ehemrstry ofthe battery ls pushmg eleetrohs away from the posrtwe termmal denoted as quot Tm many through Lhaubittery towards the hegatrye termmal electrnns denoted as e Thls eauses ayoltage aeross the ohlyresrsuye elemeht through rt 1h algebra terms Ohm39s lawls easlly stated E IR where ls th eross th re w E g E 2 lb has areslstanee of 240 ohms an dhas ayoltage of120 yolts aeross or 120 1240 to getI 0 5 amperes Suppose that the lrght bu rt Then we say E R energy The power due to aresrstmg erreurt elemeht eah easlly be ealeulated The powerlaw ls states as P EI where P ls the power emrtted by the erreurt elemeht measuredm watts E ls the voltage aeross the erreurt element and 1 ls the eurreht through the erreurt elemeht eurreht of 0 5 amperes and apower ofU 5 120 60 watt There are ahumber ofvarlants ofthe power law based on subsutuuohs from Ohm39s law P 1212 we note that ayoltage of120 yolts aeross aresrstahee of 60 ohms In our above example would produee apower of e 1202 240 e 240 7 60 watts as expeeted Here are the three yarrahts eommohly Sean P El P E Eollows Page 19 Replaces pages 207 28 chapter 3 Addltlonal Pages Resislnrs in Series There are vay many erestlng cornblnatlons ofreslsLors found G n clr ul re we focus on on y one 7 lswrsl n R at 15 one reslstor placed a er ano In th we lnLroduce e symbol for a Conslder the clrcult at rlght Wth two reslstors havlng R2 R2respec1lvely One othe baslc laws of electromcs states that the reslsLance othe two In sales ls slmply the sum thus R Rl R2 LetEbethevoltage p and the current through the clrcult elements 15 glven by Ohm s law as I E R R2 Note that we rnustbe the same LetEl be the voltage drop across Kr and E2 be that across R2 Then E IR RlERl 2 and E2 IR2 RZIE R 2 It should come as no surpnse thatE E2 RE R R2 R2E R R2 Rl R2gtE Kl R2 15 If as ls commonly done we asslgn the gound state as havlng zero voltage then the voltages at the two polnts ln the clrcult above are slrnple R R 1 Atpolnt l the voltage ls E the full voltage othebaLLay 2 ALpolnLZLhevolLagelsE2 R2 RzlER1R2 ll to l t p lat cases 0 0 R RI R2 0 R2 1000RI y The voltage atpolnt 2 rs then E2 oE Rl 0 0 As polnt 2 rs dlrecLly connected to gound we would expect lt to be at zero voltage Suppose that R2 ls rnuch blgger than Rl Let R R and R loooR We calculate th voltage atpolnt 2 as E2 RZIE R R21000IRIER1000R1000H1001or rr Follows Page 19 Replaces pages 20 e 28 chapter 3 Additional Pages Putting aResislor and Switch in Series second resistor R2 is replaced by a switch that can be either open or closeol G G RI RI RI f R 0 L112 gt 100041I The Circuit Switch Closed Switch Open r 39 39 39 39 39 In both cases the voltage at point 1 is the full voltage ofthe battery 39 39 39 39 39 39 henceR 0 Aswe noted above this causes the voltage at point 2 to be equal to zero a For our u at least 1000 battery voltage nllmn e Here is a Version ofthe circuit as we shall use it later Rt Before we present our circuit we introduce a notation useoli awing two wires that appear to cross Lfa big dot is used at the crossing the two wires are connecteol Lfthere is a gap as in the right gure then the wires do not connect then the In this circuit another 39 39 ii an ion 39 r 39 39 39 H19 mnni39m itn e Follows Page 19 Replaces pages 20 728


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All subscriptions to StudySoup are paid in full at the time of subscribing. To change your credit card information or to cancel your subscription, go to "Edit Settings". All credit card information will be available there. If you should decide to cancel your subscription, it will continue to be valid until the next payment period, as all payments for the current period were made in advance. For special circumstances, please email


StudySoup has more than 1 million course-specific study resources to help students study smarter. If you’re having trouble finding what you’re looking for, our customer support team can help you find what you need! Feel free to contact them here:

Recurring Subscriptions: If you have canceled your recurring subscription on the day of renewal and have not downloaded any documents, you may request a refund by submitting an email to

Satisfaction Guarantee: If you’re not satisfied with your subscription, you can contact us for further help. Contact must be made within 3 business days of your subscription purchase and your refund request will be subject for review.

Please Note: Refunds can never be provided more than 30 days after the initial purchase date regardless of your activity on the site.