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Computer Networks

by: Earlene Cremin III

Computer Networks CPSC 5157G

Earlene Cremin III

GPA 3.91

Edward Bosworth

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Edward Bosworth
Class Notes
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This 14 page Class Notes was uploaded by Earlene Cremin III on Sunday October 11, 2015. The Class Notes belongs to CPSC 5157G at Columbus State University taught by Edward Bosworth in Fall. Since its upload, it has received 50 views. For similar materials see /class/221200/cpsc-5157g-columbus-state-university in ComputerScienence at Columbus State University.


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Date Created: 10/11/15
Review of Instruction Fetch We have discussed the common fetch sequence in previous lectures We have given both the sequence of microoperations and the corresponding sequence of control signals Remember that memory timings restrict access to memory during the Fetch Tl time slot so we elect to update the Program Counter during this time Fetch TO PC gt B1 tral B3 gt MAR READ Fetch T1 PC gt B1 1 gt B2 add B3 gt PC Fetch T2 MBR gt B2 tra2 B3 gt IR This lecture focuses on the impact of incrementing the program counter on 1 the design of the ALU and 2 the bus structure of the CPU It is immediately obvious that the ALU must have either an addition operation or an increment add 1 operation For simplicity the design uses a simple addition operation associated with the control signal add We have always assumed that the CPU has three internal data busses We now show why such a con guration is desirable Constraints Due to the ALU Recall that the ALU itself has two inputs and one output We consider how to create a bus structure for the CPU that will make ef cient use of this ALU For this discussion we focus on the addition operation associated with updating the PC Program Counter Inputl Input Output One Bus Design for the CPU The simplest design for the CPU calls for one common intemal bus The restriction that only one binary data set can be on a single bus at any given time gives rise to severe problems Speci cally it will take two clock pulses to put the two arguments PC and 1 on the bus and one clock pulse to transfer the updated value to the PC This oneibus design calls for two holding registers here called Y and Z The control signals required for this structure are T1 1gtBusBusgtY T3 Z gt Bus Bus gt PC W The addition takes three clock pulses It is easy to show that a 27bus design requires two clock pulses to perform the addition T2 PC gt Bus add Ef cient Addition Requires a Three Bus Structure Wch r I I I B3 I 1 E2 L V W r 39 39 quot d 39 impliucu by having 71 three bus stIucture It 39 quot 39 ill ee imemdi I I complexity ofthe CPU This is considered 71 good undeioff Immediate Implications of the Three Bus Design The design of the CPU calls for it to have three internal busses These are called B1 B2 and B3 B1 and B2 serve as input busses for the ALU B3 serves as an output bus for the ALU This design can be seen in another light B1 and B2 are the only busses to which any register can transfer data directly B3 is the only bus that can transfer data directly to any register The protocol for register to register transfer becomes as follows 1 Transfer from the source register to either bus B1 or bus B2 but not both 2 Signal the ALU to connect the appropriate input bus to bus B3 3 Transfer the contents of bus B3 to the destination register This implies two additional ALU control signals tral and tra2 tral transfer the contents of B1 to B3 tra2 transfer the contents of B2 to B3 More Requirements 0fthe Common Fetch Sequence Let s repeat the common fetch sequence and examine it for more requiremenm Fetch T0 PC gtB1 tral B3 gtMAR READ Fetch T1 PC gtB1 1 gtB2 add B3 gt PC Fetch T2 MBR gt B2 tra2 B3 gt IR T0 We have handled the requirements for bus transfer This demands the signal tral to the ALU The READ control signal goes to the memory interface T1 We have handled these requirements completely T2 Here we have two more registers to be assigned to input busses My earlier designs required that the Memory Buffer Register and Instruction Register be assigned to different busses so this design reflecm that Connecting the IR to Bus B1 The structure of the IR Instruction Register calls for bits to be sent directly to the Control Unit and bits to be sent to the bus B 1 We focus on the twenty lower order bits of the IR IR19 IRO In some instructions these bits IR19 IRO form an address for accessing memory In some instructions these bits IR19 IRO are interpreted as an immediate operand either a 20 bit flye hexadecimal digit bit mask or a 20 bit two s complement signed integer In some instructions bits IR19 IR17 are part of the instruction and bits IR16 IRO are not used In any case provision is made to transfer only bits IR19 IRO to bus Bl This transfer is enabled by the signal IR gt Bl Labeling Control Signals Control signals are Boolean signals with two Values Logic 1 Usually asserted as 5 Volts Logic 0 Usually asserted as 0 Volts Each control signal is labeled by the action that it enables R a B1 This signal enables the transfer ofIng 7 R0 to bus B1 It might be called 13M a B1 add Causes the ALU to add two integers Used by the ADD instruction Extend When R a B1 is asserted this causes the transferto be sign extended Control signals that enable data transfers to either bus B1 or bus B2 will take effect by enabling a triistate buffer The R is one of many possible inputs to B1 B1K IRK IR v B1 Sign Extension in Connecting the IR t0 Bus B1 39 D slrIRn 39 T Di and DI 39 L as a 327bit two seconiplernent integer to be sign extended and treated The 39 39 39 To handle this we have a control signal Extend which is emitted by the control unit 1 treat them as an Here is arepresentation ofthe transfer mechanism for the IR Address Pan oIIR IR EEEEEEEEEEEIH Bl II I I I I mmmaaazammzammm The Complete Connection Scheme for the Instruction Register Here is a schematic that shows the basic processes associated With the transfer The Control Unit emits both signals Extend and IR a B1 Only the latter is shown explicitly due to a desire to keep the gure uncluttered Extend T0 B13120 To 13119 IR Instruction Register To B1 13 Olinorle T0 Bl17 47 To B116 7 0 17 EEEEEEEEEEEEE Control Unit The General Purpose Registers In this version of the design the CPU has eight general purpose registers R0 This register is read only holding the value 0 R1 R7 These seven registers are readwrite and can be used for any purpose They are often used as index registers Each of these eight registers can output to either bus B1 or bus B2 Bus B3 can place data into any of the seven registers R1 R7 but is not connected to R0 B1 B2 B3 The Complete Register Set Here is the complete register set and bus structure for the CPU Note the two special purpose constant registers 1 and 71 used by the Control Unit Attaching the General Purpose Registers to the Bus Structure There are only three control signals emitted by the Control Unit that enable these transfers These are R gt B1 The selected register is copied to bus B l R gt B2 The selected register is copied to bus B2 B3 gt R The contents of bus B3 are copied into the selected register We now ask how each of these registers is selected The Control Unit uses three selector registers each based on bit elds in the IR The generation of these selector registers will be discussed later BlS This selects the register to be placed on B1 when R gt B1 is asserted B2S This selects the register to be placed on B2 when R gt B2 is asserted B3D This selects the register to copy the contents of B3 when B3 gt R is asserted If B3D 000 no transfer occurs Each of the signals B l S and B28 is the control input to an 8 to l multiplexer that outputs to a bus through a tri state buffer enabled by the appropriate control signal The signal B3D is the 3 bit input to an active high 3 to 8 decoder that is enabled by the control signal B3 gt R Figure Connecting a Single Bit t0 the Busses


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