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## DIGITAL CIRCUITS

by: Zackary King PhD

61

0

10

# DIGITAL CIRCUITS ENGR 160

Zackary King PhD
Eastern Washington University
GPA 3.92

Staff

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COURSE
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10
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KARMA
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## Popular in Engineering and Tech

This 10 page Class Notes was uploaded by Zackary King PhD on Sunday October 11, 2015. The Class Notes belongs to ENGR 160 at Eastern Washington University taught by Staff in Fall. Since its upload, it has received 61 views. For similar materials see /class/221505/engr-160-eastern-washington-university in Engineering and Tech at Eastern Washington University.

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Date Created: 10/11/15
51 Sequential Circuits Unlike combinational logic circuits the output of a sequential logic circuit depends not only on the current inputs but also on the current state of memory elements in the circuit The binary information stored in the memory elements determines the state of the circuit at any given time A typical sequential circuit consists of some combinational logic circuitry combined with memory elements to store the state of the circuit The current state of the circuit is fed back to the combinational logic and can be considered as additional inputs to the circuit This is called feedback There are two types of sequential logic circuits synchronous and asynchronous A synchronous sequential circuit is a circuit that changes state only at discrete instants of time The most frequently encountered is the clocked sequential circuit Typically synchronization is achieved by a timing deVice called a master clock generator Asynchronous sequential circuits can change state independently of time The memory elements in clocked sequential circuits are called ip ops 52 Latches I A ip op circuit has two outputs Q and Q I There are a variety of different ip op variations I A ip op can maintain a binary state inde nitely unless the power is turned off even after the input that resulted in its current state is removed I The most basic types of ip ops operate with signal levels and are referred to as latchs SR Latch Circuit I A latch can be constructed from two NAND or two NOR gates R Q S Q s I R SR Latches I These basic SR latches are asynchronous ip ops I Each circuit forms a basic latch upon which other more complicated types of ip ops can be built I Set state Q 1 Q 0 Clear state Q O Q 1 SR Latch With Control Input I The operation of the basic latch can be modi ed by providing an additional control input that determines when the state of the circuit is to be changed I Q t or just Q is referred to as the present state and represents the binary state of the latch before application of the clock pulse I Q t 1 referred to as the next state represents the binary state after the clock pulse I The state of the latch is free to change as long as CP is equal to 1 S Q CP Q R SR Latch With Control Input Reset 1 Set indeterminate D Latch I One way to eliminate the undesirable condition of the indeterminate state in the SR latch is to ensure that the inputs S and R never equal 1 at the same time I The D latch has only two inputs D and CP I The D stands for data I The state of the latch is free to change as long as CP is equal to 1 CF D Latch 53 FlipFlops The state of a latch or ip op is switched by a change in the control input This momentary change is called a trigger and the transition it causes is said to trigger the ip op In circuits with feedback there are serious drawbacks to the use of latches as storage elements The problem is that the latch responds to the level of the clock pulse and therefor is free to change state as long as the clock input is high The key to proper operation of a ip op is to trigger it only during a signal transition A clock pulse goes through two transitions One transition is from low to high and the other is from high to low There are two ways that a latch can be modi ed to form a ip op One way is to employ two latches in a special configuration that isolates the output of the ip op from being affected while its input is changing Another way is to produce a ip op that triggers only during a signal transition and is disabled during the rest of the clock pulse duration EdgeTriggered D FlipFlop I Edge triggered ip ops respond only to a clock pulse edge and not to the level of the of the clock pulse I Edgetriggered ipflops can be either positive or negative edge sensitive Positive pulse Negative pulse 0 i i l T Positive Negative Negative Positive edge edge edge edge De nition of clock pulse transition I One type of edgetriggered ip op is the masterslave ip op It is constructed from two separate ipflops and an inverter I The master latch is triggered on the leading edge of the clock pulse and the slave on the trailing edge I Only one latch is enabled at a time I The master latch is enabled when the clock input is high and the slave is enabled when it is low This behavior could be reversed with the addition of an inverter on the clock input I In a masterslave flip op it is possible to switch the output of the ip op and its input information with the same clock pulse I The masterslave combination can be constructed for any type of ipflop by adding a clocked SR latch with an inverted clock to form the slave s S S Q C Master C Slave Y R R R Q A CP 1 MASTERSLAVE FLlPFLOP FIGURE 59 Logic diagram of a master slave ipflop CF L Timing relationships in a master slave ip op A more efficient construction of an edgetriggered D ip op uses three SR latches In this design two latches respond to the external data and clock inputs The third latch provides the outputs for the ip op The S and R inputs of the output latch are maintained at a logic 1 level when CLK O This causes the output to remain in its present state If D 0 when CLK becomes 1 R changes to O resetting the output latch Q O If there is a change in D while CLK 1 R remains 0 locking out further change When CLK returns to O R changes to 1 placing the output latch in the quiescent state without changing its output Setup time is the time period the input must be held stable before the clock edge occurs Hold time is the time period the input must be held stable after the clock edge occurs CP lt FIGURE 510 D type positiveedgetriggered ip op J K Flip Flops T Flip A JK ip op is a re nement of the SR latch in that the indeterminate state of the SR type is de ned in the JK type Inputs Jand Kbehave like inputs S and R to set and clear the ip op respectively When both inputs Jand Kare equal to 1 the ip op switches to its complement state ie if Q 1 it switches to Q O and Vice versa The plain JK ip op has a serious drawback Flops The T ip op is a single input version ofthe JK ip op The T ip op is obtained from the JK ip op by connecting the Jand Kinputs together The T stands for toggle because when the T input is equal to 1 the output will switch to its complement state T ip ops have the same drawback alluded to earlier with the JK ip ops Direct Inputs The preset input sets the ip op asynchronously The clear input clears the ip op asynchronously They are usually employed to guarantee that the circuit starts in a know state at power up Graphic Symbols Characteristic Tables and Equations J39K J39K QJ39K IJ K J Kl JQ K Q Qt l TQ T Q Qt l D QI 1

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