DIGITAL CIRCUITS ENGR 160
Eastern Washington University
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This 55 page Class Notes was uploaded by Zackary King PhD on Sunday October 11, 2015. The Class Notes belongs to ENGR 160 at Eastern Washington University taught by Staff in Fall. Since its upload, it has received 23 views. For similar materials see /class/221505/engr-160-eastern-washington-university in Engineering and Tech at Eastern Washington University.
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Date Created: 10/11/15
11 Digital Computers and Digital Systems Digital Systems I A digital system manipulates discrete elements of information I meaningful symbols alphanumeric characters arithmetic operators etc I signals electrical signals 7 voltages and currents signals are binary in nature 7 two states more states would reduce reliability I examples digital watch electronic calculator remote control digital instruments etc Analog Systems I An analog system manipulates a continuous signal I An analog signal is a continuous signal analogous to a process or quantity electrical signals 7 voltages and currents signals are continuous in nature 7 an in nite number of states between min and max I example The electrical signal supplied to a speaker system is an analog of the sound waves Digital Computers A digital computer is a general purpose machine It becomes a speci c machine e g a word processor intemet browser CD player etc when it is programmed as such Before electronic digital computers human beings who calculated for a liVing were called computers Control Processor umt 7 arithmetic unit A l V Storage or gt memory unit A V Input Output deViceS devices and control and control FIGURE 11 Block diagram of a digital computer block diagram control unit 7 internal control processor 7 arithmetic and logic operations storage memory 7 short term RAM long term ROM magnetic media input 7 keyboard mouse etc output 7 monitor printer speakers etc programs data binary digit 7 bit byte 7 8 bits word 7 8 16 32 or 64 bits 12 Binary Numbers base or radix is the number of unique symbols in the number system I 35 a4 a3 a2 a1 a0 11 12 13 a coefficients are one ofrdigits where ris the radix I j gives the place value 7 power of r The old familiar decimal number system base 10 I ten symbols 7 0 1 2 3 4 5 6 7 8 9 I 10n combinations where n is the number of digits I example 7 0 9210 can be written as 710301029101210 71000010091021 7000 90 2 709210 The binary number system base 2 I two symbols 7 0 1 I 2n combinations where n is the number of digits I example 10112 can be written as 12302212112 The octal number system base 8 I eightsymbolsio 1 2 3 4 5 6 7 I 8 combinations where n is the number of digits I example 107 28 can be written as 183O82781280 1 39 512 O 39 64 7 39 8 2 39 1 512 56 2 57010 The hexadecimal hex number system base 16 I sixteensymbolsio 1 2 3 4 5 6 7 8 9 A B c D E F I 16 combinations where n is the number of digits I example B 65F16 can be written as 111636162516115160 1140966256516151 45056 1536 80 15 46687m Arithmetic operations on numbers with different bases examples Binary Octal Decimal Hexadecimal 111 777 999 FFF g g L 1000 1000 1000 1000 7 511 999 4095 l l l l 8 512 1000 4096 Addition Subtraction Multiplication 10010101 10010101 1010 10001101 10001101 X 101 100100010 00001000 1010 0000 1010 110010 13 Number Base Conversations Convert binary 1 1 O 1 O 1 to decimal 1101012122121o2 12 102 21 42o5o125 662510 Convert octal 7 03 5 to decimal 70358782O8138058391 764083150125 448 3 0625 45162510 Convert hex FOAS to decimal F0A516151630 1621O1615160 15394096O392561039l6539l 61440 160 5 6160510 Convert decimal 57 to binary Integer Mm m smotient 57 2 7 28 1 a0 1 28 2 14 0 a1 0 14 2 7 0 a2 0 72 3 1 a3 1 3 2 1 1 a4 1 1 2 o 1 a5 1 5710 1110012 Convert decimal 173 to octal Integer Remainder g gotient 173 8 7 21 5 21 8 2 5 2 8 0 2 17310 2558 Convert decimal 1019 to hex Integer Remainder g gotient 1019 16 63 11 63 16 3 15 3 16 0 3 101910 3FB16 Convert hex FOA5 to binary F 1111 0 0000 A 1010 5 F0A516 11110000101001012 Convert octal 7 025 to binary 7111 0000 2010 5 70258 1110000101012 Convert decimal 0 3 7 5 to binary Integer Remainder Product 0375 2 0 075 075 2 1 050 050 2 1 000 037510 00112 Coef cient Coef cient a0 11 a1 15 a2 3 0101 101 Coef cient Convert decimal 6 25 to binary step 1 7 convert the integer part Integer Remainder Coef cient g gotient 6 2 3 0 a0 0 3 2 1 1 a1 1 1 2 0 1 a2 1 610 1102 step 2 7 convert the fractional part Integer Remainder Coef cient Product 025 2 0 050 a1 0 0502 1 000 51271 02510 0012 step 3 7 add the results from the rst two steps 62510 7 110012 To check the answer convert the binary number back to decimal 11001271221210 2002 112 2 4 2 025 7 62510 Some decimal fractional numbers cannot be represented in binary exactly One example is 07 Integer Remainder Coef cient Product 07 2 1 04 311 1 04 2 0 08 312 0 08 2 1 06 a3 1 06 2 1 02 314 1 02 2 0 04 515 0 04 2 0 08 516 0 08 2 1 06 a4 1 14 Octal and Hexadecimal Numbers Octal To convert binary to octal group the binary digits in groups of three beginning with the least signi cant digit Convertbinary 111101011001 to octal 1111010110012 111 101 011 001 75318 Hexadecimal To convert binary to hexadecimal group the binary digits in groups of four beginning with the least signi cant digit Convertbinary 111101011001 to hex 11110101100116 1111 0101 1001 F 5 9 F5916 Converting Hex t0 octal and octal to hex To convert hex to octal or octal to hex convert to binary as an intermediate step 15 Complements Diminished Radix Complement Given a number N in base r having n digits the r 7 1 s complement of N is de ned as N 7 1 7 N For decimal numbers I r 10amdltr7 1 7 9 I 1011 represents a number that consists of a single 1 followed by n 0 s example 104 10000 I 1011 7 1 is anumber represented by n 9 s I 9 sc0mplement0fNis 1011 7 1 7 N example 9 s complementof4321o is 99999 7 43210 7 56789 I The 9 s complement of a decimal number is obtained by subtracting each digit from 9 For binary numbers I r72andr71 1 I 211 represents a number that consists of a single 1 followed by n 0 s example 24 10000 I 2n 7 1 is anumber represented by n 1 s I 1 sc0mplement0fNis 2n 7 1 7 N example1 s c0mplement0f1010 is 1111 7 1010 01012 The 1 s complement of a binary number is obtained by subtracting each digit from 1 Radix Complement The r s complement ofan ndigit number in base r is de ned as r 7 Nfor N 0 and O for N O The 10 s complement of 43210 7 100000 7 43210 7 567 90 Observe that the 10 s complement of N is 1 more than the 9 s complement The 2 s complement of 1010 7 10000 7 1010 7 0110 Observe that the 2 s complement of N is 1 more than the 1 s complement To take the 2 s complement the easy way 7 invert all digits and add 1 example the 2 s complement of 10 01 is 1001 gt 0110 1 01112 16 Signed Binary Numbers How are binary numbers represented in a computer byte E 8 bits E 8 binary digits 28 256 unique combinations word 7 either 8 16 32 or 64 bits depending on the architecture VS We will assume an 8bit computer so the unsigned range is 0000 0000 to 1111 1111 or 0 to 255 How are signed biliary numbers represented in a computer Three possibilities signed 7 magnitude example 9 is represented by 1 0 0 0 1 0 0 1 1 s complement example 9 is represented by 1 11 1 0 1 10 2 s complement example 9 is represented by 1 11 1 0 1 11 We will use 2 s complement because it is the most widely used in modern computers For an 8bit word the signed range is 1000 0000 to 0111 1111 or 128 to 127 Note 0 is considered positive Evaluate signed biliary numbers by converting to decimal as follows 2 s Complement 10111 8041211 8 2 1 5 1 s Complement 10101 8041201 8 2 6 addl 6 1 5 Addition of signed binary numbers using 2 s complement 0000 0101 5 1111 1011 5 0000 1110 14 0000 1110 14 0001 0011 19 1 0000 1001 9 0000 0101 5 1111 1011 5 1111 0010 14 1111 0010 14 1111 0111 9 1 1110 1101 19 The extra bit is called an over ow and is stored separately from the byte representing the sum Subtraction of binary numbers using 2 s complement iA 7 B iA B iA 7 B iA 3 5 7 14 5 14 19 The minuend is 0000 0101 510 andthe subtrahend is 1111 0010 1410 Step 1 Take the 2 s complement of the subtrahend 1111 00 10 1111 0010 gt 0000 1101 1 0000 1110 Step 2 Add the two numbers 0000 0101 0000 1110 0001 0011 How does the computer know if 1100 1000 means 200 or 56 It doesn t 7 it is up to the programmer to interpret the results unsigned arithmetic signed arithmetic 1000 0101 133 1000 0101 123 0100 0011 67 0100 0011 67 1100 1000 200 1100 1000 56 17 Binary Codes BCD I The rst ten binary code combinations I Each decimal digit requires 4 binary digits example 63 in binary is 00111111 63 in BCD is 0110 0011 ASCII Character Code I American Standard Code for Information Interchange I encodes alphanumeric characters and control characters XS3 I First ten binary code combinations with each value being 3 more than the value being represented example 0 in binary is 0000 0 inXS3 is 0011 84 2 1 Special weighting used for each place example 7i1184 2 1is 1001 8 I 1 7 1001 8040 21 1 l 8 1 7 Error Detection Code Parity 7 an additional bit added to the data to make the total number of ones odd odd parity or even even parity Gray Code valent 19 Binary Logic De nition of Binary Logic Binary logic consists of binary variables and logic operations I Boolean algebra I variables take on two discrete values true false yes no on off 1 0 5v 0v hot cold I Three basic logic operations AND X Y Zor XY Z X AND YiS equal to Z Z is true if and only if X is true and Y is true otherwise Z is false The alarm will sound if the system is armed and someone touches the car 1 1 1 1 0 0 OR X X Z XOR YiS equal to Z Z is true if X is true or YiS true otherwise Z is false 101 000 1111 NOT X Z notX is equal to Z Z is true if X is false Z is false ifX is true unary operator Truth T ables Switching Circuits and Binary Signals L mvwav LAB LAB Logic Gates A logic gate performs one and only one logic operation not strictly true a some also include NOT operations A logic circuit is composed ofone or more logic gates and all interconnections NOT Gale lnvenev x zx x zoommoons kw v x l kw x zoommoons NOTGale kw GD 39 v x ZrlnpulOR39Gale bx v x ZrlnpulNORGale 1mm x ZrlnpulOR39Gale NOTGale 1mm v v E A SrlnpulANDGale mm B A SrlnpulORGale mm c c Timing Diagrams EEEEB gt m N 31 The Map Method Kamaugh Maps I AKarnaugh map is a diagram made up of squares used for the purpose of simplifying Boolean functions I The Kamaugh map is like a graphical representation of a truth table I Each square in the map represents one minterm of a Boolean function I The map represents all possible ways a function can be expressed in standard form I Any two adjacent squares differ by only one variable which is primed in one square and unprimed in the other Two and Three Variable Maps I A generic twovariable map Representation of functions in a two variable map example f1 7 XY example f2 x y X 0 O l l I A generic threevariable map X 0 O O O l l l l l l OOl l OO l Ol Ol Ol ON Simplifying Boolean functions I To simplify a function with a Karnaugh map group adjacent squares containing ls I Groups must be powers oftwo eg l 2 4 8 etc Adjacent squares are any squares which differ by only one literal even if they are not next to each other Strive to make the largest groups possible Group squares which can only be grouped one way rst When all ls have been grouped you re done A 1 may be grouped more than once example Simplify the Boolean function FX y z FXyZ 20 2 4 6 7 X z Xyz xz xyzy z y 2 W lyz x l 0 0 l x l 0 l l Step 1 7 grouping Make a group offour by grouping m0 m2 m4 and m6 z Make a group of two by grouping m7 and m6 xy Step 2 7 read the terms from each group and sum them FXyz Xy 2 Why does a Kamaugh map work I A Kamaugh map works because two adjacent squares differ by only one variable When these two squares are grouped the variable that differs will be eliminated because any variable ORed with its complement is l The number of variables eliminated from a term is related to the size of the group eliminated example from a threevariable map 1m m5 X y z Xy z y zx X y z example Simplify the Boolean function FAB C 7 A BC AB A BC FABC 22 3 6 7 ABC B C B C BC BC A 0 0 l A 0 0 l l Step 1 7 grouping Make a group offour by grouping m2 m3 m6 and m7 B Step 2 7 read the terms from each group and sum them F X y Z B example Simplify the Boolean function FAB C 20 5 7 ABC B C B C BC BC A l 0 0 A 0 l l 0 Step 1 7 grouping Make a group ofone with me A B C Make a group of two by grouping m5 and m7 AC Step 2 7 read the terms from each group and sum them Fxy z A B C AC example Simplify the Boolean function FAB C 7 AB AB C AB AB C C AB C AB C FABC 7 24 5 ABC B C B C BC BC A 0 0 0 0 A l l 0 Step 1 7 grouping Make a group oftwo by grouping m4 and ms AB Step 2 7 read the terms from each group and sum them F A B C AB 32 FourVariable Maps I A generic fourvariable map HHHHHHHHOOOOOOOOS HHHHOOOOHHHHOOOODG gt gt gt gt gt 39gt 39OOgt 39gt 39OO HOHOHOHOHOHOHOHON example Simplify the Boolean function FA B C D A B CD ABCD A BD ABC D ABC D A BC D A BC D A B C D A BD 14393ch c39 A BCD A BC D FABCD 21 3 4 5 6 12 13 14 ABCD C D C D CD CD A B O l l O A B l l O 1 AB 1 l O 1 AB 0 O O O Step 1 7 grouping Make a group oftwo by grouping m1 and m3 A B D Make a group offour by grouping m4 m5 M12 and m13 Make a group offour by grouping m4 M12 m6 and H14 Step 2 7 read the terms from each group and sum them FA Prime Implicants B 013 A B D BC BE A prime I mplicant is a product term obtained by combining the maximum possible number of adjacent squares in the map implicant An essential prime implicant is a minterm in a square covered by only one prime The procedure for nding the simpli ed expression from the map requires that we rst determine all the essential prime implicants The simpli ed expression is obtained from the logical sum of all the essential prime implicants plus other prime implicants that may be needed to cover any remaining minterms not covered by the essential prime implicants example Find the prime implicants and essential prime implicants for the Boolean function FAB 00 7 21 3 5 7 8 9 10 11 12 13 ABCD C D C D CD CD A B O l l O A B O l l 0 AB 1 l O 0 AB 1 l l l Step 1 7 nd largest possible groups group 1 m1 m3 m5 and m7 A D group 2 m1 m3 m9 and m11 B D group 3 M12 M13 m8 and m AC group 4 m1 m5 M13 and m C D group 53 1H8 m9 Inn and mm AB Step 2 7 identify essential prime implicants essential prime implicants A D AC AB Step 3 7 identify prime implicants prime implicants B D C D 33 FiveVariable Maps A generic vevariable map example Simplifythe Booleanfunction FABCDE 20 2 4 6 9 13 21 23 25 29 31 BCDE D E D E DE DE B C l O O l B C l O O 1 BC 0 l O 0 BC 0 l O 0 AI BCDE D E D E DE DE B C O O O O B C O l l 0 BC 0 l l 0 BC 0 l O O A Step 1 7 grouping Make a group offour by grouping m0 m4 m2 and m6 A B E Make a group offour by grouping M21 mg mg and m31 ACE Make a group offour by grouping M13 mg mg and ms BD E Step 2 7 read the terms from each group and sum them FA B CD E A B E ACE BD E example Simplifythe Booleanfunction FABCDE 20 2 4 6 16 18 20 22 26 30 BCDE D E D E DE DE B C l O O l B C l O O 1 BC 0 O O 0 BC 0 O O 0 AI BCDE D E D E DE DE B C l O O l B C l O O 1 BC 0 O O 1 BC 0 O O l Step 1 7 grouping Make a group of eight by grouping m0 m4 m2 mg mg M20 mm and m22 B E Make a group offour by grouping mm m22 mgo and m26 ADE Step 2 7 read the terms from each group and sum them FA B CD E B E ADE example Simplifythe Booleanfunction FAB CDE 21 3 9 11 13 29 BCDE D E D E DE DE B C O l l O B C O O O 0 BC 0 l O 0 BC 0 l l 0 AI BCDE D E D E DE DE B C O O O O B C O O O 0 BC 0 l O 0 BC 0 O O O Step 1 7 grouping Make a group offour by grouping m1 mg mg and m11 A C E Make a group oftwo by grouping M13 and m29 BCD E Step 2 7 read the terms from each group and sum them FA B CD E A C E BCD E 34 Product Of Sums Simpli cation I The minimized Boolean functions derived from the maps in all previous examples were expressed in sum of products form I With a minor modi cation the product of sums form can be obtained I The 1s placed in the squares of the map represent the minterms of the function F I The OS represent the minterms of the complement of the function ie F I The complement of F is the original function F I Because of the generalized DeMorgan s theorem the function so obtained is automatically in the product of sums form example Simplify the Boolean function FAB 00 7 E 1 3 4 5 6 12 13 14 in both sum of products and product of sums form FABCD 7 21 3 4 5 6 12 13 14 ABCD C D C D CD CD A B O l l O A B l l O 1 AB 1 l O 1 AB 0 O O O sum of products Step 1 7 grouping Make a group oftwo by grouping m1 and m3 A B D Make a group offour by grouping m4 m5 M12 and m13 BC Make a group offour by grouping m4 M12 m6 and H14 BD Step 2 7 read the terms from each group and sum them FABCD 7 A B D BC BD product of sums Step 1 7 grouping Make a group offour by grouping m0 m2 m8 and mm B D Make a group offour by grouping m8 mg ml and mm AB Make a group of two by grouping m7 and m15 BCD Step 2 7 read the terms from each group and sum them F AB 013 B D AB Step 3 7 apply DeMorgan s theorem F 39 B D AB BOD FA B 013 B DA B B c39 D 375 Don tsCare Conditions I For some functions not all input combinations are valid eg afunction who s input will be coded in BCD BCD uses only 10 ofthe possible 16 combinations as i i ii Melon care conditions Including don tcares in aKamaugh map is away to achieve further simpli cation Don tcares are represented on arnap with an X Individual don tcares are read as either azero or a one whichever results in the greater simplification Example FABCD 2EI 2 4 6 E This is afunction to light an LED ifan even number is input The input will be in BCD so minten39ns 1n11121314and 15 are don tcares First without the don tcares FABCD A D B C D Without don tcares Now with the don tcares FABCD D D 0 4 r With don tcares Now the same problem but we will simplify pr F ABCD D ABCD D 3 6 NAND and NOR Implementation Digital circuits are more frequently constructed With NAND or NOR gates than With AND and OR gates NAND and NOR gates are easier to fabricate NAND and NOR gates may be represented using alternative symbols Inverters NOT may be represented by NAND and NOR gates Whose inputs are all connected together y liqx FX39y z xyz39 ANDinvert lnvert 0l a Two graphic symbols for NAND gale x 2 FXyy y Fx39y39z39xyz39 z ORinven llivert AND b Twu graphic symbols for NOR gate BufferInverl ANDinvert JRinvert 0 Three graphic symbols for invcrlcr FIGURE 34 7 Graphic symbols for NAND and NOR gates NAND Implementation I Requires the Boolean function to be simplified in SOP form Method 1 two logic levels 1 Simplify the function and express it in SOP form 2 Draw Levell gates I One 2input NAND gate with both inputs connected together for each primed literal One 2input NAND gate with both inputs connected together for each unprimed literal that will go directly to Level2 One n input NAND gate for each product term 3 Draw Level2 gate I One n input NAND gate using the INVERTOR symbol Method 2 three logic levels 1 Simplify the complement of the function and express it in SOP form 2 Draw Levell gates I One 2input NAND gate with both inputs connected together for each primed literal I One 2input NAND gate with both inputs connected together for each unprimed literal that will go directly to Level2 I One n input NAND gate for each product term 3 Draw Level2 gate I One n input NAND gate using the INVERTOR symbol 4 Draw Level3 gate I One 2input NAND gate with both inputs connected together to invert the function Example F MD 2 4 6 7 Method 1 NAND logic FABC ANDORlNVERT Logic A A j39 a W C r C NAND Logic Example F MD 2r 439 6 7 Method 2 NAND 1 gi A gt At a gt07 at AND ORNVERT Logic NAND Logic Example F H71315 Method 2 NAND logic A ABD D ABD BCD ABD acm39 F a c BCD ANDORlNVERT Logic mam ABD 3ch F 13cm NAND Logic NOR Implementation I Requires the Boolean function to be simplified in POS form Method 1 two logic levels 1 Simplify the function and express it in POS form 2 Draw Levell gates I One 2input NOR gate with both inputs connected together for each primed literal I One 2input NOR gate with both inputs connected together for each unprimed literal that will go directly to Level2 I One n input NOR gate for each product term 3 Draw Level2 gate I One n input NOR gate using the INVERTAND symbol Method 2 three logic levels 1 Simplify the complement of the function and express it in POS form 2 Draw Levell gates I One 2input NOR gate with both inputs connected together for each primed literal I One 2input NOR gate with both inputs connected together for each unprimed literal that will go directly to Level2 I One n input NOR gate for each product term 3 Draw Level2 gate I One n input NOR gate using the INVERTAND symbol 4 Draw Level3 gate I One 2input NOR gate with both inputs connected together to invert the function Example F MEI 2 4 a 7 Method 1 NOR logic A w c HADD g tAoc mam F a acc AND ORNVERT Logic A Ad 39 cm i 39gtm wwwc F a m c1 NOR Logic Example F 2Ely 2 4y 6 7 Method 2 NOR logic A E A39 a B RAD ED mum una39yr F c r AND ORNVERT Logic A gt43 Ana 393 D BWMCCD tA39omcr F c mgr NOR Logic 51 Sequential Circuits Unlike combinational logic circuits the output of a sequential logic circuit depends not only on the current inputs but also on the current state of memory elements in the circuit The binary information stored in the memory elements determines the state of the circuit at any given time A typical sequential circuit consists of some combinational logic circuitry combined with memory elements to store the state of the circuit The current state of the circuit is fed back to the combinational logic and can be considered as additional inputs to the circuit This is called feedback There are two types of sequential logic circuits synchronous and asynchronous A synchronous sequential circuit is a circuit that changes state only at discrete instants of time The most frequently encountered is the clocked sequential circuit Typically synchronization is achieved by a timing deVice called a master clock generator Asynchronous sequential circuits can change state independently of time The memory elements in clocked sequential circuits are called ip ops 52 Latches I A ip op circuit has two outputs Q and Q I There are a variety of different ip op variations I A ip op can maintain a binary state inde nitely unless the power is turned off even after the input that resulted in its current state is removed I The most basic types of ip ops operate with signal levels and are referred to as latchs SR Latch Circuit I A latch can be constructed from two NAND or two NOR gates R Q S Q s I R SR Latches I These basic SR latches are asynchronous ip ops I Each circuit forms a basic latch upon which other more complicated types of ip ops can be built I Set state Q 1 Q 0 Clear state Q O Q 1 SR Latch With Control Input I The operation of the basic latch can be modi ed by providing an additional control input that determines when the state of the circuit is to be changed I Q t or just Q is referred to as the present state and represents the binary state of the latch before application of the clock pulse I Q t 1 referred to as the next state represents the binary state after the clock pulse I The state of the latch is free to change as long as CP is equal to 1 S Q CP Q R SR Latch With Control Input Reset 1 Set indeterminate D Latch I One way to eliminate the undesirable condition of the indeterminate state in the SR latch is to ensure that the inputs S and R never equal 1 at the same time I The D latch has only two inputs D and CP I The D stands for data I The state of the latch is free to change as long as CP is equal to 1 D Latch 53 FlipFlops The state of a latch or ip op is switched by a change in the control input This momentary change is called a trigger and the transition it causes is said to trigger the ip op In circuits with feedback there are serious drawbacks to the use of latches as storage elements The problem is that the latch responds to the level of the clock pulse and therefor is free to change state as long as the clock input is high The key to proper operation of a ip op is to trigger it only during a signal transition A clock pulse goes through two transitions One transition is from low to high and the other is from high to low There are two ways that a latch can be modi ed to form a ip op One way is to employ two latches in a special con guration that isolates the output of the ipflop from being affected while its input is changing Another way is to produce a ipflop that triggers only during a signal transition and is disabled during the rest of the clock pulse duration EdgeTriggered D FlipFlop I Edge triggered ip ops respond only to a clock pulse edge and not to the level of the of the clock pulse I Edgetriggered ip ops can be either positive or negative edge sensitive Positive pulse Negative pulse 0 i i l T Positive Negative Negative Positive edge edge edge edge De nition of clock pulse transition I One type of edgetriggered ip op is the masterslave lp op It is constructed from two separate ip ops and an inverter I The master latch is triggered on the leading edge of the clock pulse and the slave on the trailing edge I Only one latch is enabled at a time I The master latch is enabled when the clock input is high and the slave is enabled when it is low This behavior could be reversed with the addition of an inverter on the clock input I In a masterslave flip op it is possible to switch the output of the ipflop and its input information with the same clock pulse I The masterslave combination can be constructed for any type of flipflop by adding a clocked SR latch with an inverted clock to form the slave s s Y s Q C Master C Slave R R R Q A CP lv MASTERSLAVE FLlPFLOP FIGURE 59 Logic diagram of a master slave ip op CF L Timing relationships in a master slave ip op A more efficient construction of an edgetriggered D ip op uses three SR latches In this design two latches respond to the external data and clock inputs The third latch provides the outputs for the ip op The S and R inputs of the output latch are maintained at a logic 1 level when CLK O This causes the output to remain in its present state If D 0 when CLK becomes 1 R changes to O resetting the output latch Q O If there is a change in D while CLK 1 R remains 0 locking out further change When CLK returns to O R changes to 1 placing the output latch in the quiescent state without changing its output Setup time is the time period the input must be held stable before the clock edge occurs Hold time is the time period the input must be held stable after the clock edge occurs CP lt FIGURE 510 D type positiveedgetriggered ip op J K Flip Flops T Flip A JK ip op is a re nement of the SR latch in that the indeterminate state of the SR type is de ned in the JK type Inputs Jand Kbehave like inputs S and R to set and clear the ip op respectively When both inputs Jand Kare equal to 1 the ip op switches to its complement state ie if Q 1 it switches to Q O and Vice versa The plain JK ip op has a serious drawback Flops The T ip op is a single input version of the JK ip op The T ip op is obtained from the JK ip op by connecting the Jand Kinputs together The T stands for toggle because when the T input is equal to 1 the output will switch to its complement state T ip ops have the same drawback alluded to earlier with the JK ip ops Direct Inputs The preset input sets the ip op asynchronously The clear input clears the ip op asynchronously They are usually employed to guarantee that the circuit starts in a know state at power up Graphic Symbols Characteristic Tables and Equations J39K J39K QJ39K IJ K J Kl JQ K Q Qt l TQ T Q Qt l D QI 1
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