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Intro Digital Elect

by: Mr. Jaime Stracke

Intro Digital Elect EEE 4343

Mr. Jaime Stracke
GPA 3.66

Sanwei Jeffrey Fan

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Sanwei Jeffrey Fan
Class Notes
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This 66 page Class Notes was uploaded by Mr. Jaime Stracke on Monday October 12, 2015. The Class Notes belongs to EEE 4343 at Florida International University taught by Sanwei Jeffrey Fan in Fall. Since its upload, it has received 35 views. For similar materials see /class/221799/eee-4343-florida-international-university in Electrical Engineering at Florida International University.


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Date Created: 10/12/15
Dr Miamiicpu lic reward university EEE 4343 Introduction to Digital Electronics Department of Electrical and Computer Engineering Florida International University Instructor Dr Jeffrey Fan Fan 7 55543 437n0t52 MOSFE T Amplifier or Switch Transfer Characteristics 39n Wax V121 Triode gt f Saturation i Vun I I 1w gt Vm I V RD C m Vm w IB H e w 1rmlt v I Io l Q w Q W ms V10 39 I L mixing 2 I slope r NIB 1 m I A U Vm Vim Via V Vng Vuer Vim m we a Basic structure of the commonsource amplifieri h b Graphical construction to determine the transfer characteristic of the amplifier Dx Fan 7 m43437not aeQ ingtlt z in Q Cuklll sammlmn uinde rcgmn x A Slope at Q oltuge gain 75 ilkK V A VW Ver 7 er V n m er quot2 V2 1 L 1 lt 1 1 V Ty me C c Transfer characteristic showing operation as an ampli er biased at point Q Quiescent Point dc bias operated on certain VGS and ID apply small signal Vgs to be ampli ed slope is considered linear Dr Fan 7 eee43437nole2 Design Consideration 391 Mm 115 Two load lines and corresponding bias pointsi Bias point Q1 does not leave sufficient room for positive signal swing at the drain too close to VDD Bias point Q2 is too close to the boundary of the triode region and might not allow for sufficient negative signal swingi Somewhere in between is better Dr Fan 7 m43437n0t52 Bias Techniques and Design Considerations Biasing in MOS Amplifier by xing Vss in Device 2 Device l quot The use of fixed bias constant VGS can result in a large variability in the value of ID Devices 1 and 2 represent extremes among units of the same type Thus it may not be a good technique vm 1 0 Dr Fan 7 magma Biasing by xing VG and connecting resistance to source VIII A ll Rm RN 1 l Dcvicc 2 Device I H IH O l V ltgt I I J i l l In I V2 7 1 inquot s r R R3 lm iiiquot m V Isz R L gt VI vm by c Biasing using a fixed voltage at the gate Vg and a resistance in the source lead RS Degeneration resistance a basic arrangement b reduced variability in I c practical implementation using a single power supply Dr Fan 7 66943437110162 VIII quotan I l J If M quot2 R 39 Biasing using a fixed voltage at the gate V6 and a resistance in the source lead RS 1 coupling of a signal source to the gate using a capacitor CCI e practical implementation using two power supplies Dr Fan 7 66943437110162 Bias large draintogate feedback resistance Ra Vm Biasing using DminrtorGate feedback Iesistor one power supply 1 m 7 emoumz Van Vim A V a b a Biasing the MOSFET using a constantrcurtent source I b 39 of 39h 39 39 39 lusing m m 7 amoumcz MOSFET as a smallsignal amplifier A small signal is applied in V55 noted as Vg Common Somme Ampli er dc bias to saturation legion m m 7 amoumcz n lint almosl 7 SIK r 39se menl we km r 391 Q I V I Vm 1 k vmij ltgt gtuw Smallrsignal operation of the enhancement MOSFET ampli er gm transconductance m megame 3 127V 7777 v T 1 i i 4 J Um rm 1 1 ltlt 2ltvl W l l l l n l l y i l l l l l i l l l i l T39mm s V MRn V v o 7 Total instantaneous voltages VGS and VD To insure linear operation Inin VD should not fall below VG by more than Vt The max should be smaller than VDD otherwise FET enters cutoff region Dr Fan 7 eee43437note2 n lb Smallrsignal models for the MOSFET a neglecting the dependence of iD on vm in saturation the channelrlength modulation effect b including the effect of channelrlength modulation modeled by output Ieslstance r0 gtlt D m megame 5 T equivalent circuit model for the M OSFET ltgt 2 ltgt r0 has been omitted but can be added between D and S in the T model of 1 Dr Fan 7 9 A3437n01 2 a T model of the MOSFET augmented with the draintosource resistance r0 b An alternative representation of the T rnodel Dr Fanr mmumz D G 0 0 o o B I gymAx I u mm wk G 0 l B S a b Smallsignal equivalentcircuit model of a MOSFET in which the source is not connected to the ody Dr Fanr mmumz Small Signal Equivalent Circuit Models G 0 0 up of Suth Dr Fan 7 gunman vim Single Stage MOS Amplifier V Basic stmctute of the cimuit used to realize singlerstage discretercimuit MOS ampli er configurations m m 7 amoumz Characteristic Parameters ofAmpli ers Dr Fan 7 eee43437notez vul A 5quot gmvg m w 72 MNUMV l y m a Common source CS source grounded ampli er b C Equivalent circuit of the ampli er for small signal analysis V Small signal analysis performed directly on the ampli er circuit with the MOSFET model implicitly utilized Dr Fan 7 66M3437n01 2 V n M a Common source amplifier With a resistance RS in the source lead b Small signal equivalent circuit With r0 neglected Dr Fan 7 eee4343notez G VW 3940 T a A common gate CG Gate grounded amplifier b A small signal equivalent circuit of the amplifier in a c The common gate amplifier fed With a current signal input Dr Fan 7 eee43437note2 l quotE a A common drain source follower amplifier b Small signal equivalent circuit model c Small signal analysis performed directly on the circuit 1 Circuit for determining the output resistance Rout of the source follower Dr Fan 7 66943437110162 Common Source CS 39 in Dr Fan 7 eee43437note2 Common Gate CG and Common Drain Source Follower VIIA Dr Fan 7 gunman Dr Miamiicpu lic reward university EEE 4343 Introduction to Digital Electronics Department of Electrical and Computer Engineering Florida International University Instructor Dr Jeffrey Fan Fan eee43437note1 MOS Field Effect Transistors MOSFETs Device Structure and Device Physics GO 39 B GO 39 B GO l m b c a Circuit symbol for the nychannel enhancementpre MOSFET 1 Modi ed circuit symbol with an arrowhead on the source terminal to distinguish it from the drain and to indicate device polarity ie n channe c Simpli ed circuit symbol to be used when the source is connected to the body or when the effect of the body on device operation is unimpo ant S Source G Gate D Drain B Bulk Dv Fan eeeABABJotet region plype suhsrrale Rudy 39lmnne region Dxuin region J Device Structure Oxide sing Source S Gme 1G Dmm D quot39 Metal 4 A 4 Channel t quot region H L Hype substrate Body Body In Physical structure of the enhancement type NMOS transistor a perspective View b cross section Typically L 01 to 3 urn channel length less than 01 7 nanometer n heavily doped n type silicon W 02 to 100 urn channel Width used as resistors or capacitors Thickness of the oxide layer to is in the range of 2 to 50 nm Dr Fan 7 eee43437nole1 Gale elemode L um Induced nrlypt mm 190 channel pLype su bslrale Dcplelmn region 0 NMOS transistor with a positive voltage applied to the gate G 0 psubstrate for NMOS depletion region is thin 0 B Bulk S Source and D Drain grounded 0 n channel is induced at the top of the substrate beneath the gate 0 n type MOS 7 called NMOS p type MOS is called Dv Fan 7 eeeAaAainotet up small p rype subslmle B NMOS transistor With VG gt V2 and With a small VDS applied V2 threshold Voltage Device acts as a resistance Whose Value is determined by v55 Channel conductance is proponional to v e Vf and thus in is proportional to VG e V vm Induced channel is also called inversion layer B Fan 7 ccwcuulcl in 111A 04 7 as V T 3V 03 7 um v Liv 02 1m V lV quot 05 V 7m s v l l 50 IOO I50 00 rpm Lm V The iDivDS characteristics of the MOSFET when the voltage applied between drain and source vDSY is kept small The device operates as a linear resistor whose value is controlled by VGSi VG 7 Vt excess gate voltage effective voltage or overdrive voltage Dr Fan 7 eeeASASJotel quot65 I 1m rlfH y G when I D J 17 n39 nchnnne ptype substrate Operation of the enhancement NMOS transistor as vm is increased Induced channel acquires a tapered shape resistance increases as VDS increases Va is kept constant at a Value gt V Pinchroff on channel 7 Tunneling effort Dv Fan 2mmth Tnodc gtI Wm lt 7394 V T m Sulumliun gt i I39m y un c hcmk bvmnw Cum m MHIICHAIN hr 39 rh channel lunchcd Hll l lhe drum end on quotKnMm mm pm A p um mum antih the mound Alnnm d llulghl hm im shlpe pmpnnmlml in him 11 Hum n Vy Wns Enhancementrtype NMOS transistor operated with v55 gt threshold voltage The voltage at saturation VSDSEJ V55 7 V Triode Region Active region B Fan eeeABABJotet Source Chml Ilcl Increasing VD causes the channelto acquire a tapered shape Eventually as VD reaches me vs the channel is pinched off at the dmin end Increasing VD above v5 7 4 has little effect theoretically no effect on the channel s shape m Fan VEEMSOGJMN Hide 1mm m mm 139 u m mm 1 m n K n m LLH m Voltage 1 9mm 3quot U Derivation of the ifva characteristic of the NMOS transistor Some formulations based on 013 mm in year 2003 k n process transconductance parameter Dv Fan eeeABABJotet prtypu body 0 Crosssection of a CMOS integrated circuit 0 PMOS transistor is formed in a separate ntype region known as n well 0 ntype body is used and the n device is formed in ap well 0 SiOz for isolation Dv Fan 7 eeeAaAainotet 12 0 mA a v r e I I was 5 um rim region 10 2 was V lt lt Salumlion region 1155 v 20 IK vus as i 4 11m v 15 v m V 05 um V lt v tuition in An nchannel enhancementtype MOSFET with v65 and VDS applied and with the normal directions of current ow indicated 03 0 Dr Fan 7 eeeASASJotet The iDivDS characteristics for a deVi ce with k n WL 10 W Triode Saturation and Cutoff vss 7 V lt 0 regions i mA 1m 3 Um V 1mm ipivGS characteristic for an enhancementtype NMOS transistor in saturation Vt 1 V k n WL 10 mAVZ Vt threshald valtage Dv Fan 7 eeeAaAainotet Largersignal equivalentrcircuit model of an mhannel MOSFET operating in the saturation region Acting like a current source because of saturation Dv Fan reqe winmm 15 Voltage L ldl HL mimgu siiiummii L i G i i i D Threshold 7 Illudi s transistor for operation 7 in the triode region active region r in me saturation region in Fan eggm winmm nllnl 39IIulIlIL I Elm m r mun Channel Pinchoff Increasing VD beyond vmmcauses 1116 Channel pinchroff point to move slightly away from the r in reducing 1116 effective channel length m Fan negm el lt7 W 7 v 7 20v gt rm 7 v i av I I um 7 v 710v m r v 7 05 v 7m 7 71 Effect of VDS on in in the saturation region MOSFET parameter VA depends on the process technology and for agiven process lamda is proponional to the channel length L lamda 7 related to channel length modulation ideal Value 0 D1 Fan 7 eeaBABJotet I T u a G 0 0 0 D 1 us W a 9 4ch 7 Vrr Largersignal equivalent circuit model of the nachannel MOSFET NMOS in saturation Incorporating the output resistance r0 acting as a load The output resistance models the linear dependence of iD on rm Dv Fan someway S o PMOSDevlce GHEM CH A o D m b 1 Uquot D d1 CY a Circuit symbol for the pchannel enhancementtype MOSFETl PMOS b Modified symbol with an arrowhead on the source leadl c Simplified circuit symbol source is connected to the body d The MOSFET with voltages applied and the directions of current ow indicated Dr Fan 7 eee43437n0te1 20 Voltage A 9 l l Tmeshold TriuLvdm um ulwn l l l I crdn u whilst The relative levels of the terminal Voltages of the enhancementtype PMOS transistor for operation in the triode region in the saturation region B Fan eeemuom 21 Summary of MOSFET Current Voltage iv Characteristics 7 m Go o G HI H j 0 v l V u M EACH v Thus S 1 o B c o l I W 3 WCquot I quotso W 0 24 m D Go a gt a or NM 0S and PM OS in conditions for triode and saturation regions Dv Fan 7 eeeASAS no et Dr Miamiicpu lic reward university EEE 4343 Introduction to Digital Electronics Department of Electrical and Computer Engineering Florida International University Instructor Dr Jeffrey Fan Fan 7 eee4343note3 MOSFET Internal Capacitances and Frequency Models V 39 Vin gm Vm i Cm Cm a High frequency equivalent circuit model for the MOSFET b The equivalent circuit for the case in which the source is connected to the substrate body c The equivalent circuit model of b with C db neglected to simplify analysis Dr Fan 7 eee43437note3 MOSFET Unity Gain Frequency fT C m I ll I II I Vw T CW ngv r0 i Unity gain ftequency defined as the frequency at which the sham circuit cunent gain of the common source con guration become unity m m 7 Mmme M OSFETH igh Frequency Model in the model beau c m 39 m Fan 7 cmenoM Pub Three Frequency Bands in vgt39lt Mnux m gtlt Hl ll ruqmm Iuml I Mmpwm l hand E All leucimutm can m nugluuud mmquot mle mm mm nu Juu m um mm due 1H am man vl L Judi n quotM l I l I In lng 4 um I l l l r39 1 1L sz a Capacitively coupled common source amplifier b A sketch of the frequency response of the amplifier in a delineating the three frequency bands of interest Dr Fan 7 eee4343inom3 High Frequency Response Rm Rte 1 1 lt 3 VAVA lt II II 393 at lt V m 1 n quotw i N R Rh Cw M h Determining the high frequency response of the CS ampli er 3 equivalent Circuit b the Circuit of a simpli ed at the input and the output Dr Fan 7 eee4343nole3 r Aquot w R Illw 20 Illsdecade 201mm f f Ill log scale d c the equivalent circuit With ng replaced at the input side With equivalent capacitance CM 1 frequency response plot a low pass single time constant circuit Dr Fan 7W3437note3 Low Frequency Response V rug Analysis of the CS ampli er to determine its lowrfrequency transfer function For simplicity r0 is neglected m m 7 Mmme 40 d Bdccnde 60 xiiidecade 2U dBdccudc amenAux 1112 log scale Sketch of the lowfrequency magnitude response of a CS ampli er for which the three break frequencies are suf ciently separated for their effects to appear distinct u Fan 7 cwmmm CMOS Digital logic Inverter quot1m The CMOS inverter 7 more details in Digital CMOS Logic Circuits later m Wigwam u 1m cm Hm Hm oad curvc in 0 Operating aim u 1m u hm 1390 l g quotDSN c Operation of the CMOS inverter when V is high a circuit with V VDD logicl level or VOH b graphical construction to determine the operating point 0 equivalent circuit Dr Fan 7 m43437n0te3 Load curve Wart Vun VDD A I l39nsr ll 11 Von Vat 0 N Operation of the CMOS inverter when v1 is low a circuit with v1 O V logicO level or VOL b graphical construction to detennine the operating point c equivalent circuit u Fan gamma quot0 Va Vun QN off A Qx m amumnun 9 in riodc mg quot39Im 2 on Slope 7 B E Q and Q quotI smurarmn Q in summnnn M 2 VI Vm QN m Irindc rcgimu l ID a 2 l The voltage transfer characteristic of the CMOS inverter Dr Fan 7 m43437n0te3 pr ralmg puinl 4 r 7quot Operulmg pmm M A r 0 gt 39rm Dynamic operation of a capacitively loaded CMOS inverter a circuit b input and output waveforms c trajectory of the operating point as the input goes high and C discharges through QN d equivalent circuit during the capacitor discharge Dr Fan 7 eee43437note3 15 Current F low and Power Dissipation 0 I Vim Vm 7 Um 1M The curmnt in the CMOS invener versus the input Voltage 1 m 7 Mman m


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