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Vlsi Design

by: Griffin Wiza
Griffin Wiza
GPA 3.59

Sanwei Jeffrey Fan

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Sanwei Jeffrey Fan
Class Notes
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This 35 page Class Notes was uploaded by Griffin Wiza on Monday October 12, 2015. The Class Notes belongs to EEL 6167 at Florida International University taught by Sanwei Jeffrey Fan in Fall. Since its upload, it has received 30 views. For similar materials see /class/221834/eel-6167-florida-international-university in Electrical Engineering at Florida International University.

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Date Created: 10/12/15
Electrical and Computer Engineering FLORIDA INTERNATIONAL UNIVERSITY EEL 616 VLSI Design Devices Adaptedhom Mp bwvo eeos bevke ey eduIoEookshdes Mm Copyngm 2003 Pvermoe HaHFeavson The Diode Crosssection of pnjunction in an IC process A A1 B Onedimensional representatlon dlode symbol Mosty occurring as parasitic element in Digital 03 Depletion Region h s lffusien ectron H 39f39usidlf FWTWTWTWTWTWTW Ii 22 ii 22 22 2215 ii 22 ii 22 ii 22 2 IHHHHH iiiiiiiHHHI inn I gg na miiiHHHHHHHHHHI ll W I39 miiiHHHHHHHHHHI J ampampampamp h h hamp h h h h hole drift 21 2tr221 1 t Chcrge p De1s1 ty x Distancequot L Electncal g Fiel 11 X1 4quot P I V 7 quot V Potent a1 1 139 a V 1 quotA lg W0 Wl WZ 39 a Current ow b Charge density C Electric eld 1 Electrostatic potential Diode Current m 5 m5 E S Q o as mm 2 a stVdenadz current quot3 In In an uz 04 us Um 415 an 05 VD 1V VD V a On a hnEar scale 13 On a uganmmm scawe mywam mas V D T In Isz 71 Forward Bias r p0 nnmnmzz pregion nregion di usion Typicaly avoided in Digital 03 Reverse Bias pregion nregion di usion The Dominant Operation Mode Models for Manual Analysis e1I ID 89 VD T 1 iv quotLquot VD 1quot vi l E ii l a Ideal diode model 1 ID t Iquot L l VD i I VDon l l b Firstorder diode model Junction Capacitance abrupt junction linearjunclion C C 0 m 05 abrupt junction m m 033 linearjunclion 1 a VD m0 Diffusion Capacitance x nregion dQD dID RS rTID 0717 a MD TdVD T Secondary Effects 01 In A O 01 250 150 50 o 50 VD V Avalanche Breakdown 3322 65 SPICE Parameters Parameter Name Symb 01 Units SPICE ame Default Value What is a Transistor A Switch IV 5 Ab lgr 39j L A A A it Iquot 7 l IIIII quotv V l l I l F H39 v v r 439 An MOS Transistor The MOS Transistor MOS Transistors Types and Symbols an an 64E 6de s s PMOS Enhancement NMOS With Bulk Contact n O m m D m 1 t n C p D R n e s 6H c mlquot n a a m 0 a a a m S n v g n b a u a a I all p i Ly l Ir El 7 a g 1 1 n channel Threshold Voltage The Threshold Voltage V q M giss T ms F COX 0X COX A A Implants Wnrkl39unctiun D mm Surface Charge DepletinanyerChzrge BndyE ectCne icient VTOy 72 F WW V at u QSSamp 70 ms F COX COX UK and Egg NA 7 The Body Effect CurrentVoltage Relations A good ol transistor 4 x10 V S 25V Resistive Saturation VGS 20 V 3D 3 7 r Quadratic VDS VGs 39 VT Relationship VGS 15 V VGS 10 V 0 05 1 15 2 25 Transistor in Linear VGS VDs A I we H H H H H H H H r L J Awwwwwww il A MOS transistor and its bias conditions Transistor in Saturation Pinchoff Current Voltage Relations LongChannel Device Linear Region VDS gVGs VT W VD ID WIUVGS VTWDS 752 with k C new Process Transconductance n n 0 2 Parameter 0x Saturation Mode V95 2 VGs VT Channel Length Modulation 1a quotVV 2 ID 2 LWGS VT HWDS A model for manual analysis VDS gt VGS VT Ian 7 2 ID 7 2 VGSrVT 1 XVDS Gn n D ID VDSlt VGS VT 3 W VDS2 39539 I k39nfVGs T 1 D VDS 2 VV L with VT VTOy 72 F VSB r HM CurrentVoltage Relations The DeepSubmicron Era 25 4 X 10 l VGs 25 V Early Saturation VGs 20 V VGs 15 V gt VGs 10 V 05 15 2 25 Linear Relationship Velocity Saturation A 1 ms Usat Constant velocity Constant mobility slope p Perspective ID A Longchannel device VGS VDD ShortChannel device ID versus VGS quadratic o 05 1 15 2 25 VGsW Long Channel 4 2 1o 2 157 1 057 quadratic C 1 1 1 o 05 1 15 2 25 VGsV Short Channel ID versus VDS 4 4 OX 10 J 25X 10 y j VG V 5 2 Resistiv Saturatio n 4 VGs 20 V VGs 20 V A15 7 2 s 03 D VDs VGs VT 1 VGS 15V 2 VGS 15 V 7 17 7 05 VGS y VGs 10 V 0o 05 1 15 2 25 U0 05 1 15 2 25 VDSV VDsV Long Channel Short Channel A unified model for manual analysis ID 0 for VGTSO W ID kZVGTVmin 2 for VGTZ 0 with me minVGT VDS VDSAT VGT VGS VT and VT VTO YA 2 F VSB A 2 F Simple Model versus SPICE X 10 25 VDSVDSAT 2 W 0 Velocity Saturated 7 1 O M 2 0 0 D Llne 1 VDSATVGT 05 GT Saturated O 0 05 1 1 5 2 25 vDs v 39 A PMOS Transistor x10 4 VGS 10V 02 VGS 15V o4r VGS 20V Assume all varlables O6 negative 08 VGS 25V 2 5 2 15 1 o 5 o Transistor Model for Manual Analysis Table 32 Parameters for manual model of generic 025 pm CMOS process minimum length device Vzn V v w Vow V k39 AN A V1 NMOS 043 04 063 115 x10 006 PMOS 704 04 1 30 x 10396 01 The Transistor as a Switch V68 2 VT sJS Ww R ID A VGS V00 7 r Rmid R I I VDS VDDZ VDD 1 VDD VDD2 R52 VDD 7 I IDSAT1VDDIDSA71VDD2 41ml1 6WD 3 The Transistor as a Switch The Transistor as a Switch a le 33 Equivalent resistance Rea WL 1 of NMOS and PMOS transistors in 025 pm CMOS process with L me For larger devices divide Rea by L Vol V 1 15 2 25 NMOS kg 35 19 15 13 PMOS kg 115 55 3s 31


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