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week 10

by: Abhinav Notetaker

week 10

Abhinav Notetaker
GPA 3.5

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week 10
Intro to VLSI design
Class Notes
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This 35 page Class Notes was uploaded by Abhinav Notetaker on Monday March 21, 2016. The Class Notes belongs to at University of Cincinnati taught by in Spring 2016. Since its upload, it has received 4 views.


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Date Created: 03/21/16
Wires The Wire transmitters receivers schematics physical 2 InterconnectImpact on Chip 3 Wire Models All-inclusive model Capacitance-only 4 Impact of Interconnect Parasitics • Interconnect parasitics – reduce reliability – affect performance and power consumption • Classes of parasitics – Capacitive – Resistive – Inductive 5 Nature of Interconnect Local Interconnect Pentium Pro (R) Pentium(R) II Pentium (MMX) Pentium (R) Pentium (R) II Global Interconnect S Global = S Die S Local = S Technology No(Log Scale) Source:Intel 10 100 1,000 10,000 100,000 Length (u) 6 INTERCONNECT 7 Capacitance of Wire Interconnect VDD VDD M2 Cdb2 Cg4 M4 Cgd12 Vin Vout Vout2 Cdb1 Cw Cg3 M3 M1 Interconnect Fanout Vin V Simplified out CL Model 8 Capacitance: The Parallel Plate Model Current flow L W Electrical-field lines H tdi Dielectric Substrate ▯ di S 1 c int▯ WL SCwire ▯ tdi S ▯SL S L 9 Permittivity 10 Fringing Capacitance (a) H W - H/2 + (b) 11 Fringing versus Parallel Plate (from [Bakoglu89]) 12 Interwire Capacitance fringing parallel 13 Impact of Interwire Capacitance (from [Bakoglu89]) 14 Wiring Capacitances (0.25 mm CMOS) 15 Inter-wire Capacitance 16 CapacitiveCross Talk (Floatingor Dynamic Node) X C XY VX Y C Y Capacitive Cross T alk Dynamic Node V DD CLK C XY Y CY In1 X In2 PDN In3 2.5 V 0 V CLK 3 x 1 mm overlap: 0.19 V disturbance (about 8-10%) Dealing with Capacitive Cross T alk • Avoid floating nodes • Protect sensitive nodes (separate them from full-swing nodes) • Make rise and fall times as large as possible (adversely effects short-circuit power and performance) • Differential signaling (Cross-talk appears as common-mode noise) • Do not run wires together for a long distance • Use shielding wires (GND or Vdd which don’t swing) • Use shielding layers (GND or Vdd layers) Shielding Shielding wire GND Shielding V DD layer GND Substrate ( GND ) Cross Talk and Performance - When neighboring lines switch in opposite direction of victim line, delay increases DELAY DEPENDENT UPON ACTIVITY IN NEIGHBORINGWIRES C c MillerEffect - Both terminals of capacitor are switched in opposite directions (0 ▯ V , V ▯ 0) dd dd - Effective voltage is doubled and additional charge is needed (from Q=CV) Impact of Cross T alk on Delay r is ratio between coupling cap to intrinsic cap of the wire. INTERCONNECT 24 Wire Resistance R = ▯ L H W L Sheet Resistance H Ro R R W 1 2 25 Interconnect Resistance 26 Dealing with Resistance • Selective Technology Scaling • Use Better Interconnect Materials – e.g. copper, silicides (silicon based compound materials) • More Interconnect Layers – reduce average wire-length 27 Polycide Gate MOSFET Silicide PolySilicon SiO 2 n + n+ p Silicides: WSi2,TiSi 2 PtSi2and TaSi Conductivity: 8-10 times better than Poly 28 Sheet Resistance 29 Modern Interconnect 30 Example: Intel 0.25 micron Process 5 metal layers Ti/Al - Cu/Ti/TiN Polysilicon dielectric 31 Impact of Resistance • We have already learned how to drive RC interconnect • Impact of resistance is commonly seen in power supply distribution: – IR drop – Voltage variations • Powersupply is distributed to minimize the IR drop and the change in current due to switching of gates RI Introduced Noise VDD I Phi pre R’ VDD - DV’- X I DVl M 1 Del-V R Power and Ground Distribution V DD GND Logic Logic VDD VDD GND GND (a) Finger-shaped network(b) Network with multiple supply pins Electromigration (1): Transport of Metal Ions Limits dc-current to 1 mA/ m m Electromigration (2)


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