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# INTRODUCTION TO ELECTRONICS EE 329

ISU

GPA 3.81

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This 183 page Class Notes was uploaded by Amara Morar on Monday October 12, 2015. The Class Notes belongs to EE 329 at Idaho State University taught by Staff in Fall. Since its upload, it has received 55 views. For similar materials see /class/222196/ee-329-idaho-state-university in Electrical Engineering at Idaho State University.

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Date Created: 10/12/15

Chapter 2 Diode Circuits In the last chapter we discussed some of the properties of semiconductor materials and introduced the diode We presented the ideal current voltage relationship and considered the piecewise linear model which simpli es the de analysis of diode circuits In this chapter the techniques and concepts developed in Chapter 1 are used to analyze and design electronic circuits containing diodes Diode circuits to be considered perform functions such as recti cation clipping and clamping These functions are possible only because of the nonlinear properties of the pn junction diode The conversion of an ac voltage to a dc voltage such as for a dc power supply is called rectification Clipper diode circuits clip portions of a signal that are above or below some reference level Clamper circuits shift the entire signal by some dc value Zener diodes which operate in the reversebias breakdown region have the advantage that the voltage across the diode in this region is nearly constant over a wide range of currents Such diodes are used in voltage reference or voltage regulator circuits Finally we look at the circuits of two special diodes the lightemitting diode LED and the photodiode An LED circuit is used in visual displays such as the sevensegment numerical display The photodiode circuit is used to detect the presence or absence of light and convert this information into an electrical signal Although diodes are useful electronic devices we will begin to see the limitations of these devices and the desirability of having some type of quotamplifyingquot device 21 RECTIFIER CIRCUITS One important application of diodes is in the design of recti er circuits A diode rectifier forms the rst stage ofa dc power supply as shown in Figure 21 below BB 329 Introduction to Electronics 72 0W6 l39 lrunsforme 139 F 1 AC gt Diode F Vallwe Iller E lt rohzi ge rectifier regulator lt3 LOAD 1quot wune lt lt n Figure 21 Block diagram of an electronic power supply As we will see throughout the text a dc power supply is required to bias all electronic circuits The dc output voltage vo will usually be in the range of 3 to 24V depending on the application Recti cation is the process of converting an ac voltage to one polarity The diode is useful for this function because of its nonlinear characteristics that is current exists for one voltage polarity but is essentially zero for the opposite polarity Rectification is classi ed as halfwave or fullwave with halfwave being the simplest 211 Half Wave Recti cation Figure 22a shows a power transformer with a diode and resistor connected to the secondary of the transformer A I N1 Ni 0 39 V l l I 1 g R to a We will use the piecewise linear approach in analyzing this circuit assuming the diode forward resistance is rf 0 when the diode is quoton The input signale is often a 120Vrms 60 HZ ac signal Recall that the secondary voltage v5 and primary voltage VI of an ideal transformer are related by BB 329 Introduction to Electronics 73 w respemvely whats N transfurmer Cums mun eenaueung Dr nut m whmh me dmde s upa ahng by 1 ms cundmun than cund tmn the urder quhese twu s NOT lmpunant Fxgure z 20 shuws Lhevultage transfa39 characteristics vs versus vs futhe emu slope L When v lt H zem As lung 25v lt vv me meae Wm benunrcundumng se me uulputvultage mueemsm zem When v gt VV the dmde beenmes farmed based and a current is mdueed m the urcuxt In Lhs case we can wme a 29 macaw memms Fm gt vv the slaps quhetxansfercurvexsl 1m 5 a smusmdal 53121 as shuwn m Fxgure 2 32 395 W 1 When v gt Vvthe uulputvultagexszem 2 When v 5 VV the uulput v 7 VV and 5 Shawn m the gure beluw b M 39 v Smce the ma a enuremput 3131 vultage appears armssthe dmde as shuwn beluw a 29 xmqmm Etch1m 75 r u nuPnH sustaining alarge peak mvase vultzge pm wnhuut breakduwn A L The emem xs zem m nh m m Wearenutmakmg use uf any pussxble avalable energy 212 FulLWzve Rec cztinn a u gure 2 62 ms EIHz a sxgnal W vultzges v5 v are 215 pusmve a 29 xmqme mcmms 76 eleemeal shuek dmde D1 and the dmdes rs reversed Ifwe assumethat the furwzrd dwderesxstancen ufeaeh druders neghgrble we ubtam thevultzgetxansfercharadmsucs ya versus vs shuwnm Frgure z 50 51011 Frgure z 6a errem rs called a full wave reeu er a 29 Imam mcmms 77 AnuLhEr example uf a fullrwzve reehser erreurt appears m gure 2 72 a r M r utmt are reverse hrssea cycle quhe mputvultage v rs neganv s an 1 are furwzrd based The dueth quhe eurrerrt shuwn m Frgure z 70 pruduces the same eutput vultage pulmty as befu Frgure z 7a shuws the smusmdal vultage v and the reeheea eutput vultage vs less than themsgrhtuae ufv a 29 xmhme Etch1m 213 Films Rippleanng and made Current Fxgure capsular assuming the capsular s mmally uncharged cu decrease mum umeF1gure 2 82 Dunng ths nmepenud the dwdexs muff subtle mfferencebetween actual mun upman and the quamanve descnptmn Ifwe assume Lhatthe mpquot m mm M h Wu w M Mr whmh means that animal the vultage acruss the made 5 yeata39 than vV Huwsver Lhs cuman m r unlya a 29 xmqmm Etch1m peak value and the capacxturvultagexs cumpletelyrechzrged The steadyr ate uulputvultzge ufthe RC Shams shuwnm Fxgure 2 83 9 m gure 2 9 Figure 25 ompm vanage of a mlrwave recti er wnh an no Inter m mum The amman mum s un p 58 ufyuurtext Ifwe can assumethatthe npple effectxs mall we getthe fulluwmg zppmmmahun a 29 xmqmm Etch1m Tr I r Ll where TP 15 me me betwem peak values ufthe uulput vultage Fur afullrwzverecu erTP 15 unerhalfthe 53121 penea Therefure we canrelate TP m the we equency V 3 1 in in mm 7 b 1 Figure 210 Output ml 3 tuuewave reenter win an RC inter qur u h the equivalent emu ufthe lllrwave recti er aunng the chargng ume a 29 macaw Etchinns a k AAAA Figure 211 Equivalent circuit of a fullwave recti er during capacitor charging ycie We see that l u m gt 7 rquot A MR H 214 anmge mums Circuit mm gure 2 13 Figure 213 A voltage doubler circull a 29 xmqmm Etch1mm Figure 214ashuws the equivalent euem when he vultzge pulmty at the map ufthe txansfurmens quot u mm L m czpa turC peak value ufv 39umxts peak value c discharges mange R and c2 We assume that Lheume cunstant RLC xs vary lung cumparedtu Lhepmud quhe input 5 3an A w v e L C 0 RL yo 7 l c H b Figure 214 y mun a 1n positive mpm cycle m oc L V M essenueuy becames vM By erchhuffsvultage law Lhepeak vultage mes RL 15 nuW essenuelly equal 39 butlfcx A Vxsqutesmall 22 ZENER DIODE CIRCUITS In Chapta39 1 reference emu In Lhs chapter we Wm luuk at amdeal vultage reference nrcuxL zndthe effects uf mcludmg a nemaeel Zaner resistance xix33 hmmmnnmEkcms One reasun is that 221 mm anmge Reference Circuit Fur Lhs cmmlL cunstanL vanes aver aspem range Figure 215 A Zener diode vouage reguramr mun dmde and drugs the Excessvultzgebetwem vFs and vZ whats 1L V RL and the vanables are the mputvultage suurce Vys and the luad emem 1L dissipanun m the dmde must nut exeeed xts rated value In Ether Wurds a 29 xmqme mcmms a 1 quotquot 39 39 39 quot Ifmim Ifmaiand the source voltage is a minimum Vps min Ifma quot 39 quot Ifminiand 2 the source voltage is a maximum Vps max Inserting these two speci cations into the previous equation we obtain 7 Imlmimr l7 lzllmln mum l rm 7 l 7 17mm mnuu Equating these two expressions we then obtain ll Ivmmnr I7 17i I mums I7 l7t II39mranl ll IIMHHJH ll Reasonably we can i u a and the Zener voltage The previous equation then contains two unknowns 1min and lmax Further asa IIEI ener current or Izmin01 Izmax We can then solve for Izmax using the previous equation as follows I Univ l Ili r I uniul I mum 7 17mm 1mm l minim Imlmlln we can diode Th In one of the previous equations 222 Zener Resistance and Percent Regulation In the ideal Zener diode the Zener resistance is zero In actual Zener diodes however this is not the case The result is that the output voltage is a function ofthe Zener diode cunent or the load cunent Figure E 329 intrudurtiuntuizlertmnics z 17 shuws the edmvdem emu ufthe vultzge regulatur Figure 217 A Zener dmde vullage regulator mun with a nonzero Zener resxslance patentregulatmn andls de ned as m x w w krgddmu 1 w immune where mum 15 me mmd dame quhe uulputvultage 23 CLIPPER AND CLAWER CIRCUITS In Lhs 53an we edndnue Bur ddscussmn ufnunrlmearmrcult eppheaddns ufdmdes Dmdes canbeused up um V meme are called clippers and dampers respeemely 231 clippers cupped cxrcuxts amnV zem are ehmmated A ample eppheazmn ufa Ehppa ls m hmxtthevultage atthemputtu an electxumc sequeney quhe 513121 5 me emphmde lsnut anxmpunzntpan quhe 513121 Fxgure z 18 shuwsthe general vultagetrznsfer nhamctensncs ufahmxter emu a 29 xMeme Etchinns as Figure 213 General vallage transfer characteristics at a hmiter circull The hrmer rs almear Circuit fohe mpm 5 3an rs m the range uf V5 59237 Av Av where A sthe slupe quhe transfer curve IfAv 1 as m dwde urcmts me erremrs apassxvehmxter gure 2 18 shuws are general transfer curve F 1 HM hm Pr and V5 arepussxble h m m rerre may be pushve whde me uLhEr neganve as mangled m me gure Frgure 2 192 rs a smglerdmde elrpper errem a 29 Imam Etchinns m a b Figure 219 Stng erdtode cttppet ta circuit and tn output response The dmde mu uffaslung as v lt v3 vV thh D uf the eunehttszem the vultzge amp acmss Rts zem and the uulputvultage fulluwsthemputvultzge when v gt v3 vv the dmdetums eh the eutput vultzgexs ehppea and VB vg vV The eutputstghat ls shuwnm thure 2 190 Other ehppthg eueutts eeh he euhstxuetea hy rsva39smg the dude the pulmty quhe vultage suuhee eh huth gures 2 ZEI2 m a 29 macaw anthems mun Fugure 22a h 1 mn r gure duemns a 29 xmqmm Etch1m A para elebased diode cuppercimun and us output response Figure 221 232 Clampr In sLeady gate wavefurm z 250 b the vuusge arms the espsem fulluws me mpu and vK v assummg that n and vV u A er v and vK reachthexrpeak values vxbegms m decrease and me made bemmes reverse mssea Ideally the capantur VM y m a 29 Imam mcmms v0 rvcv VMsinatrl The capa tur and uulputvultages are shuwnm gures 2 25 and a c d The uulputvultzgexs clamped atzem veus mans vs 5 n In steady state he vaveshapes quhe mpm signal Inths w vm L L uulput Ifwe assume fur simplicity Lhatr and vv u Lhanthe uutputls clamped awe gure 2 260 Figure 225 a 29 xmqme memms When the polarity of VB is as shown the output is shifted in a negative voltage direction Similarly Figure 226c shows a squarewave input signal and the resulting output voltage signal For the square wave signal we neglect the diode capacitance effects and assume the voltage can change instantaneously C 24 lVIULTIPLE DIODE CIRCUITS Since a diode is a nonlinear device part of the analysis of a diode circuit involves determining whether the diode is quotonquot or quotoffquot If a circuit contains more than one diode the analysis is complicated by the various possible combinations of quotonquot and off In this section we will look at several multiplediode circuits We will see for example how diode circuits can be used to perform logic functions This section serves as an introduction to digital logic circuits that will be considered in detail in Chapters 16 and 17 241 Example Diode Circuits To review brie y consider two singlediode circuits Figure 230a shows a diode in series with a resistor A plot of voltage transfer characteristics v0 versus v1 shows the piecewise linear nature of this circuit Figure 230b BB 329 Introduction to Electronics 92 AAAA a Figure 230 Diode and resistor in series a circuit and b voltage transfer The diode does not begin to conduct until v1 Vv Consequently for v1 lt Vv the output voltage is zero for v1 gt Vv the output voltage is vo v1 Vv Figure 23 1a shows a similar diode circuit but with the input voltage source explicitly included to show that there is a path for the diode current The voltage transfer characteristic is shown in Figure 23 1b 117 V5 V5 R D 7 V0 1 JD 391 l quot5quot v7 5 quotI a b Figure 231 Diode with input voltage source a circuit and b voltage transfer characteristics BB 329 Introduction to Electronics 93 In this circuit the diode remains conducting for v1 lt Vs V7 and the output voltage is v0 v1 Vy When v1 gt Vs Vy the diode turns off and the current through the resistor is zero therefore the output remains constant at V5 In multidiode circuits each diode may be either quotonquot or quotoffquot Consider the twodiode circuit in Figure 232 Since each diode may be either on or off the circuit has four possible states However some of these states may not be feasible because of diode directions and voltage polarities Figure 232 A twodiode circuit Ifwe assume that V gt V39 and that V V39 gt V there is a possibility that D2 can be turned on Figure 233 shows the resulting plot ofvo versus v1 BB 329 Introduction to Electronics V Y Figure 233 Voltage transfer characteristics for the twodiode circuit in Figure 232 Three distinct regions are shown corresponding to the various conducting states of D1 and D2 The fourth possible state corresponding to both diodes being off is not feasible in this circuit Problem Solving Technique Multiple Diode Circuits Analyzing multidiode circuits requires determining if the individual devices are quotonquot or quotoffquot In many cases the choice is not obvious so we must initially guess the state of each device then analyze the circuit to determine if we have a solution consistent with our initial guess To do this we can 1 Assume the state of a diode Ifa diode is assumed quotonquot the voltage across the diode is assumed to be Vy If a diode is assumed to be offquot the current through the diode is assumed to be zero 2 Analyze the quotlinearquot circuit with the assumed diode states 3 Evaluate the resulting state of each diode If the initial assumption were that a diode is quotoffquot and the analysis shows that ID 0 and VD S Vy then the assumption is correct If however the analysis actually shows that either of these is incorrect then the initial assumption is incorrect We can also do the same thing if our initial assumption is that the diode was on 4 If any initial assumption is proven incorrect then a new assumption must be made and the new quotlinearquot circuit must be analyzed Step 3 must then be repeated BB 329 Introduction to Electronics 95 242 Dim le Lngjc Circuits u h ND and OR butwe vmn t mm ths excepttu shuw the nrcuxt magams In Figure 237 A wmnpm diode on logic mun 1 Figure 232 A Iwm npul diode AND mg circuit a 29 xmqmm Etch1m 25 FHOTODIODE AND LED CIRCUITS mmme an 212mm currentmm an uphcal 3131 251 thtndinde Circuit nur mally vary small Phutuns smkmg the dmde create Excess elemmns and hules m the spacercharge regun charge regmn treatmg a phutucun39ent m the exenemas duemun hv a Ih gt r R V0 Figure 239 A photodiode Circuii 252 LED Circuit m uns phum mm a uent band gap material such as GaAs Whmhxs 2 3291mm 3 signal LED pmnomcdc c a Figure 242 Opmisolalur usth an LED and a pholodiude 25 SUMMARY accurate results when actual dmdepmpemes ac knuer signal Ad qua supplywh1nhxsusedtu mas electxum cucms and systems uhhzethese types uf mcms effect Ether cuccm paramch circuits vultzge and luad resxstance values and ufthe mdmdual dam cc parameters applicatmns were mscussca The techniquereqmresmakmg assumphuns as c whcmcc admdexs must gm back and vanfy that mc assumpnuns made were wand a 29 xmqmm Etchinns 9a such applications as the sevensegment alphanumeric display Conversely the photodiode detects an incident light signal and transforms it into an electrical current Examples of these types of circuits were analyzed END Ch 2 BB 329 Introduction to Electronics PmblzmrSnlving Technique MOSFET Dc Analysis MOSFET saturatton of the tranststor In some cases the btas eondttton may not be obvtous whlch means that we our tntttal guess To do thts we can Assume that the tranststor ts btased tn the saturatton regton tn Whlch ease VG gt V11D gt o and Vb Z Vb sat 2 Analyze the etreutt uslng the saturatton eurrentvoltage relattons 3 p l are aha lva lt v ts probably cutoff and lf VD lt vDE sat the tranststor ts llkely blased tn the nonrsaturatlon reglon 4 reanalyzed step 3 must then be repeated 523 Cummnn MOSFET Cunl39igum nns DC Analysis Several examples are dlscussed tn thts seetton VDD5V 75 V Figure 529 NMOS CommonSource Circuit wilh source reslslor EE 2 Immduc nn tn Elzclmmcs Design Example 56 Objective Design the dc bias of a MOSFET circuit to produce a speci ed drain ctiircnt 0139 the dc circuit in Figure 529 assume the MOSFET parameters arc VT i i It SOpAVZ nd W 4 Choose R and R such that the ciiiicnt iii the bias resistors is approximame olloetemh of 10 Design tlic circuit such that ID 05mA lti the nal design standard rcsistoi valuos arc to ho tisc Solution Assuming the transistor is biased in the saturation region we have W 7 lo 39fUos Vm mi 05 14 was 7 2 which yields 7 377v Tho current through tho bl tls icsisiors sliotild bc approxniiatcly 005 111A so that ID a R Rz 7 005 7 mom We can write R7 Vbquot VS R 377 200110 7 052 V 390 i 5 llpRs 5 so that We nd that R2 954th and R 1046 m The closest si dndard resistor values are Ra 00 k9 and R 0th Comment sinco V I 4v then VDS gt vmtsat VHS 39T 3777 2 L77 v Tlioteforo tho transistor 1 bitisod in tho gt tiiul39tiiiun IL giUu as initially asstiinod Desiun Pointer We must keep in mind that there are certain tolerances in resistor va not as weli as tolerances in transistor conduction parameter and threshold voltage vanes These tolerances 12 d to variations in the Q7point values One implication or this v tioti is that we should not design the onint too close to t in transition po ml or thc parancicr variations may push the Qrpmul into the nonsatiiiation region This is no situation in which a computer simulation may cut down the number or tcdious calculations EEzzalritxadicamtsEicctxmcs m Inblpolar clrculls a run n In the clrcull In a Slrmlar way one devlce Lo anoLherbecause offabncatlon lolerances In channel lenglh channel wldLh oxlde lhlclmess or camer moblllty reslslor Furlher ln many MOSFET clrculls today the source reslslor ls replaced by a constantrcun ent source ym mu m Lhereby slabllmng Lhe Qrpolnt 5v Figure 530 a NMOS commonSource circun biased wilh a Consxamrcurrem source and b equivalent dc circuit Deslgn Example 57 Objective Design a MOSFET ellcult bluscd Rh 3 Collsl nlrcul39l39cm source The pmmncrols of lhc nunslsmr in lh cncnl shown in Figure 5300 Are V SOpAVZ and WL 3 cslgn rho oircull such tlmt lhe qulcsccm values d V9 5 v are D Solution The dc cql is shown m Figure 53mm slnoc u or me gmo ls uv l at ground potentlnl and hCI39C ls no gale culrcnl lluough R5 EE 2 Immducunn m Ehcnnnus 252 39ed m the sun alien L39eglml we have Assummg he u39anslstol39 ls blu A T W s In TWGVVH 250 vowis a 08 which yields VGS 274V The volmgc at the source terminal is VS The drum C lh39rt cam HD h VK39HK H A it D DRL Fol V 25 V as hm 474 39 211708l44 s In ammo IS 4 7w s I Dghu V VA n on region LS minullv assumed m L D b ASEd m use em smuccs much Nastd by llslng cmhmn Comment MOSFET cmnl IS m mm am ilgnrd h Imng mlm Mos mm m m m u h used as a nmllnearresxstor Atransxstorwlth ths connection ls called an enhancementload devlee Since the txansxstons an enhancementmode demos Vm gt 0 Also forthls lrcult V95 ch5 gtVpssat V55 7V whlch means Lhanhe txansxstons always blasedm the saturation region The ganeral lav charactensucs for such a devlce can then be Wntten MUM VT In IMAMx W a 29 Manama Elacmmms Figure532 Enhancement mode NMOS device with me gale connemed 11 the chain gure 5 33 shuws ap1ucuf13quauuns19fmme casewhen K 1 mAv and V 1 V 10 111A Vmsan 1 55 Tituniglur lhmntlexisric 3 4 5 103m Figure 533 CurrenHrnnage nhamm min of an enharnemem had new a 29 Managua mums mple Objective Calculate the characteristics of a Cu Cu containing an enhancement load device onsider the circuit shown in Figure 534 with transistor parameters VT 08 V and 7 0 OSmAVZ Solution Since the transistor is biased in the saturation region the dc drain current is given by In 7 KINcs Vm quot and the dc drain7torsouree voltage is Vos Vus 5 oRs CDlnhl lllg these two equations we obtain V 5 7 KnRSVGS 7 me Substituting parameter values we obtain VGS 7 5 7 0050VS 7 08 which can be written as 05 V53 02V 7 468 7 o The two possible solutions are VGS 7 7327v and V05 7 287V Since we are assuming the transistor is conducting the gaiertossoul39ce voltage nitist be greater than the threshold voltage We therefore have the following solution VHS 7 VDS 7 2x7v and D 7 0213 mA ommenl This particular circuit is obviously not an ampli er However the trains tot connected in this con guration is extremely nset39ul as an effective load resistor EB 29 Inkeduchmtalileckamcs Figure 534 Cireuii Cumaining an enhancement load device 5 35 the emu can be used as an zrnph a39 Dr as an inverta m a digital iegie emu nn Laud Dm ci Figure 535 Clrcull wllh enhancement load device and NMOS drlver a 29 hheducmm Elathuzims Theloadd i M all dth dnver Exam Ie 59 Ob39eclive Determine the dc transistor currents and voltages in a eircuit containing an enhancement load devtce 1e transistors in the circuit shown in Figure 535 have parameters Vrm vs 10 7 tiA 1 and KM 7 IOyAVl The subscript D applles to the driver transistor and the subscript L applies to the load transistor Determine V0 for V 7 and I 7 Solution V 7 5 V Assume that the driver tiaiisistoi MD is biased in the iiotisattiia tion region The drain current in the load device is equal to the drain eurrent in the driver transistor Writing these earrents in generic form we have KinlltVasD VmoWnsn V5 0 Kiierosr I rmJ Since V030 VI VDSD V and Vast VD gm 7 IQ then molari 7 Vmom 7 V5 mm 7 V 7 me Substituting numbers we nd soilzis 7 1W 7 V5 71mm 7 VU 71Z Reaitaiigiiig the terms provides 31717 24V 8 7 0 Using the quadratic fortnulth we obtain two pmsible solutions V0 7 765 v or V0 7 0349v Since the outputvoltage solution is V0 7 349v Alsoi siiioo VV 7 V0 7 o 340 v 7 Vow 7 rm 7 biased in the nonsaturation region as initially assumed The etirioiit can bc acteiiiiiiied tio cannot be greater than the supply voltage VD7 7 SV the valid 7 l 7 wt 1 driver MD is ID 7 Kimass 7 Vain Kiram 7 Va 7 VainZ D 7m5 70349712 7 133 tiA EE 2 Intmduconn m Elzcimntcs cd la the sulul39uliou 5 V Assume that he dL39IVEI39 ruuslslor MD ls 1739 c Cul39L39CmS in the m o tl39anslslors and wrulug the current equations ul Solution V region Equuung h gcnel39lc relm We hate on 1m KllannSD 7 VrNDJZ 7 KIM 7 leZ Again slhee Vm V and Van VDSL V00 7 Va lheh TALJ Know 7 leZ 7 KanDD 7 Substllullng numbers and luklug lhe square real We nd Mu57 Im57 VI 7 I xx v ohleh ylelds V Such QM V0 3 7 VH0 L5 7 MD ls blesed m rho saturation L39BglmL as lultlally assumed The current ls o KnoWaso VTND2 5W 15 i 1 115 uA l 05 V the driver UquotdlStSOl39 Comment For his example we made an Initial guess as to whmhm the driver rall7 slsmr wz bl s lll he szuurull on or nousuluruuon raglan A more unalylicul upproucl As shown following 1115 example Computer Slmulatlon The Voltage transfer charactenstlc ofthe MM OS ler ate Clrcult Wlth the enhancement load shown lh Flgure 5 35 was obtalned by a PSplce analysls These results are shown lh Flgure 5 36 For an lnputvoltage less than 1 v the drlver ls cut off and the outputvoltage ls VDD 7Vm l V and Vo 4 V charglng and dlschal gmg so the outputvoltzge cannot getto the full V99 7 5 v value mall I V l 1 5 V showed regloh and the outputvoltage IS a hohhhear functlon ofthe lnputvoltzge EB 29 Immdnctmn tn Elzctmmcs Vn V 40 20 on 5 0 V V 39 Figure 536 Vunage trans39ler enamctensucs of NMOS inverter with enhancement Dad device we can determine the transition point In the circuit shonn in Figure for the I 39 r transistor that separates the saturation and nonsatnration regions The transition point is determined by the equation I DSDHHU quotum inn 510 Again the drain currents in the two transistors are equal Using the satura tion drain current relationship For the driver transistor we have Inn 1m 52100 0 l KuLiHKL 1quotva 5210 191 er quotTVD Again noting that VUSD and VG I mL I m V0 and taking the square root we have K 3939 I V i I39m quotrm u quot I39r39L VA 522 r I EE 329 Intruducnun m Eleetmmes V and the At the transition point we can de ne the input voltage as V V Then lom Equation 522 1 output voltage as 0 Vpmsat nsition point is the input voltage at the tra VTADU KmK 1 J gt 523 kuDkuL If w apply Equation 523 to the previous example we can show that our y 7 Ln DD initial assumptions were correct Up to this point we have only consideredthe nrchannel enhancementemode MOSFET as a loaol device An nrchannel oleplellommoole MOSFET ean also be useol Considerthe oleplellommoole MOSFET with the gate w Fl ur I ion or nonrsaturatlon regions The aansluon Figure 5 37b The txanslstormay be biased in eitherthe satura L l a l so that ersat ls positive VDD l D LDS e vnslsuo in a b device with nv Figure537 la y 1 Characterisile currertwullage Consider F m 5 may a s a l andVDDandR EE 2 lmmelmomo momes Figure 538 Circu39rl comaining a deple ion load device u lw smacmmucs or cuam mmmnm a Cu Uhlznwz Example 510 dnpm mu Wand Wm M hc mrmm mwn m1 AV39 Altltumc mm I m emd gm lt 1x m mmmmr mnamnm39 mr and R m mvmnml r99 nu man m thnlnn39 vrwp mum rhmmp mmer ummd w m dc min cuu39ent i K T urT m r39 144va mm n w y volwgels 39w L o4u 13v Smw V 3v gt I muan 35 vm n 727 7 N m mnslsmr 15 um n ma smuuhmn legion Commcm Ajhougj m L Tun 39s also mm an amp m ms mms 5m con guunon is us 1 u an 2mm 10m mum m bmh analog and mm c cuim y Buththeluad a 29 Managua Elam a mu valng m the gate cme dnvenmnsxstur up 1 ML quot05 Lmud DI iver Figure 539 Circuit w h deple ion load device and NMOS driver Demmmc the dc u39umlsmr mums and much in Exam I2 5 H mumm cumn mmmumg n dcpmmu 10m dcvmz u W n nu um 1gu 3 mum K MUM L V J V K3 in AAquot and KM MIAv Dewnnm r39 n v39 a 29 Managua Elam Solmion i sumo he driver uausistor MD is blaSCd in dis nonsamrmion region and he oad transistor ML is biased in the saturaiion region The drain currents n he two iianSisiois are equal In genoric form those currems are on m KnDlNVGsD 7 VmDWDso 7 VBSDJ 7 mle 7 me Slum VGSD V VDSD Voi and V5 7 0 than mum 7 Vmo 39a 7 V5 7 16147 me Subsumilng numbersi We nd 501120 7 mm 7 V517i1011717zuf Rearrangng the arms produces 5V5 740V4 0 Using the quadmnc formula we obtain two possible solutions V0 7 790v 0139 V0 010v Since he ouipm mirage cannot be giaam man he supply voltage VDD 5v the valid solution is V0 NV The cumem is In KnLPVmUZ 10114112 40 Commen Since VDSD V0 7 010v lt VGSD 7 VW 5 7 l 4v MD is biased in he nonsamranon region as assumed Similarly since VD V00 7 0 9v gt m 7 7 7 722 ML is biased in dis saiuiauon region as originally assumed EE 2 Immdvconn tn Elzcimmcs VMVJ 50 no 50 WW Figure 540 Voltage ransier Charamerisiics of NMOS inverter wi h depletion load device Computer Simulation 4 A m Figure 5 v e F m An F e an mpm voltage less than 1 V the dnvens cut off andthe outputvoltage is 5 V TV 1 9V both transistors are largerthan 1 9 V Li Figure 5 41 shows an example of a CMOS inverter EE 2 Imamqu m Ekctmmcs Figure 541 Example of CMOS invener Example 512 objective Demrmme the voltage transfer clmractcrlstlc of the CMOS mvcrtcr usmg a PSplCe Mmlysls Far the clrcmt shown ln Flgure 5AA assume trunslstor parameters 0f va 7 d K K Also assume VDD 5v and IQ 325 v lV VT Solution The voltage ruusfct charactcl as are shown in F glue 5 42 In this casc there is a re ion as AS the case for an NMOS inverter VlKh dcplctlou load in Vhlch both translstors are blnscd in the saturation l39BglOll and the lnput voltage is a constant over this transition region for the assumptlon that the channel length modulation 939 amctgtr A is zero V0 V 50 0 5 l V V Figule 512 Voltage lmrsfel characten sucs of CMOS invene in Flyule 541 E 329 Intmducnunlu Elenmmcs 27s 51A CmmnvCunmt Smlrce Basing Mn FFT rw VrM A 1 M A type cun guranun mure dated next semester Figure 543 lmplemema ion of a MOSFET cons anrcurmm source Desxgn Consmexauon 5111 m Ins Cwlnpla M3 and M armdcnucal lrLnsamrx me n 1 equiv By mdmgmng he xldxhrmrlcngxh was We sun39an 10 FM 2 nd 13 Lmznm ldcnucaL mm 9 and IRE mu not h eun A mxiety of daslgn opnom 0 pm 113 wnh such a mrcun con guration a 29 maume Elam 275 53 e M equot n w w m mum vultages M NH u h w small 5131315 531 NMOS lnva39ta The MOSFET eah he used as a swueh m aWAde variety ufelectxum appheanehs The txansmur smeh prumdes an advantage eves meehamea1 smehes m bath speed and rehabxlxty The h39znsxstur swnch cunslderedm Lhs semunxs alsu called anmvmer gure 5 44 shuwsthe nrchznnel enhaneeahenumude MOSFEFmvmermrcmt quot27D FiguralM NMOS Invener Circuit V lt V39m veuage Ts v Alsu smee TD he puwens mssxpated m the txms ur Vxgt regun When v v the transistur Ts biased m the hehesamraneh regun the uulput veuage reaches a mmmum V 1 a 29 hmiuccmm Elam in Kim v1 7 VT m 7 vi 528 and quot0 quotDD DRIP 519 where r0 rm and i rm Design Example 514 Object Desigl the size of a power MOSFLT to meet the speci cation of a particular switch application The load I the inverter circuit in Figure 544 is a coil of an electromagnct that requires a ciu39i39ent of 05 A when turned on The effective load resistance varies between 8 and lotz depending on temperature and other v39 tables 10v power supply is available The transistor parameters are A 80 iiAv2 and Vm lV Solution One solution is to bias the transistor in the saturation region so that the current is constant independent of the load resistance Tl e minimum VDS value is 5v We need VDS gt Vmisatl V05 7 VTV we bias to transistor will always be biased in the satinanon i the transistor at VHS 5 V then t region We can then write H W 7 Figure mt 80 x 10 6 W 2 05 fi 5 71 which yields WL 78 I e maximum power dissipated in the transistor is Pmax Vosimax A D 6 A 05 3 w Comment 39 39 39 39 input current to the transistor The size of the transistor required is fairly large which implies a power transistor is necessary If a transistor with a slightly different Widt 140 ength ratio is available the applied V S can he changed to meet the speci cation EE 2 lnimduconn in Elzcimmcs 532 Digtzl Lngjc Cam the w u m m FF VDD VD the Wm be exmerhxgq urluw we can analyze the mrmxtm arms uf as parameters Ithetwu inputs are zem bum M and M are cut uf and VB 5 V when V 5 V and V u the M Cums n and sz5 mil cuff M 4 L shuwnm Table 5 z beluw m b Figure 546 A mompm NMOS NOR loglc gaie Tabbe 52 NMOS NOR logic Circuit respunse V m V H V11 quoti n 1115111 5 0 Low 0 5 Low 5 5 Low as 29 Managua Elam 533 MOSFET szurSigmlAmpuner The MOSFET L n nu m m y Fxgure u w charactensucs and the load lme The load lme IS demr mmed forv quotno vDS sun I a Figure 541 a An D 39 39 W a timervarying gate and u unH i m mm m load line and 39 We can and R2 Vsm mt 39 O L o o w 4 down the lme as 1nd1cated m the gure wrsourcevoltage L wmchmeans Th a mm na elementvalues We will skip Lhe rest at this chapter an J39FETs and MZEsFETs EB 29 mammantaEleckamcs 22m BB 329 Introduction to Electronics SUMIVIARY In this chapter we have emphasized the structure and dc characteristics of the MOSFET This device because of its small size has made possible the microprocessor and other highdensity VLSI circuits so this device is extremely important in integrated circuit technology The current in the MOSFET is controlled by an electric eld perpendicular to the surface of the semiconductor This electric eld is a function of the gate voltage In the nonsaturation bias region of operation the drain current is a function of the drain voltage whereas in the saturation bias region of operation the drain current is essentially independent of the drain voltage The drain current is directly proportional to the widthlength ratio of the MOSFET and this becomes the primary design variable in MOSFET circuit design The dc analysis and design of dc biasing of MOSFET circuits were emphasized in this chapter The use of enhancement and depletionmode MOSFETs in place of resistors was developed Basic applications of the MOSFET were discussed These include switching currents and voltages performing digital logic functions and amplifying timevarying signals The amplifying characteristics will be considered in the neXt chapter 31121113 2 Blade Circuits beluw HHDTSHH meme 4 gt Rem 1aslt gt Forwardbms dmde Kl 5mm A PNjInrtiml is present in every semimndurmr device needlessly where he cuncentxanuns are equal We start we analysts ufthe pnjunchun usmg me Fmssun equanun 39nm phyees whxnh snmph es m 17D m a 29 xmwe e Etchinns p herestOTthe resistivny butthe charge density charge an Assummg m1 mmzanun we get Eq 53 PWQD MND NA Alsu nutethat p s pmpumuna m dE dx m 17D sxtuanun Begm wnh the dupants b Juncter S 30 6 Q Hype depleuon reger 3 iomzedacceptor v Vreehole e mmmddqnor F1g47 a 14mm and pmae semmonducmr maternal b Materials after mavenan of cledmns and hole has occurred lt tree gleamquot eiecmc hem before jmmng a 29 xmqmm Etch1m Energy bands for p and n rype sc P rype nfype Ec q n kT InNdn71 F Emma M n n EFF q I I a Ev Ev The Exactnature cme bands 5 nut knuwn but the gures beluw appear m be guud representahuns a 29 xmqmm Etch1m eregmn 11ng C 011m C1 I F W emml 1 I 12m A 7 7 7 7 7 7 7 7 77 Eur Lquot Eh x Fm E urg humlx a 29 xmqmm Etch1m semcunduam RPM mm Mm rm bymvmmguneufthebands Thsleadstu a x 7x o x u p C an the builtm potential be measured WM 21 vohmeter the pn Juncuun regmn denvanve cme vultage wnh respect m x m 17D 2 29 xmqmm Etch1m oz A av E 54 577 1 dz pmpumunal m the charge density Eq 52 i 01x Kg We can see these relatmnshxps when we apply Gauss39s 13w m um sltuatlun Gauss s Law s8x AoA SSELEM pr39A I 85 semiconductor permittivity 12 for SONY p charge density C C1n3 8x xAx What can Poisson s equation fell Ii a 29 xmqmm mcmms The hrm39lel the 2 m lopmg he Ieepet the gmdmn L L L A wnhns dawn m zem at the end cme band benamg un the Ether side cme pnjuncuun a 29 xmqmm Etch1m shuwnbeluw a b Juncuon 9 G lt9 6399 e O 393 e 39 i depletion region 3 mmzed acceptor 7 free hole 6 omzeddunnr quotee elem elecmc new Fig 47 a mm and pi samuconducmx materials before ammg b inknals after mavemm of dedmns and hole has occurred buthxsulated sass 7 mm H mm the p regun a 29 xmqmm Etch1m Physical Characteristics con l dif lslon results in slanonaly charge being left behind result is quotbull in elecmc eld whlch coumerams dif lslou t statlouary charge left behmd forms depletlon regionquot Malt W at mmquot at gure M w ll mm mm mm The PN no exte connedlons A daplellon veglon forms Ihe jun ion mac mm 316 lunctlon wtlh ml 939 99999 99999999 owlmtm mm 00000000 000000000 the deplettan leglnnl resultant net current 0 A J l ltw ml mm at mmmm and mt vnAnuh39nhln lam The r slnce whlch leadsto our charge dmslty dlerlbuLlon shown below E15329 Immducunnm Ekclmnlcs 46 g mwx we get charge sepamhun whchleads m an elecm eld Junction Easy immune m a N JuuCnDu had Ohmic Holes try to diffuse this way Ohmic contact contact P N O Electrons try to diffuse this way a 29 xmqmm Etch1m o7 y accumphsh net ma due m the elecm eld See gure beluw 39 Electrons faI Ion3917 the electn39c eld gradient from left to ght Holes 727 up the electn39c eld cmve from ght to le Diffusion electl 011s Duff Diffusion holes a 29 xmqmm mcmms Ithe er Even Lhuugh there w mm W elem eld present me A memequot NFT cunean 1mm ng AND Imam JeanWAN In 71 Lha39efure net 1 n We nuW luuk ath m mure dated K39T N Nregmn 7 A i111 q Pregmn 17 7m 3 B kiln N N 4 12 7 z Let39s seehenmngvm 15 furatypxcal case mm 1e15 atKEIEIK egt kTq Isz andVb e u av 1n Therefure Vb lt 1 12V xix33 hmmmnnmEkcms o9 The next step is to determine quantitatively how many carriers we have But in order to do this we have to solve Poisson s equation which in 1D is 615 p q E 514 7 nN N q dx K580 K580 p D A When we try to solve this equation for p X or nx and px we assume we know the distribution of N Ax and ND X but we nd we also need to know nx and px in the scr but they are functions of the electric eld that we are trying to solve The electric eld depends on the distribution of charge carriers but the charge carrier distribution depends on the electric eld Therefore solving becomes a complex task of iterations So once again we simplify things by make what is known as the DEPLETION APPROXIMATION This allows us to make good approximations without haVing prior knowledge of the carrier concentrations What the depletion approximation does is to make a simpli cation to the actual charge distribution in the scr and two things are assumed I the carrier concentrations in the scr are assumed to be negligible with respect to the net doping concentrations outside the scr 2 the charge density outside the scr is assumed to be 0 These are summarized in the gure below BB 329 Introduction to Electronics 50 Depletion Approximation Assume 9 ltlt poNg for gtltP lt x lt 0 so p qNdNapn an xP lt x lt O and g 90 Na for gtltPc lt X lt gtltP so p qNdNapn O gtltPc lt x lt gtltP Assume nltlt nDLNd for O lt x lt Xquot so P qNd39NaP39n quI O lt X lt an andn n Ndforxnltxltxncso P qNd39Napn OI Xn lt X lt ch a 29 xmqmm Etch1m s Graphmally this means that m a step Junan as shuwn beluw Depletion appr39ox charge distribution p inquan Nd Coulcmz 39Xquot x XPC Xn ch qNa Charge I neu fr ali ry gt Qp 39qNaXp QK39 Qn39 O gt CIXD Coulcmz Ndxn inn 17D Fmssun equanun Simpli es in A 391 K15 NVNA fagle 0 xsix AND rle Eqs 5 151i 2 29 macaw Etch1m xpu 1171 7 J n 1 Wz n 21mm NAND quot5 q AND a 29 xmqmm Etch1m V Lhs vultage mustbe mapped sumewhere Wthm m mount must uncur armss the 5 When VA gt u the vultage un the n ma ufthejundmn s luwered relative m the p side And the uppusne mm when we make vAltn 1n uLherWurds the vultzge amp arms the m vb vA gure beluw Begm wnh the bands at equllxbnum as shuwn m the 123 culumn a 29 xmqmm Etch1m Diodes under Bias mm mamm Emu Let s consider what is going on inside the diode Initially there are an excess number of h on the left side and e on the right So an e wants to diffuse to the p side but it sees an energy barrier at the scr due to the electric eld previously created due to charge separation Also note that any e that reaches the scr on the p side will be quickly swept down the energy ramp to the 11 side drift So with V A 0 we have reached an equilibrium Note that everything for the h is the same just different polarity and directions of movement Now when V Agt0 we are making the end of the p region more positive and this potential attracts e This lowers the potential on the 11 side and on our band diagram the energy barrier from the p to the 11 side for both e and h is reduced as shown in the center column of the previous gure Another way of looking at forward bias is to think of holding both ends of the band diagram in your two hands and under forward bias while holding the p side steady ie your reference voltage raise the 11 side up with respect to e energy Now what happens to our drift and diffusion components The reduction in the energy barrier primarily affects diffusion and since the barrier for diffusion is reduced we get increased diffusion The drift component does not change much since it depends on the electric field due to charge separation The drift component does not change much since an e on the edge of the p side is still swept into the 11 side but we know that there are not many e there in the rst place because they are minority carriers there therefore the magnitude of the diffusion current changes dramatically under applied bias but the drift component changes very little and this is called forward biasing of the diode We will see how this affects current ow in the device in the neXt chapter but we can guess that forward biasing will dramatically increase the current ow through the device and it does eXponentially see gure below BB 329 Introduction to Electronics 56 1mm y I tgenww39 Dif mm 7 Hunt v At zero voltage the hilt and dif lsion cuu ents equal zero the unbiased cat Eulumns The ma Lhmugh the device a 29 xmqmm Etch1m Now let s look at what is happening quantitatively The only change we have to make from our previous derivation is that we now have V A and since we assume that all of V A is dropped across the scr all we have to change in our previous equations is to substitute Vbi V A everywhere Vb occurred What we end up with are the equations on p 216 leading up to 05 2K V V N N Eq538 W q NAND We see that the amount and polarity ofthe applied bias will affect the size ofthe scr width Now look at how p the electric eld and voltage have changed for the various bias conditions First look at Eq 538 for W We note that W Xn and Xp increases with reverse bias and decreases with forward bias Now for the case where we have a heavily doped p side and lightly doped 11 side see below BB 329 Introduction to Electronics 58 b a 29 xmqmm Etch1m Figure 511 urea Hmwardund I39cvcmclviemugnn mu IHh39plLIlun um IVH IMI IJA elm m m nlccum Held and uh ulcrlvmlellu39 pmcnl imidc n w murlum 4lhnh39 m me n39 r ieto p side to get equal number ofcharges p m r h above L A we thereislesstotal 39 39 39 39 H 39 11 an e A r e voltage across he st in foxward bias as in Figure 51m above EB 29 Inkanhmanta Elenmmcs 5 0 PREVIEW In the last two chapters we looked at BJT circuits In this chapter we introduce the second major type of transistor the eldeffect transistor PET There are two general classes of PETs the metaloxidesemiconductor PET MOSPET and the junction PET JPET The MOSPET has led to the second electronics revolution inthe 1970s and 1980s in which the microprocessor has made possible powerful desktop computers and sophisticated handheld calculators The MOSPET can be made very small so highdensity VLSI circuits and highdensity memories are possible We begin the chapter with a look at the physical structure and operation of the MOSPET The current voltage characteristics of the device are developed and then the dc analysis and design of MOSPET circuits are considered We will see how the MOSPET can be used in place of resistors in a circuit In JP ETs the junction may be a pn junction which forms a pn JPET or a Schottky barrier junction which forms a metalsemiconductor PET or MESPET MESPETs are used irrvery high speed or high equency applications such as microwave ampli ers Although the emphasis of this chapter is on dc circuits we discuss how the PET can be used in switch digital and linear ampli er applications A major goal of this chapter is to enable the reader to become very familiar and comfortable with the MOSFET properties and to be able to quickly analyze and design the dc response of PET circuits 51 MOS FIELD EFFECT TRANSISTOR The MOSPET compared to aBJT can be made very small Since digital circuits can be designed using only MOSPETs with essentially no resistors or diodes highdensity VLSI circuits includi 2 39 znrl memnr if s canbe fabricated In a MOSPET the current is controlledby an electric eld applied applied perpendicular to both the semiconductor surface and to the direction of current The phenomenon used to modulate the conductance of a semiconductor or control the current in a semiconductor by applying an electric eld perpendicular to the surface is called the eld effect Again the basic transistor principle is that the voltage between two terminals controls the current through the third terminal In the following two sections we will discuss the various types of MOSFETs develop their I V characteristics and then consider the dc biasing of various MOSFET circuit con gurations 511 Two Terminal MOS Structure The heart of the MOSFET is the metaloxidesemiconductor capacitor shown in Figure 51 BB 329 Introduction to Electronics 226 7 Scmkonduclar mbmme Figure 51 The basic MOS capacmar s1ruc1ure yum h Gava L L uxldepen39mmmty gure r Wm mmme m b a F gumaJ murmum smurrum urwmwms anhuhurlvaarmmmnrnhzlgu nvmmnmmmm mummy Wu mwmw m and g m 1rd lay me Mcs a m m an wurn amn kwcr a my mm m a asshuwn A w 315 um 39 mm mm The a 29 Managua Elam Figure 52c An accumulation layer of positivelycharged holes in the oxidesemiconductor junction corresponds to the positive charge on the bottom quotplatequot of the MOS capacitor Figure 53a shows the same MOS capacitor but with the polarity of the applied voltage reversed lnd ed Elccunn Space rargc lt gs trwersrort Ngiun lcycr a b 0 gure 53 The MOS capacttgrwrth prtype substrate ta ettect ol pdstttve gate mas showing the etectrrc held and charge new tn the MOS ca act th with an induced ed charge regiun due ID a moderate gate bias and 1c the MOS capacitor wrth an induced epacecharge regrgrt and electron tnvererdrt layer due td a larger gate tae A positive charge now exists on the top metal plate and the induced electric eld is in the opposite direction In this case ifthe electric hole in the p t p t 39 Will experience a force away from the oxidesemiconductor interface As the holes are pushed away from the interface a negative spacecharge region is created due to the xed acceptor impurity atoms The negative charge in the induced depiction region corresponds to the negative charge on the bottom quotplatequot of the MOS capacitor Figure 53b shows the equilibrium distribution of charge in the MOS capacitor with this applied voltage When a larger positive voltage is applied to the gate the magnitude of the induced electric eld increases Minority carrier electrons are attracted to the oxidesemiconductor interface as shown in Figure 53c This region of minority carrier electrons is called an electron inversion layer The magnitude ofthe charge in the inversion layer is a inction of the applied gate voltage The same basic charge distributions can be obtained in a MOS capacitor with an ntype semiconductor substrate as shown in the gure below EE 329 Introduction to Electronics 228 Holt lnw mlon layer El Induced sweetnegr regmrr c ctrou accumulation la er Figure 54 The Mos capacrtorwnh retype substrate tar ta 3 positive gale bias tn 3 mederate negative bias and lo a larger negative bias 39 L inversion layer For the MOS capacitor with r quot r h N 39 1 39 39 quot L inversion layer for the MOS capacitor with r h 39 39 a negative aw quot create the hole inversion layer 512 Channel EnhmcunmtrMode MOSFET Figure 55a shows a simplified cross section of a MOS eldeffect transistor Sou CC t Metal electrode Oquc lSuhslmle bias 3 The gate oxide and ptype substrate regions are the same as those ofa MOS capacitor In addition we now have two nregions called the source and drain terminals The current in a MOSFET is the result ofthe ow of BE 29 Introduction m Electronics w y H mm urless quw M h Scum mm Mum Gm oxide Dmmmcla Dmm Field axldc prsubsmuc b m k w l H am 6 H wl farmed The gaee material is usually heavily duped pulyslhcun Basic Transislm39 Opnu39nn h Wu w Figure 5 62 2 29 Managua Elam Zn Gm r G v Sniricc5 DiamlDl mo 5 D mvusion lnym Substrate at body rBy Substrate nr body 31 a b 0 H 955 ta Cross section at the nrchannel MOSFEI priorto the tarmation at an electron inversion layer 39 transistor is in autoquot and to cross sectan alter the tarmaliun at an electron vnversiun layer This is equivalent to two backtoback diodes as shown in Figure 56b The current in this case is essentially zero Ifa an 39 39 laver is created at the oxidesemiconductor interface and this layer quotconnectsquot the nsource to the ndrain as shown in Figure 56c A current can then be generated between the source and drain terminals Since a voltage must be I39 L charge uri uau i rur i called an L Also since the carriers in the inversion layer are electrons this device is also called an nchannel MOSFET The source terminal supplies carriers that ow through the channel and the drain terminal allows the carriers to drain from the channel For the nchannel MOSFET or NMOS transistor electrons ow from the source 39 the drain to the drain with an applied quot 39 39 voltage 39 and leaves the source The magnitude of the current is a function of the amount of charge in the inversion layer which in turn is a function ofthe applied gate voltage Since the gate terminal is separated from the channel by an oxide or insulator L 39 Similarly L L and substrate are separated by p L 39 L 39 39 the substrate 513 Ideal MOSFET CurrentiVoltage Characteristics The threshold voltage ofthe nchannel MOSFET is denoted as VTn and is de ned as the applied gate voltage needed to create an inversion charge in which the density is equal to the concentration ofmajority carriers in the semiconductor substrate In simple terms we can think ofthe threshold voltage as the gate voltage required to quotturn on the transistor For the nchannel enhancementmode MOSFET the threshold voltage is positive because a positive gate L charge If L 39 less than the threshold voltage the 4 current in L 4 39 39 39 zero If L 39 greater vuua e adrainto BE 29 lntruductluntu Electronics 231 measured with respect to the source FiDIIYP l l connected to ground G lt VTrV D quotG gt VIN D 5 G S J lrpeo lip m s i n 7quotquot in J t aces Induced cicclmn p tw region a nyer a b Figure 57 The nachannel enhancememrmode MOSFET ta With an apptied gate vattage 155 s Vm and b with an apoiied gate iaitage 155 gt VW biased A L A Finme with an 39 In the tima nn 39 whenasnraiiaiu electrons in the inversionm e r quot A 39 drain terminal r A 39 39 L39 A IL The iD versus vDS characteristics for small values ofvDE are shown in Figme58 E 329 Intmducnun39n Electronics quotD Van gt Wm V115 gt Vm VDS Figureu Pl Di 1 versus v55 characierism for small valu s s ree v65 voha Whenvss lt WhPmM w VPr Then created and the am current 5 geezer fur a gwen value um Figure 5 92 shuwsthebasl Mos structure fun55 gt v1h and asmall m a 29 Managua Elam last gt quotm Channel invasion charge 0 s DJ Deple on legion Io quotDS 8 mm mme m m length curvexs also shown m the gure Fxgure 5 9b shows the snuauon when VD menses EE 2 Immdvctmn n Ekcfmnlcs S bs Channel xmexsi n chmge VDS b L L A r Y A wmch pnjmmom L L A Y L L L L othe 17V curveto decrease and ths 15 shown m the above gure As VD VTm Fxgure 5 9a EEZZQInrmducnanmElzcrmmcs 235 S A n 1 x vDSsun rm 5 Fothxs mm H L L Y the 17V curve 15 zero We can Write m L vmtsan 51mm 0139 5 quotrx 51m termmal W39hm VD m m man a In thscase 61 u n m me mm m wward Lhe dmm andfhm L regxon 39L F 4 L 4 mm de FFT L A consmntforvnsgtvnssat L L m Fxgure 5 9a mzzgxmmmmaxemms m In S 1 39DS gtvDs4mn Channel inversian charge in T r 1 Samm on legion DS sat rm 1 We pm all this togetherto generate the famny of curves for an neehannel enhancement mode MOSFET as shown m Figure 510 E 329 Immduconnm Ekcrmnlcs Va 5 quot54 mu gt V553 55 VTAgt0 VDS Figure 510 Family M in versus 1475 curves 1m an nchannel enhancemem mode MOSFET The regon for which VD lt VD sat is known as the non 5mmquot or triode region The ideal current voltage characteristics in ma region at descn39bed by the equation EB 29 Imadummm Electmmcs 52421 in Knll m l Ts39lllDS rm 1n the saturation region the ideal currentwoltage characteristics for rag gt VTN are described by the equation in 1w is r Vrrtl 520 in the saturation region since the ideal drain current is independent of the draintosource voltage the incremental or smallsignal resistance is in nite We see that 393 Armanr mm r Kquot is called the conduction parameter for the nchannel 00 e paramete device and is given 1 WMCM 1 quot 7 T 533 where Cm is the oxide capacitance per unit area The capacitance is given by Cw EurMt d em is the oxide permittivity For silicon Where Im is the oxide thickness an devices 5W 39885 X 10 cm rire parameter 1 is the mobility of the electrons in the inversion layer The channel width W and Channel length L were shown in Figure 5a A L 39 IL L r r parameters 39 technology n v m r m m AL I L wr u e um quot 39 39 39 39 circuits We can rewrite the conduction parameter in the form 5301 Ki A w where k39 L c Nor tally In is considered to be a constant so Equation 531M emphasizes that he widtlitolength ratio WL is the transistor design quotable Vari EB 29 lntxanhctmnm Electmrncs 514 0 ircuit Symb uls arid c unveminns h h Va Figure 511 The nchannel nhancemem mo e OSFET a cunvenuonal circun symbol an b simplmed circun symbol w k lme u um mumm Thedn ectxon of h E 329 Imamqu m Elzctmmcs connected together EXplicitly drawing the substrate terminal for each transistor in a circuit becomes redundant and makes the circuits appear more complex Instead we will use the simpli ed circuit symbol for the nchannel MOSFET shown in Figure 5 llb In this symbol the arrowhead is on the source terminal and it indicates the direction of current which for the nchannel deVice is out of the source By including the arrowhead in the symbol we do not need to eXplicitly indicate the source and drain terminals We will use the simpli ed circuit symbol throughout the teXt except in speci c applications 515 Additional MOSFET Structures and Circuit Symbols Before we start analyzing MOSFET circuits there are a number of other MOSFET structures in addition to the nchannel enhancementmode device that need to be considered n Channel Depletion Mode MOSFET Figure 512a shows the cross section of an nchannel depletionmode MOSFET BB 329 Introduction to Electronics 241 v lt LGSlt 0 05 G D Elecuun accumulation Kaye C emion of an n channel depleuon mode MOSFEr fun a yes z 5 0 Figure 512 Cross 3 b V55 lt 0 and c 15 39h u n quot 39 39 it mu 1 394 F vexample of 39 39 39 39 39 39 39 4 39 2 Am 39 39 L voltage 39 L 39 voltage A L L depletionmode MOSFET to tum the device off FET with a negative applied gatetosource voltage Figure 512b shows the nchannel depletion mode MOS Anega ve t 39 39 39 39 39 39 a mien 39 39 nchannelregion 1 39 39 39 39 conductance quot 39 39 39 39 A current a Lt 39 39 4 deviced1c A A r L t L A L A positive th 39 39 39 a n um m mute 512c which increases EB 29 Imaducuanta Electmmcs the drain current The genera family ofcurves for the nchannel depletionmode MOSFET is shownin Figure 513 V552 gt quot51 mm gt 0 VI v lt Vma lt m VI Figure 513 Famin of in Vesus VD Curves for an nEhannel deple on mode MOSFEF L L A L H 39 Vrnisposidveforthe Mr Wdeu LL u L LL L r L A A I L 4 different circuit symbols are used wL L 4 I A mo FFTi hownin Finure 514a EB 29 Intmducumta Electxamcs e OB G quotg D in VDS S a D in Go 05 J S The nChannel OSFET mun sym 0 5 112 and mm a mh mude MOSFEsz shuwn m gure 514k prChannd MosFE39rs a 2 hundnnmn m Elachnnms depletionmode MOSFET M SDi Souxee v Gale Drain G D lb k J k J N prclmnnel Bodv a Cross section 01 pChannel MOSFErs a enhancementmode and b depletionmode The rest ofthe explanation in the text is similar to what we saw for the nchannel MOSFEl39s and won t be covered further Remember that currents and Voltages are reversed here G rm lin lquot a b 9 re 5 16 The p Fi u channel enhancementmode MOSFEI a conventional circuit symbol and b simpli ed circuit symbol BE 29 Intruductmntu Electxumcs Figure 517 depleunn o The pchannel m Er a convenuo de M nal circun symbol an bsimplmed mun symbol Cumplementzry MOSFETs Fxgure 5 18 shows the r A L 4 EB 29 mammantaEleckamcs Hem uxmc Polyxilicon gm Mam Mmi Contact Gale oxide nrsubslrale Figure 518 Cross sermons of Wuhannel and pchannel lransistovs fabricaled wilh a p wel CMOS echnolugy CMOS iv nil in n n val rquot 4 t L39 J39u U 0 PMOS circuits especially pow consumption Inmd mL L A L i L L A L r threshold Voltages must be equal and the mud and pchannel conduction parameters must be equal A lquot inn n ml tolengthra os ofthe transistors 5 6 Summary oI Transistor Operation ofthe MOS transistor For an nchannel We have presented a tam om model ofthe Opemion 39 39 39 39 must be Voltage g L 39 39 39 39 ForvG5gtva L A 39 39 A Forannchannel 394 39 I VGSOThed1reshold quot 4 4 39 achannel Forapchannel device all 39 39 device Table 51 lists due rstorder equations chat describe due IV relationships in MOS devices EB 29 lmxaducuanta Electmmcs Summary of the MOSFET Currenkvoliage relationships Table 51 lS PHOS Ninishturhtion region it lt t mmm Nonshtumtion region rm Y SDRM D 7 K420 7 who 7 viii D 7 Knizrwn Intup 7 trioi Shtumtinn region um gt v oshtt D Knuth 17H Tihusitiou point hturhtmn region rm gt i in KnU m Vwi39 Tninsition point i a 7 up su 7 in In Euhnuooinont mode v i owns7 ri Enhnnconunt mode V gt 11 lt 0 Dcplction mode Depletion mode m a n P39sr gt 0 517 Nun7idezl Curreernlmge characteristics Th F 1 the finite output resistance in the saturation region 2 thebodyeffeot 3 sub7Lhreshold currentoonduotion 4 breakdowneffeotsand 5 temporatureeffeots Finite Output Resismnce In the ideal case whm a MOSFET is biased in the saturation region the drain current is independent of quot HOW r at point ForVD gt ionothd nea nr 1 in th ii i u isvn thm diiiatim shown in Figure 5 19 EE 2 Immducnan tn Elzci mnlcs Ds Figure 519 E ecl 01 Channel lengm modula om resuhing in a mile omput resis ance 1x Thevoltageva BJT mi H Uh channel modulation parameter The outputreslstance dueto the channel length modulahon 15 de ned as 211 58 quotbx m cnm or 11 l V A 5 9h t e D 7 7 L quotpg 00 Budy Effect Up to this poht we have assumed that the substrate or body1s connected to the source For this bias with n however 15 shown In Fxgure 5 20 EB 29 xntnductnn tn Elzctmmcs Mlwhleh means L L the substrate effeet ehannet devlces For example conslderthe nrchannel devlce shown m Hg 5 21 below To mamtam azeror orreverserblased source 7 substrate pnjuncnon we must have m 2 0 Haul9521 An nzhannel rr enlmnde MOSFEF wnh a subslmle vonage The threshold voltage for ths eonolltlon ls glven by EE 2 lmamamo Ekcrmnlcs f m Vme iVwl SE e ml 510 where VTNU is the threshold voltage for 1755 0 y called the btllk threshold or bodyeffect parameter is related to device properties and is typically on the order ems v 3 pr is a semiconductor parameter typically on the order of 035 V and is a function of the semiconductor doping We see from Equation 510 that the threshold voltage in nchannel devices increases due to this body eff ct The body effect can cause a degradation in circuit performance because of the changing threshold voltage However we wi genet 39 neglect the body effect in our circuit analyses for simplicity Subelhreshold Conduction wae consider the ideal currentvoltage relationship for the nchannel MOSFET biased in the saturation region we have in Killrlr lrl l Taking the square root of both sides of the equation we obtain l U iEll39ri Hr 5 From Equation 511 we see that is a linear function of l1 Figure 512 shows a plot of this ideal relationship Experimental Figure 522 Plot of via versus v55 characteristic showing subthreshold conduction E 329 lritmdumiurim Electmmcs zsl Also plotted in Figure 522 are experimental results which show that when sz is slightly fess than VTquot the drain current is not zero as previously assumed This current is called the subthreshold current The effect may not be signi cant for a single device but if hundreds or thousands of devices on an integrated circuit are biased just slightly below the threshold voltage the power supply current will not be zero and may contribute to signi cant power dissipation in the integrated circuit In this text we will not consider the subthreshold current However when a MOSFET in a circuit is to be turned off the quotproperquot design of the circuit must involve biasing the device at least a few tenths of a volt below the threshold voltage to achieve quottruequot cutoff Breakdown Effects Several possible breakdown effects may occur in a MOSFET The draintosubstrate pn junction may break down if the applied drain voltage is too high and avalanche multiplication occurs This breakdown is the same reversebiased pn junction breakdown discussed in Chapter 1 As the size of the device becomes smaller another breakdown mechanism called punchthrough may become signi cant Punchthrough occurs when the drain voltage a large enough for the depletion region around the drain to extend completely through the channel to the source terminal This effect also causes the drain current to increase rapidly with only a small increase in drain voltage A third breakdown mechanism is called nearavalanche or snapback breakdown and is due to secondorder effects within the MOSFET The sourcesubstratedrain structure is equivalent to that of a bipolar transistor As the device size shrinks we may begin to see a parasitic bipolar transistor action with increases in the drain voltage This parasitic action enhances the breakdown effect If the electric eld in the oxide becomes large enough breakdown can also occur in the oxide which can lead to catastrophic failure and in silicon dioxide the electric eld at breakdown is on the order of 6e6 V cm which to a rst approximation is given by on VG t0X A gate voltage of approximately 30V would produce breakdown in an oxide with a thickness of 50 nm However a safety margin of a factor of 3 is common which means that the maximum safe gate voltage would be around 10 V A safety margin is necessary since there may be defects in the oxide that lower the breakdown eld We must also keep in mind that the input impedance at the gate is very high and a small amount of static charge accumulating on the gate can cause the breakdown voltage to be exceeded To prevent accumulation of static charge on the gate capacitance of a MOSFET a gate protection device such as a reversebiased diode is usually included at the input of a MOS integrated circuit BB 329 Introduction to Electronics 252 Temperature Effects Both the threshold voltage and conduction parameter Kn are functions of temperature The magnitude of the threshold voltage decreases with temperature which means that drain current increases with temperature at a given VGS However the conduction parameter is a direct function of the inversion carrier mobility which decreases as the temperature increases Since the temperature dependence of mobility is larger than that of the threshold voltage the net effect of increasing temperature is a decrease in drain current at a given VGS This particular result provides a negative feedback condition in power MOSFETs A decreasing value of Kn inherently limits the channel current and provides stability for a power MOSFET 52 MOSFET DC CIRCUIT ANALYSIS In the last section we considered basic MOSFET characteristics and properties We now start analyzing and designing the dc biasing of MOS transistor circuits As with bipolars the dc biasing of MOSFETs is an important part of the design of ampli ers In most of the circuits presented in this chapter resistors are used in conjunction with the MOS transistors In a real MQSFET integrated circuit however the resistors are generally replaced by other MOSFETs so the circuit is composed entirely of MOS devices In the dc analysis of MOSFET circuits we can use the ideal currentvoltage equations listed in Table 51 in Section 51 521 Common Source Circuit One of the basic MOSFET circuit con gurations is called the commonsource circuit Figure 523 shows one example of this type of circuit using an nchannel enhancementmode MOSFET BB 329 Introduction to Electronics 253 Figure 523 An NMOS Common Source Circui qur Ma V 5 v quotnu lift mA 5401 01 V a h Figure524 a An NMOS commmsoume circuit and 1 me NMOS circun Vor Example 5 3 EE 2 Immducnan m Elzcrmnlcs whxeh ean be wnueh as 1 512 w h r V thanV bxasedm the sacuhamh hegmh the dram currentls lo KuUns quot n39 513 The drainmmurce vnl39agr i I m 7 100 7 10125 514 V05 gt VDSVehn 75 7 V men he namian i hiaeed in me am ruliun region Hi we lnili39d unumrd end our dn39 h h curlrcl 1r VD lDs39 heu me mm tor i biased in the nonnturation region and the drain current is given by Equation 123 a Example 53 Object Calculate the drum Clll39lem and dumpmsource v0 mge of u commonesouroe cit lit x 11 An 5H ml cuhanwmcnmnodc MOSFLT Fo39 the cu39cun shown m lagme 7 assume mu R 7 mm R1 7 20 k l RU 7 mm V3 7 5v I m 7 l v and K 7 mAVZ Solu on From 1 Circuit shown in Flgmc 5 24W and Equation 512 WC Llch VG VGS W Assummg me uausxslm n bhzsed m me Saull39i non region the drum rurrcm 15 ID KH1V557 Pm m Htquot 7 I2 n lmA and me drum to muce V01ng l5 Vm 7 Vm 7 IDRD 7 5 7 mom 7 v v Comment Bonus V 3V gt V sawi 7 IV the Munster I m P r v IS mdeed bmscd m the snmrmion rcgmn and our analysis 5 valid EE 2 Immoth Ekcrmnlcs 255 Figure 525a shows a commonsource circuit with a pchannel enhancementmode MOSFET V quotDD VDD 5 v S5ro57sw5 0665 v lt thsutl 1 ID 0578 mA Not correct b Figure 525 lt R150kng VG25v R3 50 m Vol 5 V 3 ID 0515 mm Correct a A PMOS commonsource circuit b results when saturationregion bias assumption is incorrect and c results when nonsaturation region bias assumption is correct The source is tied to VDD which become signal ground in the ac equivalent circuit Thus the terminology commonsource applies to this circuit The dc analysis is essentially the same as for the n Channel MOSFET circuit The gate voltage is L 7 R2 U I 7 RI DD and the sourcetogate voltage is VSG IVDD IquotG 515a 515am Assuming that V lt VTP or VSG gt llTpl and that the device is biased in the saturation region the drain current is given by 1L 2 pl 139 st 1 77 and the sourcetodrain voltage is Iquotso VDD IDRD 516 517 If V3 gt VSDsat V36 V7 then the transistor is indeed biased in the saturation region as we have assumed However if V513 lt lr SDtsat the tran sistor is biased in the nonsaturation region BB 329 Introduction to Electronics Example 54 obieelive Caleulale lne drain current and Solll39cc7to7draln vollage of a COIHIHOII7SOUI OC circuli W h a prchanucl enhancemcubmode MOSFET Consider the eirenii shown in Figure 525a Assume iliar R RZ 50m V00 7 5in V v and k 02mAv3 5VRD Solution From me eirenir sliown ln Fignre 515m and Equaiion 55n we have R 50 7ll on 5 25v V R R2 5050 A The soul39cedosgzlte voltage is therefore Vsa Von 7 Vs 5 7 25 25v Assuming l ie lransislor is biased in the saturation region the drain eurrenl is D Kpll so VTPF 021m 7 082 0578 FHA and he sourceaordrain voltagc is VSD V0 7 0RD 5 7 0578l75 0665 v Si i I 7 65 v is nor greater than VSDlsar V50 V 7 08 i die pschlumel MOSFET is not biased in he saruraiion region as we initially assumed n llle nonsaluralion l39eglou llie drain eurrenl is given by In Kp13Vso Vrprsn 7 Vin and he souroe7m7draiu vollagc is Vso Von 7 Mo Combining these mo Bqu dnons we obtain 10 K12Vsu VrpiVoo 7 01 7VDD 7 DvaE D 02712 5 7 085 7 0757157 0752 Solving this qundrane eqnaiion rel1D we nd D 051 5 inA We also nd hm VSD l4V Therefore VSD lt Iggolsal which veri es that the transistor is biased iii the nousanlra7 non region Commenl In solving the nnadrane eqnanon for In we nd a seeond salnnon iliar yields V 7 293 v However rliis Value of VSJ is gl39cuicr rlian Vmsat so ii is not a valid SDIHUOH since we assumed the lrauslsror to be biased in the uous diur dilon region EB 29 ImamuantaEleckmcs 257 522 Land Line and Mndes nf Opemiun w Mm shelpful xsbxased nAuAa anu F HY 110 AW A loopresuusmEquauOnc14 m m m Mm m MM 11 m a dram current and dmmrwrsource voltage Fxgure 5 L L m Luau xstor p mm fDmxA 030 7 Nonsnuu39mion I quot05mm or n 025 Lgi0n I I 020 7 ITmusmou poim 015 7 Qrpmm Figure 528 Tmnsisior characteristics mum curve load line and 0point for We NMOS mmonsoume circuit in Figure 524 The load lme ls gwm by 7 40 5 l8a Vns IDD IDRD 518b u If 0 then VDS 5 V1fVD the dram Current 0 then dmm current 520 0 25 mA The Qrpomt othe o u u w n kansxstor 15 gl shown m the gure EB 29 mammantaEleckamcs me 39 w M mm the saturation region As VGS increases the Qpoint moves up the load um The transition point is the VD5VD5satVGS V1n As 39 f L region Exam Ie 55 Obiecive Determine h e n39ausui 0n poim parameters for a commow source circuit C Dm er the cn39cuu shown in gure 5241 Assume lmnsismr parameters of Vn I v and K lmAv2 Solution At the Lrunsmou pomt VD Vos l as Vzw 7 VDD IDRD Th dram current 15 sull i I m Combmmg he 1 dSI W0 equauonsr we oblum Vas VTN Von K1 RnU as Vm39f Rearranging Ins equanon produces mRDtIm 7 WV Hm 7 we V00 0 enemauA VANFHVW I m 50 Solvmg he quadrane cquauom we nd that VGS 7 V 135 v VDS Therefore VGS 135v and ID 235 7 0 lXZmA Comment For I lt 2 5V he ranslsmr 15 based m the sumrauan regmu for VGS gt 235 V no x39ausislox is biased in he nonsamrmion region EB 29 Intmducumta Electxamcs Ch 6 Basic FET Ampli ers In the last chapter we described the operation of the FET in particular the MOSFET and analyzed and designed the dc response of circuits containing these devices In this chapter we emphasize the use of FETs in linear ampli er applications Although a major use of MOSFETs is in digital applications they are also used in linear ampli er circuits There are three basic con gurations of singlestage or singletransistor FET ampli ers These are the commonsource sourcefollower and commongate con gurations We investigate the characteristics of each con guration and show how these properties are used in various applications Since MOSFET integrated circuit ampli ers normally use MOSFETs as load devices instead of resistors because of their small size we introduce the technique of using MOSFET enhancement or depletion devices as loads These three con gurations form the building blocks for more complex ampli ers so gaining a good understanding of these three ampli er circuits is an important goal of this chapter In integrated circuit systems ampli ers are usually connected in series or cascade forming a multistage con guration to increase the overall voltage gain or to provide a particular combination of voltage gain and output resistance We consider a few of the many possible multistage con gurations to introduce the analysis methods required for such circuits as well as their properties 61 THE MOSFET AMPLIFIER In Chapter 4 we discussed the reasons linear ampli ers are necessary in analog electronic systems In this chapter we continue the analysis and design of linear ampli ers that use eldeffect transistors as the amplifying device The term small signal means that we can linearize the ac equivalent circuit We will de ne what is meant by small signal in the case of MOSFET circuits The term linear ampli ers means that we can use superposition so that the dc analysis and ac analysis of the circuits can be performed separately and the total response is the sum of the two individual responses The mechanism with which MOSFET circuits amplify small timevarying signals was introduced in the last chapter In this section we will eXpand that discussion using the graphical technique dc load line and ac load line In the process we will develop the various smallsignal parameters of linear circuits and the corresponding equivalent circuits BB 329 Introduction to Electronics 282 3 ofchapter 4 Tableu Fourequwa enuworportnetworks Tun quotpm Vultugc unmh cr 0m m volmgc pnmmu P mt 0 mput vonugt rumut Ampli er Omyut Lun cnt pmpmm m m mva muwm A l Tuumuudumutu Ampl my Omth mncm p uponu ml 0 quotmm VolhlgL Tmnsn mahnkc Amph u 0mm volmgc pnmmu 1m 0 1ptu1rcu whxch Lhe mput 519131 15 avolmge and the output signal 15 a currmt EE 2 Immducnan tn Elzcrmnlcs 61 1 Graphical Analysis Load Lines and SmalleSignal Paramaers Figure 51 L source 39 39 I I I 39 39 characteristics dc load line and Qpoint wlme d1 dc load line and Qpoint are functions ovaS VDD RD and d1 transistor parameters I I Wm I I Qrpnlm r T39llm VGSQ l l l Vusp bn D lTlmE Figure 51 NMOS commonesaurce circuit wilh Figure 52 Commonrsource transistor eharaeleneties dc load 39 ervarymg signal suurce l n Ime and sinusm dal variation in galermrsuurce voltage dram m series Wllh gale dc saurce current and drainrtorsaurce vo lags t hnquotquot l a saturationregion Note that discussions d1 same results apply to due other MOSFETs It dxaincun39ent and drain tosource voltage as a result ofthe sinusoidal some v The total gatetosource voltage is due sum 0fVGQ and v Asv lquot v a 39 value ova lquot a A larger I t 39 39 39 39 quot alo DE 39 established 39 r 39 f HIquot nu Mn 1 yuan signal7 tosource voltage draintosource voltage and drain ement voltage For the FET EB 29 Imadummm Electmmcs region Transistnr Parameters The inslanlunetvtts gttlslu Smu39ce Vtvllagc is quotan sg r v VGAU ver 11 hcre row is the tic component and try is the ac componenl The Instanta ncous drain current is 1 cute 7 lt6 2 Suhsulullng Equation 61 into all dmduces in 7 altnit 7 vlt7 hull r kiwig 7 tw7qu to 3w or r ch 7 mg 0301 The nl term in Equation 6303 is the dc or quiescent drzlm current Der the second term is the tin ttVurying drztin current component lhzil L linearly related to the signal pg and the third term is prnpuruonal to the square or the signal v t r Fm a i t nit input xignuL the squared tenn pro ttec c e harmonic inear distortion 1 tie output voltage To mlnll nllc these harmonics we require 3 its ltlt 2lt Varo 7 I M which tnenns that the third tenn in Equation b3th in be much lhcsecond m Equation 64 rpmthem lmll1tlvtquotglltllCandi tit ttm39 ttt fm39 liucm39 tImpIg m39 Negl miller than an that man acting the r ltn tL we can w ile Equation tutti in IUU it 6 5 Again smallsignal implies linearity so that the total current can be separated into a dc component untl an 21C component The tic component of the drain current is giren by 41 NW quottag MM 0139 T e smallsignal ttrttin current is tetttteti to the mutt signut gttte ttr source voltage by the tmnscontluctance gm The relationship is E 329111than tn Ehctrnntcs I viii 397 4 M Vow L7 i g The transconductance is a trans er coel licient relating outp tl n ot s epres ting g lsn be obtained From the derivative hi ut current to input ie transistor voltage and can be thought ot onductance can a tran a m i 114th 71 with with iimsi which can be written 1m 7 1 Kttlnp IL W T drain current iersus gate to iurce ioltage for the transistor biased in the saturation region is given in Equation Ii 2 and is shown in igtire 63 The he Umemeintg signal iigx is us transconductance gm is the slope ol the curve umcicntl iiall the tran conductance m i nt With the Qpoint in 39 39 the transistor 39 linearly the ll t a co contitilletl by it ll the Qpomt moves into the nonsaturatitin region transistor no longer operates a linearly controlled cuirent source 39D Slaw g Figure 53 Drain currentversus gatetasuums voltage characteristics With superlmpnssd sinusoidal signals As shown in Equation man the tr timial m the conduction parameter wind 1 ratio Therefore increasing the width at the tra transcoiidtictance or gain of the transistor aiisconductance is directly pmqu 391 int n is a function ol the width tor inciea es the to lengtl iii39 a titlitiliit iiiiisisior is tr lI QI39y i tiliitli is i 1 Inquot The Inn scottducmncc utlnn ni39M SF Ti ll ctinipiiieil in time ir mi utiiimi lllc riilitiiittigii til MUSI39ET i iiiiiicttliiiec Nlllt lii MIC iiiti i0 piiiiei aissliititititi Cummenl The utiliscmiduchilicu i m V tor a cullt cmr cumii 39lti 0 he will iiitliiite Illgll iiiiiii EE 2 imaiimhh in Ekcimmcs AC Equivalent Circuit l mm gure 61 we see that the output voltage is l39tts 397 la Von T IuRu M Lsing Equatitm 6 S we obtain quotll Om T no T WK I Vnp T thRn T rtRn 6 I The Output voltage 390 2 cumhmatiun ttl tlc zmd t vzllu s The rm Varying Output signal is the time mining druinlostmree nltage or 611 012 n summary the folltming relationships exist between the time varying e circuit in Figure L1 The equalinns Me given in lenns ttl the ntaneous ac value s uell as the phascrs We have I signals for th in v trim tw it cr V 11301 gmtg tutu or V twat we iiiRu 01500 Ur Vm rLtRn mum The ac equivalent circuit in Figure 54 i developed by selling the dc sources in Figure Ll euttal tn zero The small igmll rellitium hip39 are given in qululions 513 514 and 515 As Show in Fiuure LL t e tlrain f E R t which i compose u slg nnl superimposed un the uuie ent value nous through the nllage source rm since the voltage acress this a 2 inhumaeenu Bach1mm Figure 64 AC equivalent circuit of commonsource amplifier with NMOS transistor thselanem r h nrmw A VDD xs at signal gmund 612 Smallrsiglal Equivalent Circuit m m 4 wemust awaup a smallrsxgual equivalent mam fur the mam initially cmbenegleded Themputtu the gatethus appears as an upen nrcmL uranm mteresxstznce Eq 5 14 relates the smallrslgnal am cunean the smallrslgnal input vultzge and Eq 5 7 Shaw thanks NMOS device s shuwn m gure a s Thephasur cumpunems are m parentheses a 29 hhducmm Elam Figure 65 Commonsource NMOS transistor with smallsignal parameters and b simplified smallsignal equivaient circuit for NMOS iransisior 11 11 1 1 1 L 1 1 1 1 c MOSFETL39 439 L 39 39 This eifect quot 39 39 39 39 C L nonzero slope in the in Versus vns curve We knowthat 11717 Kuhn r 1111 1v11 110 here 1 is he channellength modulation puraincier and in u pmiiii39c Linunity The sniullsign31 oulpul resistance uh prminusl de ned is i 017 11mg Wanna or 1 r 1lt1r 1w 7 r f 39x WW 11m Tim smuil ill uulpui resislunce is also i l39unciion 01 1h Qpuiul pm umelers r quot quot 39 39 39 the n l MO F39FT is shown in Figure 66 in phasor notation 289 BE 29 Intxudummn m Elemmmcs ended smallr ui Figure 67 Smallrsignal equivalent circuit a monrsource Circuii w h NMOS Iransrslm 1 Figure 66 Exp signar equivalent cm 1 39 eluding output resistance to cum MOSIransxslor mo el mung cunsxdered m Chapter 4 a 2 Manama mm 290 Example 62 omecttve Determine the smallsignal Ullilgc gum of a MOSPET circuit hor the circuit in Figure 11 assume parameters 211 39 Q 2v V and RD 7 am Assume lmnst or parameters are VW 1 vi 080mAV i 1002 V me the iru istor is hiuseit in the sulurauon region Solution The quiescent a iies are 119 7 rm 7 VW O821i 71f 10mA and Vase 7 Therefm39ei rim 2 5 v gt 1quotStsut V03 7 W L82 7 082 V which means hm the transistor 15 hiased in the saturation regmni as initially asaumedi and as rcquircd for n linear ampli er The irnnscunitiicuince is Hm I M V559 V1 c 208212 71179mAv and the Output 139 JrD91quot 0t21quot h om ngre 6 7 the output wtltage is tzmce IS 0 k9 h Is to gdr39ollku Since VM 4 the s urn signat untiage gain is nrtt39atlkri 71 79x5 Comment M FF39T smallestgnal nottage gain than cornparabte bipotar circuits Atso the smallestgnal nottage gain contains a minus sign A p input sinusoiotat signat Prnhlernesnlving Technique MOSFET AC Analysis since we are oteating With tinear arnptifiers superposihon appties which rneans that we can perform the otc t t L A quiescentsotuhon The transistor rnust he braseotin the saturataon region in oroter to prootuce atinear arnptifier EE 2 Immduconnm Ehcnnniss 291 Z r a r a r lLs smallsrgrlal equrvalem Clmult r m u r r the response othe clmultw Lhe leervarylng lnput srgaals only l nr du Theprevlous dlscusslon was for an rrchanrlel MOSFET ampllfler The same baslc analysts and equrvalem a m a r MOSFET b FigureEE la equivalent mull rr r w h VDDr k m y l supply H2 mm FFTclmulLs wlth the dc voltage sourees replaced w c V H r a m wrmwm 10 292 E 329 Immdllcnan tn Elzcrmnlcs Figure 510 SmahesIgnal equivarem circuit at commonrsource ampmzerwnh mos transisiar made Mn FFT zmph er emu 51 BASIC TRANSISTORAMPLIFIER CONFIGURATIONS As h Threebasn emmer emeefeuewee and cummunrbase cun guranuns usmg BJTs These parameters as well as vultage gem fur the three has Mos FET emu cun gurauuns Wm be determmed m the fulluwmg semuns 53 THE coMMoNesoLchE AMPLIFIER m the semun we cunsIdethe Sm ufthe three basI IrcuIts the cummunrsuume amph er We Wm analyze Impeaenees 631 A Basic Cmnmnnrsmn39ce Cnn gurz nn R m lR shun cIrcuIt a 29 Imeduccmm Elam sourcew As WEW 7 the amph er mput resistance R Rx H R2 m orderto mxmmxze loadmg effects Von R R D R5 Ca 0 V A K1 Figure 513 5 gure u h m mom signal voltage V are gwen m phasor form Figure 614 Srraursxgna equwalem cucun assumxng cauphng capacnar acls as a shun mm a 3291xmudnccanm Elgcms The output voltage is Vt quotSm Vgtlt rllRo 627 Tho input galcrlorsourco Vollago is R V V 28 3 R Rm so the smallasignal voltage gain is V I R A 77 mute 629 Wo can also rolato tho ac drain ounont to tho ao drainrlormmrcc voltagor as Vttr I D Figuro 615 shows tho do load lino tho transition pointr and tho Qrpuiul which is in tho saturation r gion As previously atatotl in or or to rovido tho maximum 5 mmolrical output voltago swing and koop tho tmmistor biasod i tho saturation rogion tho Qrpoinl must ho noar tho middlo of tho a39dllu39aliun gion At tho 3a 1 39 ll ILL tho input ignal must ho small onough for tho ampli lior to romain linoar 39nn I mm a i on RD I b5t1ltquot5 39m I l Trttnrnrmttmnt I L Qpmut a loud inn vlmx39 Figure 515 DC load ltne and transman paint separating saturation and nunsaturatton regions EE 2 immducnan tn Elzctmnlcs Lhe amph a 15 RE R H R Smce Lhe lowr equency mputresxstance lookmg mto the gave ofthe MOSFET senhally The output equal to zero whxch means LhaLVc 0 The outputreslstance lsLhaefore Ra Ra H ra Example 63 Objective Dclem39nne the ma rsxgnal vullagc gm and mpuI and umpm mumm or a commumsourcc umph cr For the cucun show in hguxe 513 the pudrnde are 1 10V R mum R 1 Tm and RD 5L9 r a Lmnuum39 pzu39umela m I39n LS K 5m39V and mnr mumc RE 4m Soluliun DC 39nlulla nns The dc nr qmesccnl galerlorxuurce valmgc i quotasg yvmx mi ylm 111 v Th qulewenl drain current u lug Kn v39mgr I 1 UEJIZ 917139 ImA and the quiescent dramrlnrsource ullagc Is Hug Vim r IDQRD In 7 11 H5 5V Since r059 gt rug 7 r the unnqus hmed m m mlumlmn zegmn Smallrsignal Vollage Gain The nail ltignal mnscnnducum gquot n then 115W29lrl 5 14xmAv Sm 31 Vnm T md me smallr 11 au pul rcsls ancc y 5 21le Lumnmr 1mm Th ampll cr mpul r noel Rx RTIR 7ow191 MLQ me hgum a H and Equmnn m 2 he smalhsgnal ul A rgmwknur 05 7141 1005 7 r H 201374 Rl Run money mam md the umph a umpul si anc i Ru Rpm sunur 47th Cnmmenl T mumng Qrpoim is in me serum or me land line but nm In he ccnler he of me summhon raglan Therefure this clmnl docs no Ichlmc the nmimum sun meuicai hmpm Huge gtng m m cue EE 2 Imamqu tn Elzctmmcs he mmlHIgnul mpm gmamumcc nhugc n Discus 39 R M 7 quot KARM quot 1054 V39 M quot Since m n um um hc Jmpli c inpm up I39K m Approximmcly M pcrocm of H gum mung Hm n ugqln called 394 lnudmg cfl39cm hven Hmugh he mpm 1cm 39ncc m gm of me mmmm w cw Hy in nne hc hm re Marx gmny in ucnu me Ampii cl inpm mmmcc md Inn g af x 531 CmnmnanmIrce Ampli u39 with Sauna st39mn39 Figure m Cnmmunrsource mrcunwnn suurce reswsiol am Dusmve and neganve suppw manages m fur example res urwas mcluaea taken mm accuunt The substrate nut Shawn vmuld nur mally be cunnected m the 75 v supply 5 that the a 29 Managua Elam wewttt neglect thts effect Example 65 ohtective gnal voltage gam of a common sottrce circutt contmning a source sts or Consular the atrcutt tn hgut e 318 The tram tor parameters are I m Otx V t mAVz and A U Dtlcrmine the small re t Solution Hum lhc tlt tly t1 ttt L TL t wc I ttttl tltttt X39uw ltsttv W u SDmA and I m 25v Um amullraigmlt lmnscunductance la L quot IKHUL 39 3 ZHNLSU H0 I 4111AV and the smtttt ttgnttt reztslance t n 7Inglquot av thttre ml xlmm lllc mulling MnunMgnjll cqttimlcnt circtttt thute 6 19 tut source resistor 39t39ttc uulpul voltage 15 quott lt2 quotLtRu Writing a KVL cquzmun from the inpul around he gal rzom c luUp we and gt Rs L 39t mlttl s 397 EB 29 Inkamchmtalilectxamcs The small signal voltage gain 15 1611 me nan 519131 vollagc gum would be uppmxx We may now 1131 if gm er 12mg 1 male I he mun 5191211 Vollagc gain Howmr us 115 nan a xliml agmml vanminm in 111 v n gi cs A w ment A sourc rmsmr reduces 1 the Qpmm b x 1121 ha uppmxxmme vnlluuc Lm cussed in 1h lzm chap m p v ET 33 gcncmlly low the approx er mr parame Ve may um 714 Smc he uaxmnnduclance UFMOS m uRs imal gain exprmion 15 a poor mm at best Discussxun w menunncd lhzu Including 1 mllrc rcxixlur mud U gtluhi1i1 lhc Cir 11 rm cxumplu m cun elm rlcrmm canducuun pdrumelcr A umcs b mm um chmng m lmugtigtur purmnctm mo percem 6 nd me muom ng mulls Kn u 1 g nuH ullmg cllungu m m Amy bu expecmd nu Chung m 1quot mmluucx 1 mm lurgc Chung m Thu A N V A lt perccm I because he mum mlue 012 15 muller mun hm of m hipular cm 633 Cummuanuurce Circuit with Suurce Bypass Czpzcimr Fxgure ayn u EE 2 Imamqu m Elzctmmcs Figure 522 NMOS commonrsaurce mmuil with source bypass capacitor 2 29 Managua Elam m gnal voltage gain ol a circuit irrent uuree an incorporating a source bypass capacllurr nit shown In Figure 6 22 the transistor parameters are V L1 1 1 Example 66 objective Detennnte the s all r biased with a constantw s For the ci W on i mAV Solu on Since the dc g le current is LEWL the dc voltage at the source terminal is 393 Jam and the gate losource voltage is determined i mm 1ng In KnU osg Viw2 o 5 a 1 Vng 708 which yields qu The quiescent draubmvsnurce voltage is 7 057 7 7151 301 V The tra The smal g F g g 3 a r a E E as 5 a l signal equivalent Circuit Figure 523 Smallrsignal equivalent citcmt assummg ins ssutce bypass capacitor acts as a shun circutl 0 l i 39ngith Sinee Vm I the smallsh al ulluge gum is 1quot T umkti 4l7l a 7 X Compunng the smuthsignal Vullnge ain cm s in 111quot example to the 5 it lutnlt 5wtgtcclIl g tlte guin r I quot cupucilur is includedi EE 2 Immdumnn tn Ekcimmcs SOURCEVFOLLOWERAMFLIFIER The seeeha type ufMOSFE T amph a39 m he cunsdered Ts the eemmehearah urcuxt An Example enhs emu cun gurauunxs shuwn m gure a 28 Figure 523 NMOS sourceeionower or cammorrdrain ampuher eehheecea uently m V Smee vm heeemes 3121 guund m the as munelem 5quotme we get the name app arm as we pmceed thmugh the analysts 541 Smauesigmwnlmge Cain smallrsxgqal analyss The shhalhsxghal equivalent nmmL assummg the Euuplmg capacxtur acts as asth s a h T m wnh all signal gmunds at a eemmeh pumt We are zgam neglemmg the budy effect The uulput veuage Ts a 29 hhduccmm Elam V K We 7 b a Figure 629 13 Smallrsignal equivarem nircun a NMOS source lollower and 1h 5m signal equwalenl mrcun o1 NMOS sauvce tonnwer wilh an Signs gmunds at a common pmm EE 329 Introduction to Electronics Vt Cm nXRr ll39tt It 30 Vi39iling a KVL equation l min input to output results in the l ttllouing a quot gm lltRs ttn n no IJl l ant Equation i31h is written in the form l a 11lage dl39idcr qiiatinn in gatetusmi ct iiiquot the NMUS device luoks like a resistance With a which the urine et 1 g More accurately the ert eetiite resistance looking in the nuns tenninal ignoring r is lgm The voltage V is related to the souice input voltage K by tm 7 L R T R where Rt Rille is the input resistanee to the anipiirier Substituting Equzitiuiis6t31band on into 630 we have the small signal voltage gain 5 032 quotmanllr39tJ Rr 1 L mle lv39n Rt ARsi mun 6 3300 vhich I n is written in the term of a voltagvdivider equation An inspection of eqtulmn 633b shovis than the magnitude ofthe voltage train is alwa sl y 3 than unity This result is consistent Wllh the results til the BJT emitter follow ei eiicuitt a 2 meantime m Enemies Exam IE uhjechve lollowcr enetnt tn Figure 5 Calettlate the smttl gnal voltage gatn or the Volll co x sumc the etteutt pat ttmclcls ttrc V00 l2v R 52 m R 7463 m and R 075th and the tran 39lt or pttrtmwtcrs ttrc V lav It39n 4mAV2 and 7t nnl vr Also As lntc Rs m nlutlnn The tie analysts lcmhs Mglml ttattsenndttetanee ts tltetet39or are 109 797m and I m 29IV The small e gm 219er VT t 24t29 and the smttllrslgnttl tramntor rcsmtmcc ts re 2 Wugl S1ntAV mm hum l7 The ttlnplllicl lnpltl rcltlltltmcc ts R gum lzn m The smull 5lgmt voltage gatn then becomes ymlelll lt l Alto HI I gmlRSHu Rt Re I ttll 3ll7llll 860 l I70 t 4 On The magnttttde ol the smttllrslglml voltage gum llt lclts than I An examtnar lion ol Equation 633k shows that Him 15 ttlwttys lluc Alsu th a t 7 e u pt ltltlvc which nicam that the ttput stgml voltugc ts tn phav tttth the nptli signal t ttgc SIHCC the amp sourcc follower e t t tgtal is essentially equal to the 1quotle ght the menu is eallect a Discussin The cxprcsmon tor the voltage gatn or the sottree followcl is essentially clenueal m that ol39 the btpnhn cmtttcl vcr stnee the lrttnwmlducttttlcc til the BIT the voltugc gum oi tl tullot ts tn gcltcrtt lttrgct than tltat ut the MOSF te emitter t39ollmtet Wlll be closer to unity than that or the MOSFET suurcc rollover E A though the lnltage gum is slightly less than It the smmce l ollttwer is extremely useful cir tit because the output resistance is less than col nmun uurce circuit In output re tztnce is destrubl ire is to 39 t 39 an ideal voltage source and drive luud circuit Vtithotlt suffering any loading affects an t that at a 6 when the c39 39 a 29 twitteth slams 642 Input and Output impedance The 1nputreslstanceR as de ned m Fxgure 6 Z9b1sLhe Thevmm equwalentresxsmnce ofthebxas reslswrs m man m A loadmg effect t mm a test Fxgure 6 31 i r Figure 531 W voltage the output impedance 15 Simply an output resistance mm 15 de ned as R VxIx EE 2 Immducnan m Elzcrmnlcs Writing at KCL equation at the output source terminal produces 03 gk s 0 Since there is nn curient in the input portion ol the circuit we see that Vg il Therefore Equation 635 becomes u shut 0300 037 Frm n Figure 6 31 we see that the voltage V directly ticross the current source ngm This means that the effective resistance ol the device is lg The output rcststance given by Equation 637 can therefore be vtriiten directli This result also means that tie res ce 100kng into the source terminal ignoring t is lgm as pmvlnusl note Example 69 Objecllve Culculutc the output itsistuiice or u MVUI CL J39UHUWL39I39 circuit 39misidcr Ihu vircnh shown in Figilr i 28 vilh L lrk uil ziiid lrztimsmr parAmman gum in Euuuph m Solullan The I CMJIh or E lmiplc o art 07quot ME n ILSLSZ And 3quot it3uiAV Usuig Figurh tn uiul Euuutuiu mm c lilid l HRdllut l I 3 075 R4 7 mum m 7 7x 72 Comment The output msutuuuu or u tiul L Clullmwl citcuil is tltinmltllctl by he because the mllptil mituuicc i very hm lhc mum uhit39h mums tliLil llic nutpul tutu drihc iiscontluctuncemrumctcr rolloucr tends to hut like Lm ldcu Voltth ol uiiutlur cnuull uttliout siguitiututt luudlllg ttl ctts EB 29 Inkamchmtalilecixamcs 55 THE COMMONVGATE CONFIGURATION ume aw prsvmus MOSFET cums 851 Smallrsiglaanlmgeand Curran Gains gmund Figure 534 Cammanrgme circum and uuplmg capamm Cc cuuples the uulput vultzge m 1m resistance R n u assumed m be m mte a 29 Managua Elam Figure 535 Smallrsignal equNalenl circuit U1 cammomga e ampnner The uulput vultzge s n 38 Iv 301 MAIN mu 150 mm me what gum 13 posmm m output and npm sugnal are m rhusc n nmry mm Lhe sxgml input to u c0mmun ulc want 3 2 Lun39Enl Figure 030 sl uws 11 mal usual equnatm anmonrgan m m with a Nor39on eqmull m 1 en 1 the 5mm snurce We um calculate 1 currsm gum 1h Uu39pul cunenl 1 mm b mum 1 1w 0421 m m inpm wc hm ram 139 A43 a 29 Managua Elam Figure 535 Smanesignar equivalenlcircuil m commonrgaie amplmer with 3 Norm equivalent signal source atU Th 39 ms c may mue um 1139 Ru 1v L and 3mm gtgt 1 mm 11 current gjin 1s cxscn H113 umly unit 1 m an uleul EJT eunmmnbase cucml 551 Input and Output Impedance advantage The mputreslstance 15 de ned as a 29 hmduccmm Harms R 7 4 4 I I 39J Smee I 7gquot V the Input re R L 647 This result has been obtained previou We can nd me uulpul resistance by seumg UR Input algnal voltage equal in zero From Figure 635 we act Lhal V5 igny 123 which means that Vge C6 equenlly gnuN u The output resi ahee looking back i mm Lhe load resistance IS Thereiore R 12 642 Example 510 Objeclwe For hc aommowgmc circuii deiemiueihe ompmvoL mgc for h given mpui ehrrehi For ht menus lthoxm 1 m 139 SY V Em or pmhmciers MC V i l V current R Inn mlwlpiA and mum 11 in Figures 634 mid 636 the eimhi pummeiers Arc 5v R mm m an RL am The Assume the mpui r K 3 lmAV and e sn m Snlulmn The quieseem ghieimsomee veiuge i dc cmuncd 1mm lg leg T Mth VmV 1 mm 1 which yields 1 Q9 The smallrugndl mnsconducmncc 5 EE 2 immaqu tn Ekctmmcs Sm 2KtlGSQ Vm 313 1 2 LAN me Equauun x 45 we can write th output current an gm Rs Rs The Output oltage i IQ Inkb so 6 nd V RLRD L mRSt RIJRL Hanks 39ILI mu m V0 U 283 stn 01 V Comment As vtith the BJTcommun basc circuit the MoshE39l commongate amph Her is useful tr the input signal 15 a current 66 THE THREE BASI C AMPLIFIER CONFIGURATIONS SUMIVLARY AND COMPARISON Table 61 39 39 39 39 39 39 Table 5 1 Characterishcs o the three MOSFET ampttlrer cmltgurattons Input mimmcu ulplll mimum mliiullmtiuu mum min urnIll gain Cmunmn uuruc l 1 km MmlL39lulL39 tulltglt Suulcclullmwr t t R u Common gale t 1 I Lou I udcxttlu lulug1 quot1 quot 39 39 39 L 39 quot circuitsis 39 t 39 39 n t 39 39 m discth Iquot quoton c 39 ampli ers is the 1 L L 4 4L Theoutput EB 29 Imamchanm Elecuamcs 57 SH IGLEVSTAGE INTEGRATED CIRCUIT MOSFET AMIFLIFIERS In the last chapter an heehahhel enhancementrmode demos an heehanhel depleuonrmode demee and aprchannel enhancementr mode demee The MOS trmsxstorused as aload demee 15 refenedto as an aeuve load We mehuohedthat these three ehemts eah be used as amph ehs In this section we revisit these three euemts and eohstdeh than amph eh charactensucs We Wm emphasize euemt amphheh designs consideredm Pan 1 of the text 571 NMOS Ampli erswith Enhancementhzd t t t a Figure 6 38a shows an NMOS ehhaheemeht loadtranslstor D vmmr 45er Transislnr chamdcnsdcs I W I D VIM DD 27 a b Figure 533 o1 Iransislar and thure 6 38b shows the currentrvoltage charactensucs The threshold voltage Is vm thure 6 39a shows an N39MOS ampli erthh ah ehhaheemeht load EE 2 Immduconnm Ekcrmnlcs Van rpm 0 a vm P a J MD MD n MD m a cutoff Salutation Immatumuun bu L n 39uum Qpumt Tmmilion mm x t 0 quotIND quot65quot c Figure 639 a NMOS ampli er with enhancement luad device b dnver transistor 39 int and 2 Voltage transfer 39 a characteristitx and characteristi 0 N The driver Figure 5391 the load device Since the i E 329 Intmdummn39n Eledmmcs nhancemen e t mad mrve with transition p0 MOS ampli er with enhancement load demo 1 L W andthe load nonlinear DD 7 vm L quot Thiscurveis showninFigureo39c m L 39 39 4 saturation region For use as an ampli er the circuit Qpoint should be in this region as shown in both Figures 5391 and c We can now apply the smallsignal 39 39 39 39 L A 39 L follower with R5 oo was R0 1 gin H ro The smallsignal equivalent circuit ofthe inverteris given in Figure 540 where the f remem39 vel r effect ofthe load transistor MD Figure 640 Smailrsrgnal equivalent circuit of NMOS inverter with enhancement load device The srnallsignal voltage gain is At 2le V on Mt 649 gmL Since generally lgmL ltlt 1 L mid lgmu ltlt W the Vullugc gain to a good lippnyximllliun is given by is 4 L A u t 51 w L 39 39 3 o 2 V M ThL vlliigu gum hell is rcllilcd l0 lht size at lht lwo lrunhihluro E 329 Intruduwunlu Ele mmcs BB 329 Introduction to Electronics Design Example 511 Obiecii e nexign me 3911quer ml vohugc gquotn or an NMLS mp1 u mm cnlmnccmcm lmd and m h H Qrpnlm m he middle ur the saturation reginn Cnmidcr 1m drum Imn in ngm 5 19m win lmn Vm xv k sowvi and WUL L lhc cmqu pum Design me clrcui we mm m mlugc gm i w m lnr pummelcn rm mclcx m V 5v um 50 M haw Solution me Equ39 Vme AJ 10 7 rruLIL rherermc H MdHHnrlcngxh who of me dnvcr mnsmr mu he w 2 w 7 7 m 7 7 mu 1 m I ML 1 n1 canducuun pammclcn are man My w moms 39gt I SmAvz and Thcrernrc um 7 I m mm 7 I m 7 f K n V Wax My 15 man 157 xiinounmr 11 which mm lmml m1 pnim valuw of my 135V and my umv a 29 Managua Elam th idenng iirc rcmlung ulmge lmmkr chnmder c Vlinwn In ngic mi hc middle of me muruumr xegl r rm i rquot mlfwuy bcmecn inc cumii palm VM 1 I Liiddiel unparmivm 3Vnx Mm iiw ing 5 Own am 4 r p r 3 mm V J QP l r Tinnsman pm i i n 14 i6 Gmm i in L2 vagaixv H v Figure 541 vaitage irarrsier cnaracierisiics and Orpaim M was ampimer with enhancemem iaau mi Exampiee n Commen Tth mum mow um Avery iurgc driimncc r required in lhc rim thc A 39 u mm mm m produce r gain of H In mm a gain niii ii mu lhc large p gall that can be prudutcd by an cnlmncemcm ma dame A iurgcr mullrvignml gm quot 39V39idri39rlquothiiiv1 mi mum Design Pointer The may cfl39ed ni he loud Umhmnr rm ncgiocicd in UliV unmlwn me cxumplc 571 NMos Ampli er with szlajnn and Alsu the slupe uf a 29 Minimum Elam m Dmzx1 Tmnmmn pail a b Figure 542 a wim gene and s A was 4 load ampn a w curve for the cxrcuxt are shown m Fxgure 6 430 MD and My are also mdxcated D ML EE 2 Immductmn a Ekcfmnlcs m we 7130 V0530 Smce the W The dc voltage curve about the eromt Agam both MD and ML mustbe blasedln Lhelr saturatlor reglons at all tlmes Flgure 4R tquot Ella m IV 2m 4 Vn39L Qrpoilu 0 VIM GSD C Figure 543 1a NMOS ampli er wllh deplelian load device1bdrlverlransislor characteristics and depletion load curve wilh Iransilian palms and 1c vallage transfer chamelene lcs We ear agam apply the smallrslgnal equrvalerrt elreurt to flndthe smallrslgnal voltage gam Smee the gater r The smallrslgnal equrvalerrt elreult of the rrrverter ls glven m Flgure s 44 where n source termlnal ls Ru refer r 0 effect of the load demee EE 3 lmmelmran tn Ekctmmcs MD M Figure 544 Smalksignal equivalent Circuit 0f NMOS inverler wilh deplslian 03d device d 10 smallsignal antagc gain is lllcn i39iiiull liulll39ul 6 In this circuit the voltage gain is Hardy propul39LiannI to the output resistances of me two lmnsistorsl Exam Ie 512 Ohiecllve Dclcrmmc lhc smalllxlgnal vollilgc gain nl39lhe NMOS iimpliiiii th illplciiiiii liiuil Fm Ihc Clrcull shown in Figure 643m assume mll iix lm piiriiiiiclm nl39 rm 408 v I39 7 7175 v Km 7 lmAVz KM V lizmAV39K and 2 1L 7 lull v Altltumu he llillnlslnrs i ed iii M 02 mA Snlulion The lriln cnnducmncc of Ihc dn39vcl Xi gm 7 Zvi KwID 7 Mm 7 LKUJmAV Since 2 LL he Dulplll ieiiciiiiim iiie l l I 0 quot Lizlwflllulxozl 3mm Tl aluilllSlgnul OIhlgc gain is Ihen AV 7gli anliuLl 7 7ioxy4ii5lxl sum 7224 The Vulluge gain iir he NMOS ampli er wiili dcpleliml liiiiil IS in genel39ull signi cunlly larger lh nn iiiiii iiiili lhc ciiliiiiicemeiii loud ileirimi The had cl l m Will lower he iileiil giiiii riiciiii Discussion mic LISle of Ibis clrcuil d lg thl we have iiiil ciiipliii ml is It dc hl sillg We lncnliuncd iliiii hon ll39a slnm nccil I0 be mm m llieii iiiliiiiiliiiii regiiim liniii quotIgurc HEN ilii dc hiu ng is accomplished wiili hc dc snurcc l39 l nic39cr became or the swap lan39 at a lmmrcr chmcicnslic Figure 5 mm iiiipliiiig ilic quotCorrectquot vnlmgt became dll cullv m we will cc in It ncxl SCCllCIl Il dc blib img S general accompllshcd viiui cumin source biasing BE 29 Intxudumun tn Elemnics 673 NMOS Ampli er with PMOS Load CommonVSource Ampli er a Anampli er 4 andapchannel showninv39 39 39 Thepchannel 39 H A fmmMaandIam 39 39 39 39 39 to their mi 39 Figure quot59in Chaptersquot 4p 39 39 39 39 39 39 quot aa CMOS ampli er Vuu 392 Qpmnl 15m 39 1 Slopcri 1 39ip 1 1 1 1 K501 M 10 Vnn I Q pnml QM A Vail 12m quot1 C d Figure 545 13 CMOS mmmanrsuurce amplitrer1n PMOS active load v characteristic 2 on r 11d s 39 iv 39 39 39 h 39 Fimlre645b W t t 39t 39 constant and is established by M3 The driver transistor characteristics and the load curve are shown in Figure 645c M All h vaintn39 quot 39 39 39 transition point for M2 The Qpoint to establish an ampli er shouldbe approximately halfway between mint A andR E 329 lntmdumunm Eledmmcs m m 645d m quota the desxred Qrpomt thhvm held constant 0 4 39 qur 646 b d r L r n m 1 t b A quotWh1chlsLhe same asLhe source ofM and the body Lammal ofM2 wm be uedto VDD which s the same asLhe source of M2 Hence has 15 no body effect n ths cmnt 652 51mquotn H quotm Again r01 this binmt lhc smallrsignal voltage gain Ls dn39cclly pmporliomtl 0 ha onlle r mums of the we lnumslurs PH MI 412 Figure 646 Smalhsigna equivaient cvrcuil 11 Ihe CMOS commanrsuurce ampli er EE 2 Immduconn m Elzctmmcs Example 6 13 Dhlec ve Dclcrmint the small signal v lag gam lil lhe CMOS ampli er bar 1 K V mr puramtlen ol V 39 w 11 Circuit sliiiwn in Figure a 4st 7 xv Ic S Lp 3L H SUpAVj A Alsoi assume 1Em U Solution The ranscnnduclance 01 1h NMOS driver is Wigup 0 8 TV lhe Uulpul reslslances an 500 kSZ l l 39 quot 390quot 2110 7 001 rlis small signal Vullagt gliiii is llmi UU7173 Ai willWilla 0 Mills Comment Th nllzlgc gall of 11 mos limpli ci is on ili same order oriiiagiiiiuils as he NMOS limpli si iiilli ilsplsliiiii loliil Howcvcr he cmos ampli er dots not suffer from the body cffscl Discussion 4 Pi up 6453 ofMl to achieve the proper Qrpolnt CMOS SDHI CEFDIDWEY and Cummnanate Amplifiers L A r ll and commonpgate configurations Figure 6 473 and b show these Circuits EB 29 mammantaEleckamcs Dm L Y 7M1 u L d Ina 0 V moi Mt Dmot I a 1 gure 547 ta CMOS sourceriuhuwel amphtter tn CMOS eummortgate amptmer We see that for the sourcerfollower etreutt the aettve load M2 is an heehahhel rather than a prchannel devtee The thput ls apphedto the gate ofM and the outputts a the source of M For the commonrgate mm 7 L Ldevtee M andthe output is at the dram of M1 We note that m A the body aeeouht Inbothmrcmts L L A L negattve voltage whteh is hot the same as the source terminal 5x MULTISTAGE AMZFLIFIERS w L an t t t amptm t wnutr L v F r wn may exceed that whteh eah be obtamed m a singlertransxstor circuit Transistor amph er circuits ean be eohheetedm senes or easeaded as shown m Figure 6 48 Thts may be LL LL L L orprovldean thanl wtth L EE 2 Immduconnm Ehetmhtss Figure 543 Generahzed Iworsmge ampli er type ufanalysxs required 531 DC Analysis mm r m suurce fulluwer has aluw umpm impedance L r Rs 1 IANWHEH w Figure 509 Communrsaurce ampli er n cascade wnn sculce Mower a 29 Managua Elam Design Example 514 Uh er u Damnhebxasx1gofamummgeMosrbl39 cncml w mat vpecl c qumremenm Cnrwder he cucuu ahnwn m h e My m hummer pmmem x mumv1 Ig274MvuAV Vlesz IIV naA72 u Dciuynlremp cull mcluml 1 701m Ig i imA mm mm JV and n mom Leuzvam 5mm Foroulpullmmnmr v wchme InoK m7 0 sum Mm Wm Kg x m Mia mm mm 1 mf In 01th I 2 Much mm VW 27w Smog vwgnv mcmurocvohageoszu VS IV mm vm2 Lhagalemlum an 11 mm be a I 27x l7xv lhc resmor n x then m Rm m I m 01 For mm 7 Lhasourcevnlugeol u u Vnl7x 411v m mum V 5 men m b l 3 4 Ln 01 m Mammal m e have Kwam Vm 1 nm 2 o swam 11 Much mm vm xsv 10 rm A and la we can wnLe K m gt Ia n m kmvmmmm Emu Since Is iunummemznm 1 Muchyeldml mm Imm R mum M ndilmk HSk Hmh mmNnn are bmcd m lhc mmnninn regmn Much I de ned In Cemme 1 linear umph cn 611 SUMMARY 2 A e design uflmezr amplmees n F H eemmen gate These three cun guratmns farm the basxcbmlmng blacks fur cumplex integrated circuits T1 The euem characteristics quhethree eueunsweee cumpzred m Table 5 1 e and cumplementary cmos devxceswae analyzed END CH 6 EEEZQImmduccnnmElzchunms Thehnnk gnes we swmlmm e Examplzsthatyml shmlld gn nvu39 pp m 7 un 33 BASICTRANSISTORAFPLICATIONS umervarymgsxgqals In m5 semun we cunslderthe switchmgpmpa ues quhebxpulartxznsmur analyze a 31215 331 Switch cutuff and satumhun FigureSAZ An npn bipalar inve ercircu used as a switch Theluad furexzmpla mde be mum ahwmmng dde m sums uther elecmcal device If v ltVuun L 7 Smcexc Wmv m m kamse1ftheluad were ahgutrermmng mm the ugh uulputvmuld be zem wnh zem current a 29 xmqmm Etch1m Ifweletvlvee A L L ll Vhan hm Lhe Lmnslslor ls usually drlvm lnto saturatlon whlch means that Inthscasea ll M lal aw load leml n lo Wlll be modl ed sllghtly when we dlscuss blpolar dlgltal loglc clrcults DeslglP ml r Thls voltage V l go Into breakdown and be damaged llnear Consequleythsmodeofopaatloncannotheusedforllnearampllfla OnLheothahand whlch ls 332 DigimlLugic lll ller Fl HY A a the aanslslor ls ln cutoffand the outputls hlgh and equalto vCC If on the omelhand the Input ls hlgh and equal lo vcc Lhe Lranslslor ls dnven Into samratlon and the output ls low and equal to VCEsaL 5329 lmammmtaEleckmcs l27 Vccisv Figure 343 A bipolar 1a inverter circun and 1b NOR mgm gale A1LL When the two inputs at zero both transistors are cmo and V0 5 v Whenv 5 v and V2 0 Q can be m MchQ n men 39 Vo chsat02 V 39 39 39 1 mmquot 239 Huh A cases I I 39 I I 39 H quot 39 333 Ampli er a dc input voltage Example 312 Objective Deurminethedevoltageu39ansfercharacteds csandthmthe M H Sr 100 VA we VEE0n 07 V and chsat 02V EB 29 Intmducuanta Elenmmcs 122 Forwardacme mode Sntummrt 19 s t V a b Figure 344 13 A bipoiar mverter used as an amptitrer b the invener vettage transter charactenslics no Solutio r t 7 Q is cul 0T lnd my 5 v For 139 gt 17 v Q mm an and n biased in the active region m that I 7 139 I39 on 7 It 2 The output ultnge is rquot lquot r RA Iquot fi Rr um e is 74w 39nm equkmun i5 Valid t39ttr n 2 07V and r0 2 1 n 102V 39l ltc inpul ulluge t ttr tu2v 15 r 13v 39 at r e r xtm or r gt 19 v the transistor r bl u n alur uon and the output voltage is Gunslam at 2 v The Voltage transt er character isttcs are shown In anre 344b AC Solution Now btas the tramtstnr in the center nfthe 39dLl voltage arm 7 v e 13 v Also Include u stcond Input v0 we rcgtun with an input lag source denoted an Av a The dc output vultage ts 21 V whtch is the Qpninl urthe tramistnr in Ergnre 3 EB 29 Inuanhcuantalilecuamcs 129 Qpovn 2 v m Tm FigureaAS 1a The Inverter circuilwnh mm a dc and an ac input signal 0 1h 39 39 39 and in nidal39 1 h I 5 dc wings on e dc masmg rpmm ransler characteristics showing xmpmper me Figure 3450 0 511 lhul the base auxrum IS A 7 I Ar Van 13 0 7 Ar 12 mu m whcru he BrE voltage is insulind lo bu uunslunl u 07 V The uulpul vullugu 15 Va 2 7 ich iaRC whmh um be linen as mmrm Am r 7 4m 274A39 390 100m gt quot The change in 111 uulpul mltage due lo the change in he inpul vullug can be wrillen m Ara 7 4mm The change in mupul voltage par change in input Vollag is the ampli cation Dr A 7 4 Ar EE 329 IntrudumunluEledmmcs Comment As the input voltage changes we move along the voltage transfer characteristics as shown in Figure 335b The negative sign occurs because of the inverting property of the circuit Discussion In this example we have biased the transistor in the center of the active region If the input signal AvI is a sinusoidal lnction as shown in Figure 345b then the output signal Ave is also a sinusoidal signal which is the desired response for an analog circuit This assumes of course that the magnitude of the sinusoidal input signal is not too large If the Qpoint or dc biasing of the transistor were at vI 19 V and v0 02 V as in Figure 345c the output response changes Shown in the gure is a symmetrical sinusoidal input signal When the input sinusoidal signal is on its positive cycle the transistor remains biased in saturation and the output voltage does not change During the negative half of the input signal the transistor becomes biased in the active region so a halfsinusoidal output response is produced Here the output signal is obviously not a replication of the input signal This discussion emphasizes the importance of properly biasing the transistor for analog or ampli er applications The primary objective of this chapter as stated previously is to help readers become familiar with transistor circuits but it is also to enable them to design the dc biasing of transistor circuits that are to be used in analog applications 34 BIPOLAR TRANSISTOR BIASING As mentioned in the previous section in order to create a linear ampli er we must keep the transistor in the forwardactive mode establish a Qpoint near the center of the load line and couple the timevarying input signal to the base The circuit in Figure 345a is impractical for two reasons 1 the signal source is not connected to ground and 2 the dc base current ows through the signal source 341 Single Base Resistor Biasing The circuit shown in Figure 350a is one of the simplest transistor circuits BB 329 Introduction to Electronics 131 CC W Figure350 my hi resismr do equivale Icircuit WW The Wm M M q u F ma by the addxuonal subset th Design Exampe 313 Objecllve Dwgn hc clrulll shunn m hgurc 35mm to yield a guru I md ICLQ Assume hill Vpp 12 V K 100 zmd I39mum 0 W The Qpoinl nlum quot10 ha b 1 7 lmA and my 0 Solunon 39l hr mlleclur rcsmancs um be l uund from Th bans current mm then b ho 1 7 mA 5 7 100 1W 7 2 llmA EE 2 Immdvcnanm Electmmcs and the base rusxsmnce IS ducrmmed m bu 0M7 12417 10M 0mm m Altlnmgh u value 01113 am PM RE will calabliah L11 required buss cur mu his reusmncc 1s loo large m be used in 2111 m39cgraled cu39L39mL acmemgam oflOO y Wm m a M m um new cxrcun are shown m Fxgure 3 51b gures 51 Iransxstalcnalastensuts and had me mm mmnn Exams 5J3 wnen WY7W1 m1th K5n 1mm c1rcu1tthen A L A w 5329 ImammmtaEleckmcs 133 342 Vultzge Divider Biasing and Bias Stability The cxrcun m Fxgure 3 533 15 a classxc mmp 1e of dxscreme Lmnslswrbxasmg Ki q V R a b Figure 353 1a A commonremi er circuit wim an emmer restsmr and voltage divider bias circuit in the base in the dc circuit with a Thevenin equivalent base cimuil resstor RE 15 also added capacltor The coupling cap BCILOF acts as an open clrcu w dc The equwalent Thevemn volmge 15 EB 29 xmmancmh tn Elecfmmcs m V111 RzRi 39i39 mm and he uquivaicnl Thcvcnin resistance is Rm R1 HR Figui u whcrc lhc symbol u indic 5 he pamilci Combination or In my 3 39 A 39 imiiar 53b allows lhc cquivalcnl dc L 5 Wu can scan is rcnil to these wc huvc previomiy considurud Applying KirchhulT s law around lhc B E 100p we nbinin Wu BQRHI 39i VHL 0 luQRL39 336 1139 ha lransislur in biased in he fonmrdraclivc mde lhcn and he base cunan l mm Equalion 336 is V r 1 on RUM1 Ru The coiiuclur cuncnl is lhcn I 7 Cg 5130 338 Vm Va on Rm 439 WRL Example 314 Ohlecnve Amilyzt a Circuit nnng a voltage dander bias one and dclcm n39 1116 Chung in ht Q poinl With a variation in y when the Circuit Contain an emilltr resi L int he Circun given In 11gan 3 533 lei R 7 57in R2712 2km RC 7 2m RE 7 mm rm 10 yawn 07V and 3 100 Solution Usmg he 39I39hmrenin equivalent circuit in Figure 35 n have 1 1mm 7 hHi iu um and V R V 1 mcs aning 111 mainOrr vollugc law cqua ion around lhl 37E loopi wc obtain V 7 yawn 7 179 7 07 Rm 1R 11104 Th culltciorcurrcni Is In 5150 100216i1A Zil mA HQ 7 7 2117M and he emiuer current is I 13IEQ 101x21mm7 21xinA 55329 imamchmta eckamcs 135 The quiescent CrE voltage is then 1qu VCC 7 ICQRC 7 IEQRE 1t 7 2161341181104 4191 V These results show that the transistor is biased in the active region If the current gain of the transistor were to decrease to is 5 150 we Obtain the hittewrng nits 0 or increase to 1 1min i lfatitn VfgofV gt11 559 1 xii gt at Inn 1 i 216 4 x1 ISD I S 7 3 4411 For a 3 1 ratio in t the collector current and collector emitter voltage change by only a 129 1 who Comment The W region using resistor H l F n the loii kilohin range In ontrast single resistor bia requires d resistor in the inegohin range In addition the change in m u change in is has been substanually reduced compared 0 the change shown in i ignre 351 Including an emitter re or RE has tended to sitiliilizt the Qpmnt This niea that including the emitter resistor helps to stabilue the Qpmnl Wllh respect to varia lions in I he d 39gn requirement rer bias sltlhilily lh Riltlt1eku Cole sequently the collector current from Equation 338 beemnes approximate 1 339 Nonnnliy 19 gtgt 1 theierere iiil if z 1 end in 1 tint q a 3411 Now the quiescent collector current is essentially tr rtinetinn or only the de l and the emitter re tanee and the Qrpoinl is slabi39 d 39i sl yttrititteiis Howe er il39 R1 i tee small then R1 and Rs ive power is dis 39 considered bias 7 ttr m dIL ttnd exc muted in these resislmh The general rule is that ti circuit 15 table when R e 1111 t hikL 341 55329 Inkaducuanta enmmcs Design Exam le 315 ohlecuve Deslgn a blas slzlble clrcuil CLJnSldln he Clrcull shown in Figure 35 a 1 V V kwn 107V and 5 120 Choose RE and determine R Circuit is bias slahle and that Vch 3 v m zvr r lmr and R2 such 11ml lhe Design Pointer Typically lhe vehage aeress reg should he on the same errler or magnllude as V glan Larger vellage drops may mean the Supply vallage V has lo be increased in urder lo gel the required voltage across lhe collectoremitter and acress RC T Ten chnusmg a standard value 01151 km for Solution wilh l 120 Cg m IE RL we nd The vellage drop across R is new 132x051 0573 vi which is approximately lhe rlesireil Valuce The base current is round to he I 7 1579 7 l 32 59 3 120 lloiiA Using ihe Thevemh equivalem Clrcuil in Flgure 353m we nd I 7V1 1 H1 9 Rm1 rle as lable circuit R 0 11 mks or Rm 0112151 n17m Thehl 1 110 A are H 36 which viehls V l 747 070 IASV R288 EB 29 Inkanhcuantalilectmmcs 137 whlch yields V 0747 070 145 v Now 7 R2 7 605162 124 R 2252 R R2 whtch yields 12 21 m amt R1 x 5m mm Appendix D we can choose standard restslur values of 1220m and 8 2 M2 Comment The 94 m 39 I L t l in a and the voltage dwider resistors 12 and K have reasonable va range ues m the ktlohm Computer Simulation thare 354 shows the I Sptce circutt schematic wtth the stan tlartl reststor values and wtth a standard mmlstor l mm the Spice ltbrary for the clrcml designed m thls example A 11 anal sts was erfnn ntd and the resulung r W J lt trans ter Qpmnt values are shown The colleetormnitter voltage ts l e of 3V 1 reason for the diflerence Is that the whtch close to the destLrn ralu Ot standard valued reststors are not exactly equal to the tlestgn values Another reason E 329 tntmdueaunm Electmmcs o Figure354 PSpice circun schematic for Example 315 or he shghl dx 39ersncc 15 111211 the e ecuve 5 or the ZNZZZZ n 157 compared to he asaumed alue of 120 BIPOLAR JUNCTION TRANSISTORS NAME MODEL IE c VEE vac VCE VBDEvDO EETADC lV57E02 Rananbawenoted m ch r m Conr L Ithe Luu MM am HOW r 1 Wm be small r 139 E 329 xmmancmn m Elecfmmcs 343 Inmgmmd CircuitBizsing mtegated cn cuxts we would 1 larger surface area than translstors AAymAuanALA v a h mnrmr w andLhecollectorcurrmL B Thevalueof D k A 7 39 39 a 11 nm F HY 5329 ImammmtaEleckmcs Figure 357 Conslamrcurrenl suurce basing We W111 study thxs clrcu m more detml Had semester m EE 429 35 MU39LTISTAGE CIRCUITS apnp m the same cxrcuxt EB 29 Inkamchm m Electxamcs Rel 15 kn sv Figure 355 A mumslage Irmsxslm cvrcu Example 1 Objeclive Culcu 1 1 dc volluges at each nod and me dc cup rcnls through lhc clumcnh in a mullmugu circ 39 For 1h 39irLuil in ngrc 35 I39m each trumusmr 9 Lmumc 1h 1H nunnu mllugc is H V and If 100 Solution The Thevenin equimlsm L39H C il of the has circui of Q is thm in Figure 3 on The arium amen an nodal Ullagh are dclincd as shown The l hsvenin rcmslunue and mung are Rm QM3 lUU SO 333k 2 R1 V39 39 I III RIR3IH unchhorr39s ultuge law equation around the we loop Ur g i And VI39H All a gunnh39rlglkm 75 55329 Inkaducuantalilzckamcs Figure 350 EE 329 IntrudumunluEledmmcs Noung um I 1 5th we lune 15 q 11 211A Therefore 511112111A and 11 113mA Summing 11m currcms a1 1h cullecwr 019 we obmm m 152 In which an be wnuen as 341 Tlen 111 base currcm I can be wrruen m 1enns of 1he ennuer current 1531 an 111110111 V 0 7 I 347 3 1 Jim 171411251 Subslimung Equation 347 11110046 w oblam o 1 3 7 V5 Rm 1 wk wlnch can 13 mm for V5 to y1eld 1m 1 IZmA 11111mA Tn nd 152 we have V53 um ywmn in 432 0 7 11 212W EB 29 Inkanhcuanm Electmmcs The emiuer current 152 is 570213 f 39 mA lt 237 A 100 K 7 1012 3 7 37mA The remaining nodal voltages are Vu I me 119075 3 V 274V and up v 77 R9 7 23715753 Vm7145V We then nd that Z V V 70432 7 72 quot4 and that V553 0213771 45 1 n7 V Comment These regulla 5m um both Q ma Q are hiked m mm mm mod a uriglrally man 110w whm we constcr m ac cpcmlim39 om as an mpuncr in he rexl mme we mu Set 1111 a bcucr desxg39n wrmld mm 2 the vach 0 r39 36 SUMMARY r umummy The three Uermmals are called the base B anme E and collecwr c BoLh npn and pnp Junctions The fourmodes are forward actwe cuwff sammuon and mvase actwe In the forward actwemode collect EE 2 Immdvcnanm Electmmcs same for both npn and pnp transistors as long as the conventional current directions are maintained When a transistor is cut off all currents are zero In the saturation mode the collector current is no longer a function of the base current 3 The dc analysis and the design of dc biasing of bipolar transistor circuits were emphasized in this chapter We continued to use the piecewise linear model of the pn junction in these analyses and designs Techniques to design a transistor circuit with a stable Qpoint were developed 4 Basic applications of the transistor were discussed These include switching currents and voltages digital logic functions and amplifying timevarying signals The amplifying characteristics will be considered in detail in the neXt chapter END Ch 3 BB 329 Introduction to Electronics Carrier At nn we can39t get any net Currant aw wnhm and extremal m the samcunductur are mm D armss asermcunductur as shewn beluw 223 Drift Current and Conductivx Current density AcmZ or CCanSBC the resulting fume un the charge camers accelerates the pusmvely charged hules IN THE SAME states m the ca DIVE Because uf equent culhsmns ufthesepzmcles wnhlamce atums andmmzed impurity atums Lhs eeme accelerauun 15 cunstzndy mtenupted called scattering evants Resulth eeme PM mquot m a 29 macaw Etchinns 3n h atmy given me velunty Va The thermally mun speed ufllghL 21 Thermal Simian Zigizag motion is due to collisions 0r scattering with imperfections in the crysta 0 Net thermal velocity is zero Mean time between collisions is rm 0 lps the remun ufthe electric eld Wemen de ne vr1 quot c which has umts ufdAstznce and szythat allhules a 29 macaw mcmms 1 umt ume Eq 31 I m qpvA end up wnh meI qpv qpIPS Judrz quotInquot 1quot415 Jmfr Jmn Jp 39nfi 75 qn n IPQE carirhcl ivify Of semiconductor is 7 177111 1pth umts Emz n has strange as 29 xmqmm Etch1m 221 Electron and Hole Mobilities v 1 E 39 u has the dimensions ofvE cms g Vcm 7 V 5 Electron and hole mobilities of selected miconductors Si Ge lGaAslInAs 1cmZVvs 1400 3000 8500 30000 1cmZV s 470 1000 400 500 Nuts thaw gtuF m almust all quhe mzjur sermcunducturs vw vanes inversely with the mum uf scattmng taking place mm the sermcundudur Di usinn dimmed sysLEm think uf upmmg aper lme battle m a dused mum FxgureKllpBS a 29 xmqmm mcmms lt I r Law hm h r dnam du have m be present m menu get a dif lsun Currant m a semeenamer w we qumufy Begm wnh Fxnk39s 12W Eq 3 m 3 mm 77 sthe pzmcle as fulluws f qu Vp 1 Eq 3173 b 1 1W qnyn y n m A u A e eachpamcle resultmgm a 29 xmqme Etchinns JN JNidrifI JNidiiT i drift JPtdn39 JPidifl39 mplfg quVP diffusion qunn qDNVn Recmnhina nanmu39z nn semcundumurdsvices semmundudur mtu gear in urdertu resume the cam as in equilibrium values m equilibnumlsvels equilibrium levels ufdiffa39mtmechamsms a 29 macaw Etch1m eqmvalem energy L E Thtrmal E W Photon Entry ngm 039 Ligm W m Ev Lv a Bandrmrbami recombination d BandWham gencrmmn 11mm 7 7 Thtnnnl E nergy uncrgy 7 0 R43 cemcr mamhmmmn c 1143 cam gunman These arelamce as E Where Ttx3p states a 29 xmqmm Etch1m E 15 ED MAMEH mambimm 0 Fame gencmnnn via Impact Iomzauun D D D H cD D 1D5Dsmgy ande trapped c D D D D D D D D whxlethe phunun emssuns a 29 memD mcmms

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