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# DIGITAL LOGIC EE 2740

LSU

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This 10 page Class Notes was uploaded by Kaci Terry on Tuesday October 13, 2015. The Class Notes belongs to EE 2740 at Louisiana State University taught by J. Trahan in Fall. Since its upload, it has received 44 views. For similar materials see /class/223159/ee-2740-louisiana-state-university in Electrical Engineering at Louisiana State University.

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Date Created: 10/13/15

EE 2740 7 HW 3 solutions EE 2740 Homework 3 solutions Fall 2013 1 a Convert 37710 to binary octal and hexadecimal b Convert 001011012 into octal hexadecimal and decimal a 37710 10111 10012 5718 17916 b 001011002 55 lt2D16 45 2 Take the 8 bit 1 s complement and the 8 bit 2 s complement of each of the following binary numbers a 00000100 b 1 1 1 1 101 1 c 001 101 11 d 11 100000 To enhance the readability the answers insert a space between each four bits a 0000 0100 1111 1011 1111 1100 b 1111 1011 00000100 0000 0101 0 00110111 11001000 11001001 d 1110 0000 0001 1111 0010 0000 original 1 s complement 2 s complement 3 Determine the 8 bit sign and magnitude 1 s complement and 2 s complement representations for each of the following decimal numbers 36 84 Note Be sure to represent 36 as a positive number and 84 as a negative number To enhance the readability the answers insert a space between each four bits decimal signed magnitude 1 s complement 2 s complement 36 0010 0100 0010 0100 0010 0100 84 11010100 10101011 10101100 4 Determine the decimal value of the following 8 bit 2 s complement numbers a 1 1 1 1 101 1 b 001 101 1 1 c 1 1 10001 1 a 5 b 55 c 29 EE 2740 7 HW 3 solutions 2 5 Perform the following addition or subtraction of the given numbers using 8 bit 2 s complement representation of the numbers Parts a and b are given in decimal while parts c e are given in 8 bit 2 s complement Indicate in each case whether over ow occurs a 65 72 b 65 72 c 01101100 01010011 d 01101100 01010011 e 11100011 11111001 a 65 10111111 72 w 7 0000 0111 Note discard carry No over ow b 65 65 1011 1111 1721 72 10111000 137 137 1 0111 0111 Yes over ow occurs 0 0110 1100 0101 0011 0001 1001 No over ow Note Could also add 2 s complement of 0101 0011 d 0110 1100 0101 0011 1011 1111 Yes over ow occurs 6 1110 0011 1111 1001 1101 1100 Note discard carry No over ow EE 2740 7 HW2 solutions 1 EE 2740 Homework 2 solutions Fall 2013 1 Demonstrate by means of a truth table that the following identity is correct abbcdcabdc Include in your truth table the columns shown below abcabbcdclabbc clab c a C 2 Convert each of the following expressions into both sum of products and product of sums forms Simplify each expression in these forms a ab cb Ed b f xx 37y Z a ab Cb C d ab b ab C d C b C C d sum of products but not simplified distribution Theorem 12a ab abC d be Theorems 7a 8a 6b ab be absorption Theorem 13a simplified sum of products ba C distribution Theorem 12a simplified product of sums b a xx 37X Z a 3601 Z absorption Theorem 13b a y Z Theorem 16a simplified sum of products In this case this same answer is also simplified product of sums EE 2740 7 HW2 sulutluns gates 3 Implement the following expression using only NOR gates z 25 y z2z The circuit below converts the citcnit above to use only NOR gates NT and NOT 4 a t gt a Wrine g as a mintel39mlisl that is in the form 2m bWline g as a mnmiml snmrofrpl39 Icts cWline g as a rmxterm list that is in the form HM dWrihe g as a mnmiml productrofrsnms ag y by 6 2M01113v7 bg11bc 7 555 1355 5115 11b 0 ga b 6 mm 4 5 6 dgubc 7 11 Ec h cE h EE 3 5 EE 2740 7 HW2 solutions 3 5 Simplify each of the following expressions twice i first using algebraic manipulation and ii second using a 3 Variable Karnaugh map a fxy37372fyi b g 2T37yzfyi ai fxyf37ifyi xy 37 Z combining Theorem 14a 000 30 00 01 11 10 zonnnn 1 man f xy a Z bi g 2737 yz 312quot 377 yZ fyz fyz39 absorption Theorem 13a 3737 yZ 37 y combining Theorem 14a 3737 37 y 32 commutative Theorem 10b 37 32 combining Theorem 14a bii 90 00 01 11 10 z 0 an 1 n g27yz 6 Simplify the following expression using a 4 Variable Karnaugh map fw x y z 2m4 6 7 15 Wx 00 01 11 10 yz 00 01 11 10 f sz39xyz EE 2740 HW 4 solutions EE 2740 Homework 4 solutions Fall 2013 x 00 01 11 10 Z O O 1 O 1 1 1 O 1 O 1 a Does the K map below correspond to XEByGBZ or to XEByGBZ or to something else b Does the K map below correspond to xy63z or xy63z or 3106632 or 3106632 or something else x37 00 01 11 10 z 0 O O O 1 10 O 1 axy z WHO 92 2 Figure 315 depicts the first two stages of a carry lookahead adder where the first stage outputs so and c1 and the second stage outputs 51 and 02 a Write expressions for 52 as a function of x2 y2 02 and for 03 as a function of g2 g1 g0 92 91 90 CO b Draw the next stage of a carry lookahead adder that is the stage that outputs 52 and c3 21 39 391 x0 yo Co 1 50 Figure 315 The rst two stages of c1 carrylookaheud adder EE 2740 7 HW4 salutwns a 52 new2692 5 112 m P217190 17217117050 b EE 2740 HW4 solutions 3 3 Write Verilog code to implement the circuit below using the continuous assignment Note If you assign a value to an intermediate signal say value g for the output of a gate in the middle of the circuit then you must declare it using the Wire primitive as in Wire g module hw43X y Z f input X y Z output f assignf X y z amp X z endmodule 4 a Draw the circuit corresponding to Verilog module hw44a below b Draw the circuit corresponding to Verilog module hw44b below In this drawing represent module hw44a as a box with 3 inputs and 1 output as shown below module hw44aX y z f input X y z output f X f Wire d e V 4a assign d X y amp X Z Z assign f d A Z endmodule module hw44bA B c h input 10 A B input c Wire 10 G output h hw44a boxO A O BO c GOD hw44a boxl Al Bl c Gl hw44a box2 GO Gl c h endmodule EE 2740 HW 4 solutions a 4a b AO x G0 8M y 4a Z c 0 Am x 4 GH B1 V 4a EE 27407HW4SOZLMLOYLS 5 5 Conslder the ruhetmh g a 175 ab Use the truth table to derlve a shunt forf that uses a 24071 muluplexer ul rtorl of the muluplexer and the expresslon 1 for the 1 lhput of the muluplexer a b t m g 1 Altemauvely usmg b as the select lhput results lh a shunt Wlth a for the o lhput and a are the 1 lhput oh uslhg c as the select lhput results lh a shunt Wlth a b for the o lhput and a for the 1 lhput

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