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by: Kaci Terry


Kaci Terry
GPA 3.95

Gabriel De Souza

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Gabriel De Souza
Class Notes
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This 60 page Class Notes was uploaded by Kaci Terry on Tuesday October 13, 2015. The Class Notes belongs to EE 2731 at Louisiana State University taught by Gabriel De Souza in Fall. Since its upload, it has received 21 views. For similar materials see /class/223162/ee-2731-louisiana-state-university in Electrical Engineering at Louisiana State University.

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Date Created: 10/13/15
Classi cation of Digital Circuits Combinational logic circuits Output depends only on present input Sequential circuits Output depends on present input and present state of the circuit Combinational Logic Design Procedure Start with the problem statement Determine the number of inputs variables and the required number of output variables Derive a truth table that de nes the required relationship between input and output Simplify each output function Karnaugh maps Draw the logic diagram Half Adder Design Example A half adder computes the sum of two one bit Boolean inputs which can be at most 102 This requires two outputs Inputs X and Y Outputs S and C ccgtlt A A lt AOOOO OAAOM Half Adder Design Example CXY SX BY Decoders A decoder is a multipleinput multipleoutput logic circuit that converts coded inputs into coded outputs Where the inputs and outputs codes are different Function Realization With Decoders The outputs of a binary decoder provides 2 minterms for its n inputs and a Boolean functions can be represented as a sum of minterms therefore a decoder and one or more OR gates can be used to realize sums of minterms of 11 variables Multiplexers Combinational logic circuit that selects binary information from one of many input lines and directs it to a single output line The input is selected by the binary value on the select lines Demultiplexers Combinational logic circuit that receives binary information on a single input and sends this information to one of many possible output lines The output is selected by the binary value on the select lines Function Realization With Multiplexers A multiplexer is basically a binary decoder Whose outputs were ORed together and some extra input lines were added to each product term Function Realization With Multiplexers A sum of minterms can be realized by setting the corresponding input line of the chosen minterms to 1 and setting the input lines of the remaining minterms to 0 Transition Time Time interval between two reference points on a waveform These reference points are usually 10 and 90 of the voltage change Rise time t Time interval when waveform is changing from a logic low to a logic high level Fall time t Time interval when waveform is changing from a logic high to a logic low level Propagation Delay Time it takes for a change at the input of a device to produce a change at the output of the same tpLH is the propagation delay when the output changes from LOW to HIGH tpHL is the propagation delay when the output changes from HIGH to LOW pLH and tpHL are not necessarily equal and their values depends on the logic family Propagation Delay and Transition Time INPUT TRANSITION 0 tp LH lt gt p HL 3 V 3 OUTPUT TRANSITION 5 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 U 39 39 39 H 4 V I Fanout The number of gate inputs that a single output can drive or operate Without exceeding its worst case loading speci cations IILMaX is the maximum current supplied by an input when a LOW logic level voltage is applied to that input IIHMaX is the maximum current required by an input When a HIGH logic level voltage is applied to that input IOLMaX is the maximum current into an output When this output is in the LOW state OHMaX is the maximum current provided by an output When this output is in the HIGH state Fanout 1 L 11H I0L Ii I 3910 13 I IIII Low 1 IL HIGH GATE ACTING AS A CURRENT SINK GATE ACTING AS A CURRENT SOURCE Fanout LS fanout IOLI M HS fanout IIOH Iml fanout min LS fanout HS fanout Power Dissipation The power consumed by the gate that must be available from the power supply This does not include the power delivered from another gate VCC supply voltage ICCH current drawn by the circuit when the output of the gate is HIGH ICCL current drawn by the circuit when the output of the gate is LOW ICC average current drawn by the circuit PD average power dissipation Power Dissipation ICCH ICCL CC 2 PD VCC XICC DC Noise Margins The maximum amount of voltage variation noise that may be permitted from LOW or HIGH voltage levels VOHMln the minimum output voltage in the HIGH state VIHMln the minimum input voltage guaranteed to be recognized as a HIGH VILMax the maximum input voltage guaranteed to be recognized as a LOW VOLMax the maximum output voltage in the LOW state DC Noise Margins LOWState VILMax VOLMax 39 HighState VOHMin VIHMin m V V HIGH STATE I DC NOISE MARGIN LOWSTATE DC NOISE MARGIN Unused Inputs Handle them as follows Tie them to a used input in the same gate Tie them to logic 1 through a pullup resistor for AND amp NAND gates Tie them to logic 0 through a pulldown resistor for OR amp NOR gates Vcc 1 Logic 1 Logic 0 mm used inputs VOHmin lt V Ileax I V lt VOLmax unused input 7 R lt VOLmax R lt Vcc VOl lmin IILmax Illlmax Tying an unused input to an used input Pulling down an OR gate Pulling up an AND gate Logic Families Transistor Transistor Logic TTL is one of the most popular and widespread of all logic families Very high number of 81 and MSI devices available in the market Several number of subfamilies that provide a wide range of speed and power consumption Sub families 74xx The original TTL family These devices had a propagation delay of 10ns and a power consumption of 10mW and they were introduced in the early 60 s Logic Families Sub families 74Hxx High speed Speed was improved by reducing the internal resistors Note that this improvement caused an increase in the power consumption 74Lxx Low power Power consumption was improved by increasing the internal resistances and the speed decreased Logic Families Sub families 7 4Sxx Schottky The use of Schottky transistors improved the speed The power dissipation is less than the 74Hxx subfamily 74LSxx Low power Schottky Uses Schottky transistors to improve speed High internal resistances improves power consumption Logic Families Sub families 74ASxx Advanced Schottky Twice as fast as 74Sxx with approximately the same power dissipation 74ALSxx Advanced Low power Schottky Lower power consumption and higher speed than 74LSxx 7 4Fxx Fast Performance is between 74ASxx and 74ALSxx Logic Families Note that parameters like VOHMin VIHMin a VILMax a and VOLMax are all the same for the different subfamilies but parameters like IILMaX IIHMaX IOLMaX and OHMax may differ Most TTL subfamilies have a corresponding 54series military version and these series operate in a Wider temperature and voltage ranges Logic Families Complementary metal oxide semiconductor CMOS replaced TTL devices in the 90 s due to advances in the design of MOS circuits made in mid 80 s Advantages Operate with a Wider range of voltages that any other logic family Has high noise immunity Dissipates very low power at low frequencies It requires an extremely low driving current High fanout Logic Families Disadvantages Power consumption increases with frequency Susceptible to ESD electro static discharges Subfamilies 40xx Original CMOS family Fairly slow but it has a low power dissipation 74HCxx High speed CMOS Better current sinking and sourcing than 40xx It uses voltage supply between 2 and 6 volts Higher voltage gthigher speed Lower voltage gtlower power consumption Logic Families Subfamilies 74HCTxx High speed CMOS TTL compatible Better current sinking and sourcing than 40xx It uses voltage supply of 5V Compatible with TTL family 74ACxx Advanced CMOS Very fast It can source and sink high currents Not TTL compatible 74ACTxx Advanced CMOS TTL compatible Same as 74ACxx but it is compatible with TTL family Logic Families Subfamilies 74FCTxx Fast CMOS TTL compatible It is faster and has lower power dissipation than the 74ACxx and 74ACTxx subfamilies Compatible with TTL family Pre xes usually added to device designation to identify the manufacturer SN Texas Instrument MN Motorola DM National N Signetics P Intel H Harris AMD Advanced Micro Devices Logic Families Pre xes usually added to device designation to identify the manufacturer SN Texas Instrument MN Motorola DM National N Signetics P Intel H Harris AMD Advanced Micro Devices Suf xes identi es the packaging N Plastic DIP dual inline package P Plastic DIP J Ceramic DIP W Ceramic at package D Plastic small outline package Latches and FlipFlops These sequential devices differ in the way their outputs are changed The output of a latch changes independent of a clocking signal The output of a ip op changes at speci c times determined by a clocking signal S R Latch SR latch based on NOR gates The S input sets the Q output to 1 While R reset it to 0 When RSO then the output keeps the previous value When RS1 then QQ O and the latch may go to an unpredictable next state OI 39 SR Latch S R latch based on NAND gates The 8 input sets the Q output to 1 While R reset it to 0 When R S 1 then the output keeps the previous value When R 1 then QQ 1 and the latch may go to an unpredictable next state 6 Figure 2 SR latch D Latch This latch eliminates the problem that occurs in the S R latch when RSO C is an enable input When C1 then the output follows the input D and the latch is said to be open When C0 then the output retains its last value and the latch is said to be closed Figure 3D latch with enable D Latch For proper operation the D input must not change during a time interval around the falling edge of C This time interval is de ned by the setup time setup and the hold time thold stable unstable tsetup thold tsetup thold D C EuanEdictable Q Q follows D W closed open closed open closed Figure 4 Setup and hold times for a D latch Edge Triggered D FlipFlop This ip op is made out of two D latches The rst latch is the master and the second the slave When Ck 0 the master is open and the slave is closed QIn and DS follow DIn When Ck 1 the master is closed the slave is open and QIn is transferred to QS Note that QS does not change because the master latch is closed leaving QIn xed Edge Triggered D FlipFlop D DM QM Ds Qs Q CM Cs Qs Q CK gt gt Figure 5 EdgeTriggered D FlipFlop The same constraints regarding setup and hold time discussed previously also apply to the edge triggered D ip op K Edge Triggered JK FlipFlop The operation of inputs J and K in the JK ip op is similar to the operation of inputs S and R in the S R ip flop The difference arises when J and K are asserted simultaneously In this situation the output of the JK ip op inverts its current state D DL fDJ pOlepLoI 9 plroppp go Figure 6 EdgeTriggered J K FlipFlop T FlipFlop Also known as the toggle ip op When input T 0 the output Q retain its previous value When input T 1 the output Q inverts on every tick of the clock When inputs J and K of a J K ip op are connected together the J K ip op will behave like a T ip op Sequential Logic Design Procedure Derive a stateoutput table from the problem speci cation Minimize the number of states in the stateoutput table by eliminating equivalent states Choose a set of state variables Assign to each state a unique combination from the set derived above Create a transitionoutput table Sequential Logic Design Procedure Choose a ip op type and construct its excitation table Using the excitation table ll the values for the input excitation function columns on the transitionoutput table Derive the excitation and output equations Draw logic diagram Sequence Detector Design Example Design a sequential circuit with one input I and one output Z The output is asserted When the input sequence 011 is received See stateoutput table below In put Output Present State I Next state 2 Init 3 1 mt o o S o o S 0 1 S o o o S o o S 01 1 S 011 0 0 S 011 1 S 011 1 S 011 1 Sequence Detector Design Example Set of state variables and their unique assignment to the different states State Q1 QO Init 0 0 S o 0 1 S 01 1 1 1 0 S011 Sequence Detector Design Example Transitionoutput table Present State Input Next state Output Q 1 Q 0 I Q 1 Q o Z 0 o o o 1 o o o 1 o o o o 1 o o 1 o o 1 1 1 1 o 1 o o 1 o 1 1 o 1 1 o 1 1 1 o o 1 o 1 1 1 1 o o Sequence Detector Design Example See excitation table below Required inputs Present State Next State D J K I T o o o o X o o 1 1 1 X 1 1 o o X 1 1 1 1 1 X o o Sequence Detector Design Example Present State Input Next state Output Input Excitation Q1 Q o I Q1 Q o Z J1 K1 J 0 K o o o o o 1 o o x 1 x o o 1 o o o o x o x o 1 o o 1 o o x x o o 1 1 1 1 o 1 x x o 1 o o 1 o 1 x o o x 1 o 1 1 o 1 x o o x 1 1 o o 1 o x 1 x o 1 1 1 1 o o x o x 1 Equations derived from the table above JIIQ0 K1I Q0 JoI Q1 K0IQ1 Z Q1Q0 Sequence Detector Design Example See the logic diagram for the circuit below I Q0 1 Q0 1 Q1 I Q1 CK D L Q1 D m gt 3Q1 D Q0 13 ltFF0 Open Collector Devices Entire upper half of output circuit is omitted External pullup resistor is needed If any input is low then Q2 and Q3 are cutoff and the voltage Z is high VCC external CSlStOI39 R 3 2 7 R L Ae ye 2 BO Q R 4 3 Open Collector Devices Can be used to drive a load such as LEDs relays or other device It is important to calculate a suitable resistor R The current through the load must not exceed IOLMax Vcc ILED VLED R VCC VLED VOL TYP 1 LED VOL TYPICAL Open Collector Devices Wired AND Logic When two or more opencollector outputs are tied together with an external pull up resistor the circuit behaves as if the gates were connected to an AND gate Open collector output gates Totemltpole output gates Open Collector Devices Common Bus Several open collector outputs may be connected together to create a common bus The decoder in the circuit shown below selects which device outputs to the common bus by sending a high to the open collector output NAND gate connected to the chosen device Vcc Open collector output gates R decoder undue a I S I 00 I I control lines device 3 enable line Open Collector Devices 0 To calculate the pullup resistor of the gure in the next two pages one must consider two cases Only one gate is active and forces the bus voltage to be LOW VOLTyp All gates are disabled forcing the bus voltage to be HIGH VOHMin Open Collector Devices Case When output voltage is VOLTyp 39 IR IOLMax 39 311LMax RMin VCC IR 0 MD ltgt 0 Low D I OL High 10 1 High V OL TYP Low state Open Collector Devices Case when output voltage is VOHMin IR 4IOHMax 3IIHMax RMax VCC 39 VOHMin IR Select RMin S R S RMax Hmdx High state Tri State Devices This kind of device include a third electrical state called high impedance or Hi Z This new state is controlled by an input control line called output enable When this input is asserted the device behaves like a normal gate otherwise the output behaves like an open circuit C39 A Y o o 1 o 1 o 1 o HiZ 1 1 HiZ Tri State Devices TriState Devices One application of tristate devices is to be used to connect several devices to a single bus When changing which output is connected to bus one must ensure that all outputs must rst go into the hiZ state thus avoiding the possibility that two outputs would be connected to the bus simultaneously opencollector oulpm gates Bus three state output gates device 0 device decoder 0 device 1 0 0 device 2 0 LON G device 2 control lines control lines device 3 output enable line enable line Schmitt Trigger Gates Used for waveshaping purposes Level sensitive with output switching state at two distinct trigger levels called lower trigger level VT and upper trigger level VT The difference between the two trigger levels is called hysteresis VT 39 VT Shown below is the inputoutput transfer characteristic Output voltage 50 L Input voltage 00 I l I VT vT 50 Schmitt Trigger Gates Transforming an analog input signal into a clean square form signal Input signal VT VT time Output sig ial High time


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