Digital Electronics EE 231
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This 4 page Class Notes was uploaded by Ms. Isobel Rau on Thursday October 15, 2015. The Class Notes belongs to EE 231 at New Mexico Institute of Mining and Technology taught by William Rison in Fall. Since its upload, it has received 9 views. For similar materials see /class/223646/ee-231-new-mexico-institute-of-mining-and-technology in Electrical Engineering at New Mexico Institute of Mining and Technology.
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Date Created: 10/15/15
EE 231L Fall 2006 EE 231L Using AHDL to Design State Machines Finite state machine is another name for sequential circuits A two bit up down counter can be described as a state machine with one input and two outputs There are many ways to design state machines using AHDL Here are one design for the two bit up down counter SUBDESIGN twobit count 1 O OUTPUT c l o ck INPUT up INPUT VARIABLE ss MACHINE WITH STATESsO 1 52 SS BEGIN ssclk clock 70 Specify the clock for the state machine 70 CASE 55 IS WHEN SO gt count BquotOOquot IF u 1 THEN ss 1 ELSE ss SS END IF WHEN 51 gt count Bquot01quot IF up 1 THEN ss 2 ELSE ss sO END IF WHEN 52 gt EE 231L Fall 2006 count Bquot10quot IF up 1 THEN ss 3 ELSE ss sl END IF count Bquot11quot IF up 1 THEN ss sO ELSE ss 2 END IF END CASE END The two bit up down counter is a Moore machine 7 ie7 the outputs of the machine depend only on the current state7 and not on the current input You can design a Moore machine by speci ng a bit pattern associated with each state In this example7 we use a state transition table rather than a CASE statement The count 1 0 outputs are directly associated with bits of the state machine This means that the count 1 0 outputs will be the outputs of ip ops7 and will not change value until the machine changes states SUBDESIGN twobit count 1 O OUTPUT clock INPUT up INPUT VARIABLE ss MACHINE OF BITS count10 WITH STATESsO BquotOOquot 1 Bquot01quot 2 Bquot10quot 3 Bquot11quot BEGIN ssclk clock Z Specify the clock for the state machine Z TABLE Z current current next Z Z state input state Z ss up gt ss 50 1 gt 1 1 1 gt 52 2 1 gt 53 SS 1 gt so so 0 gt 3 sl 0 gt 50 2 0 gt 51 3 0 gt 52 END TABLE END EE 231L Fall 2006 You can use AHDL to design state machines with asynchronous outputs7 also called Mealy machines Here is an example from your textbook Ref wlz0 W0z0 C wlzl w0z0 Here is an AHDL le to implement the design This example shows how to reset a state machine When reset goes high7 the machine will be reset to the rst state in the state machine list in this case7 that will be state A The reset is done using the clrn and prn inputs to D ip ops7 so the reset is done as soon as reset goes high it is not necessary to wait for a clock edge When in state E7 the output will be 0 when the input is 07 and the output will be 1 when the input is 1 The output will change multiple times While in state B if the input changes multiple times For a Moore machine7 the output changes only when the machine switches from one state to another SUBDESIGN mealy clock INPUT reset INPUT w INPUT 2 OUTPUT VARIABLE ss MACHINE WITH STATESA B BEGIN ssclk clock Z Specify the clock for the state machine Z ssreset reset Z Specify the reset for the state machine Z CASE ss IS WHEN A gt if w GND THEN z GND ss A else 2 GND ss B END IF WHEN B gt if w 1 THEN z Bquot1quot ss B EE 231L else Z Bnon END IF END CASE END Fan 2006 Here is the same system designed using a state transition table SUBDESIGN mealy clock INPUT reset INPUT w INPUT 2 OUTPUT VARIABLE ss MACHINE WITH STATESA B BEGIN ssclk clock ssreset reset TABLE Z current current current Z state input output ss w gt 2 A 0 gt 0 A 1 gt 0 B 0 gt 0 B 1 gt 1 END TABLE END Z Specify the clock for the state machine Z Z Specify the reset for the state machine Z next Z state Z ss A B A B 1 Note that this just describes in a table what the state diagram described in a gure
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