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Concepts and Facilities of Operating Systems for Computer Scientists

by: Jaden Jakubowski

Concepts and Facilities of Operating Systems for Computer Scientists CSC 246

Marketplace > North Carolina State University > ComputerScienence > CSC 246 > Concepts and Facilities of Operating Systems for Computer Scientists
Jaden Jakubowski
GPA 3.94


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Class Notes
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This 10 page Class Notes was uploaded by Jaden Jakubowski on Thursday October 15, 2015. The Class Notes belongs to CSC 246 at North Carolina State University taught by Staff in Fall. Since its upload, it has received 17 views. For similar materials see /class/223821/csc-246-north-carolina-state-university in ComputerScienence at North Carolina State University.

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Date Created: 10/15/15
The Pentium Architecture October 9 656201 Sec rion 002 Fall 2000 Basics Almos r 350 differen r ins rruc rions Backwards compa ribili ry wi rh The first 8086 processor Twoaddress ins rruc rion forma r Operands can be regis rers or memory NOT a loadstore archi rec rure CSC201 Secfion Copyrighf 2000 Douglas Reeves 00 Fall 7000 Basics cont Regis rer sizes 8bi r 16bi r and 32 bi r Very flexible addressing modes Permi r red ins rruc rionltgtaddress mode combina rions irregular lo rs of special cases hard To learn Condi rion codes such as ZF and SF Kep r in a special r egiS l39er EFLAGS Effec r by each ins rruc rion is somewha r complex irregular CSC201 Secfion Copyrighl 2000 Douglas Reeves 00 Fall 7000 Registers 1 EAX 1 l1 AX 1 4 4 1 EBX 1 l1 BX 1 W4 1 e ECX 1 I1 cx 1 w 1 1 EDX 1 l1 DX 1 WI 1L4 EBP 1 1 BP 1 1 ESP 1 l1 SP 1 1 ESI 1 1 5 1 1 EDI 1 1 DI 1 CSC201 Secfion Copyrighf 2000 Douglas Reeves 00 Fall 7000 Registers 4 main 32bi r general purpose regis rers EAX EBX ECX EDX Goal for regis rer use minimize The need To read from wri re To memory Would be a lo r easier wi rh more GPRs Each GPR can be spli r can refer To The leos r significon r 16 bi rs AX BX CX DX Each 16bit regis rer can be spli r can refer To upper and lower half AH AL BH BL CH CL DH CL 4 o rher 32bit general purpose regis rers EBP ESP ESI EDI CSC201 Sec l ion Copyrighf 2000 Douglas Reeves 00 Fall 7000 RegisTers ConT Each of These can be spIiT can refer To leasT significanT 16 biTs BP SP SI DI Specific insTrucTions may imiT which regisTers can be used for which purpose In some cases The regisTer is impliciT Makes The i nsTrucTion encoding and hardware implemenTaTion more efficienT Makes programming more difficulT EFLAGS is a 32biT special purpose regisTer SegmenT regisTers noT used CS DS ES FS GS SS CSC201 Secfion CopyrighT 2000 Douglas Reeves 00 Fall 7000 Pen39rium Memory Model quotFlafquot model every address is 32bifs Any of 4 billion by res of memory can be specified quotSegmenfedquot model each address is 16 bifs Used by early x86 processors To reduce ins rrucfion size 216 64KB of memory way foo small Add To a segmenf regisfer base address To specify a 64KB region in memory Can access much larger overall memory Only 64KB for a specific segmenf regisfer value CSC201 Section Copyrighf 2000 Douglas Reeves 7 00 Fall 7000 Segmented Memory Address Computation 16bit offset in inst 39uction 20bit segment register 20bit effective address CSC201 Secfion Copyrighf 2000 Douglas Reeves 00 Fall 7000 Addressing Mode Examples Immedia re mov eax OOOOffa3h Regis rer39 mov eax ecx Memory Dir39ec r mov eax var1 Regis rer39 Indirect lea ebx var1 mov eax ebx Al rer39na rively leaebx var1 mov eax dword ptr ebx By re p rr39quot also possible CSC201 Secfion Copyrighf 2000 Douglas Reeves 00 Fall 7000 Examples Cont Base Displacement lea ebx myarray mov eax 16ebx Al rer39na rively lea ebx myarray mov eax ebx16 BasedIndexed lea ebx myarray mov ecx 16 mov eax ecxebx Memory Indir39ec r none PC Rela rive jmp labelnottoofaraway CSC201 Section Copyrighf 2000 Douglas Reeves 10 00 Fall 7000


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