VLSI Systems Design
VLSI Systems Design ECE 546
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This 6 page Class Notes was uploaded by Miracle Jaskolski on Thursday October 15, 2015. The Class Notes belongs to ECE 546 at North Carolina State University taught by William Davis in Fall. Since its upload, it has received 21 views. For similar materials see /class/223891/ece-546-north-carolina-state-university in ELECTRICAL AND COMPUTER ENGINEERING at North Carolina State University.
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Date Created: 10/15/15
Announcements ECE 546 VLSI Systems Design Lecture 5 Latchup Analytical Transient Inverter Sizing Fall 2008 W Rhett Davis NC State University with signi cant material from Rabaey Chandrakasan and Nikoli W Rhett Davis NC State University Slide 1 ECE 546 Fall 2008 o HW2 Due Tuesday 0 Video Lecture next Tuesday See the link to the video on the schedule Harun Demircioglu and Chanyoun Won will be in class to go overthe slides and examples from the lecture W Rhett Davis NC State University Slide 2 ECE 546 Fall 2008 Summary of Last Lecture Today s Lecture o What are the five capacitances for a MOSFET and how can we calculate them 0 How do you extract As AD PS amp PD values from the layout W Rhett Davis NC State University Slide 3 ECE 546 Fall 2008 gt o Latchup 333 0 Analytical Transient 54 541 o Inverter Sizing 543 W Rhett Davis NC State University Slide 4 ECE 546 Fall 2008 Why are well contacts necessary CMOS Latchup VDD Vim RMquot mm J WP quoti P Uf Him 9 39 m RM R 39 nmurcz m psubsimc km E Origin of laichup b Equivalcnl circuit Caused by parasitic BJTs in positive feedback High currents can burn out a transistor Primary way to revent this is to minimize RnweH amp R mg by putting substrate contacts close to source contac s W Rhat Davis NC State University Sllde5 ECE 546 Fall 2009 W Rhett Davis NO StateUnlverslty Slldes ECE 546 FaIIZOOE I What We W111 Requlre 1n Our Class Today 5 Lecture o Latchup is much less of a problem in today s processes 0 Still see a lot of overdesigned layout with overkill in substrate contacts doesn t hurt but might waste area 0 I will require one well contact per active area w Rhett Davis No State Univerle Sllde7 ECE 546 Fall 2009 o Latchup 333 gt 0 Analytical Transient 54 541 o Inverter Sizing 543 wRhettDavus No smeumversity SIIdeE ECESAG Faiizooa Analytical Transient Parasitic Capacitances Vout 0 Need to get circuit in the form of tpReqCL o Follows example 54 in text W Rhett Davis NC State University Slide 9 ECE 546 Fall 2008 W Rhett Davis NC State University Slide 10 ECE 546 Fall 2008 Computing Parasitic Capacitances Which Capacitances Matter Cutoff Resistive Saturation CDB Keq AD Cj Keqsvv PD stvv CSB Keq As Cj Keqsvv Ps stvv W Rhett Davis NC State University Slide 11 ECE 546 Fall 2008 M4 CGD34 M3 o Are there any others W Rhett Davis NC State University Slide 12 ECE 546 Fall 2008 Simplifications 1 Assume parallel capacitors can be added into one capacitor Allows usto combine CGD amp CGD2 2 Assume that a capacitor tied to VDD is equivalent to a capacitor tied to GND if you work through the differential equation you ll find that this doesn t change the value of tp Allows usto combine CD8 amp CDE32 W Rhett Davis NC State University Slide 13 ECE 546 Fall 2008 Simplifications 3 Assume that second inverter doesn t switch and Vout of second inverter is effectively GND Allows us to combine 0683 0683 amp Gem into 063 Allows us to combine 0684 0654 amp COD4 into CG 4 Assume CG3 CG4 COXWL 200W Technically one transistor will be in cutoff and the other in saturation so there will be a difference of COXWL and 23COXWL but this is complicated and the error from ignoring it small W Rhett Davis NC State University Slide 14 ECE 546 Fall 2008 Simplifications 5 Use Miller Effect for CGD1amp CGD2 C U E II 1AC o A gain 0 Assume A 1 0 Therefore CGD1 referenced to GND is 20GD1 W Rhett Davis NC State University Slide 15 ECE 546 Fall 2008 Summary of Simplifications VDD gt COW M4 M2 C3D34 Vin Vout M3 m1 CL T GND T 39 CL 2 CGD12 CDB12 C034 W Rhett Davis NC State University Slide 16 ECE 546 Fall 2008 Tabulation of Results Capacitance Formula HL vs LH 2 CGID1 2 COnW1 same 2 C002 CDBl CDBZ C63 C64 W Rhett Davis NC State University Slide 17 ECE 546 Fall 2008 Today s Lecture 0 Latchup 333 0 Analytical Transient 54 541 gt o Inverter Sizing 543 NC State University Slide 18 ECE 546 Fall 2008 Inverter Sizing NMOS PMOS ratio in 250 nm x 10 M 3 l l x101 36 for fixed load tPLH tPHL O B 4 5 t g 4 P o ThlS curve Selfeloading effect 3 for 025 Mm Intrinsic capacitances dominate 35 W Rhett Davis NC State University Slide 19 ECE 546 Fall 2008 l5 2 2 5 3 3 5 4 4 5 B mIn tp equal tp wRhettDavis NC State University Slide 20 ECE 546 Fall 2008 NMOS PMOS ratio in 45 nm Delay Beta ip 0 Our process th Min tp for 39 5 JP W PLH 2393 Equal tp for 75p T h V l l l l l l to 15 20 25 30 35 40 45 50 Bet Which Sizing is Better o Sizing for min tp sizing for min avg delay 0 Sizing for equal tp sizing for min worst case delay 0 Which is better Why min tp equal tp W Rhett Davis NC State University Slide 21 ECE 546 Fall 2008 W Rhett Davis NC State University Slide 22 ECE 546 Fall 2008 o Learned how to extract AS AD PS amp PD values from the layout 0 Learned how to compute the effective load capacitance CL for an inverter loaded with an identical inverter 0 Learned how to choose 3 WpWn for a single Inverter Min tp for B15 Equal tp for B35 W Rhett Davis NC State University Slide 23 ECE 546 Fall 2008