VLSI Systems Design
VLSI Systems Design ECE 546
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This 13 page Class Notes was uploaded by Miracle Jaskolski on Thursday October 15, 2015. The Class Notes belongs to ECE 546 at North Carolina State University taught by William Davis in Fall. Since its upload, it has received 119 views. For similar materials see /class/223891/ece-546-north-carolina-state-university in ELECTRICAL AND COMPUTER ENGINEERING at North Carolina State University.
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Date Created: 10/15/15
ECE 546 VLSI Systems Design Lecture 18 SRAM Peripheral Circuitry DRAM Fall 2008 W Rhett Davis NC State University with significant material from Rabaey Chandrakasan and Nikoli W Rhett Davis NC State University Slide 1 ECE 546 Fall 2008 Announcements o HW7 Due Today 0 Project Milestone 1 Due in 1 Week 0 HW8 Due in 1 week W Rhett Davis NC State University Slide 2 ECE 546 Fall 2008 Summary of Last Lecture 0 Assuming that the bitlines are precharged to VDD what constraints must you satisfy in an SRAM cell to avoid a readupset o What constrainst must you satisfy to guarantee a successful write 0 Do the bitlines have to be precharged to VDD W Rhett Davis NC State University Slide 3 ECE 546 Fall 2008 Today s Lecture gt o SRAM Peripheral Circuitry Row Decoders Column Decoders and Multiplexers Bitline Conditioning 0 Dynamic RandomAccess Memories DRAM W Rhett Davis NC State University Slide 4 ECE 546 Fall 2008 A More Complete View of an SRAM Wordlines Bitline Conditioning Bitlines 4 Bitcell Array Row Decoder Address Lines K oumn Multiplexers Column D d Drivers amp eco er Sense Amps Data Lines w Rhett Davis Nc State University Slide 5 ECE 546 Fall 2008 Row Decoders Collection of 2quotquot complex logic gates Organized in regular and dense fashion NAND Decoder WLO A0A1A2A1A4ASA6A7A8A9 WL511 A0A1A2A3A4A5A6A7A8A9 NOR Decoder WLO AO A1A2 A3 A4 A5 A6 A7 A8 A9 WL511 A011121212131Z1412151216121712181219 W Rhett Davis NC State University Slide 6 ECE 546 Fall 2008 Traditional Decoder WLO WL1 A0 A1 A2 A3 0 What problems will this circuit have for a large number of address lines o What can we do to mitigate these problems W Rhett Davis NC State University Slide 7 ECE 546 Fall 2008 Hierarchical Decoders Multistage implementation improves performance NAND decoder using 2input predecoders W Rhett Davis NC State University Slide 8 ECE 546 Fall 2008 Dynamic Decoders Precharge devices 6 D G D JEl J11 WLS um 3 L Jr 1quotquot T1 WLZ IE WL1 MII 11 1quot 11 1 Mo WLo V00 A0 1 0 A1 11 A0 E0 A1 1 2input NOR decoder 2input NAND decoder 0 Assuming K address lines how many transistors does each decoder have 0 What are the advantages disadvantages of each architecture 0 What does this structure remind you of W Rhett Davis NC State University Slide 9 ECE 546 Fall 2008 Passtransistor column decoder amp MUX 5L0 BL1 BL2 BL3 AD LI Multiplexer Decoder Driver 0 Column Decoder must be bidirectional to allow reading writing by senseamps line drivers 0 Assuming a NORtype dynamic decoder w K address lines how many transistors does the column decoder have W Rhett Davis NC State University Slide 10 ECE 546 Fall 2008 4to1 tree column decoder amp MUX o For K address lines how many transistors does this structure need 3L0 BL1BL2 BL3 o How does the delay scale with K Driver 0 How can we improve the performance W Rhett Davis NC State University Slide 11 ECE 546 Fall 2008 PreDecoded Column Decoder amp MUX An S l SI IIJ l IlJ l IH S l 1il39 A 33 Fl il LI I39 l 391 l 3917 E2 I J A2 I1 I Fl l Dr er W Rhett Davis NC State University Slide 12 ECE 546 Fall 2008 Bitline Conditioning Options 0 Clocked PMOS o NMOS Faster precharge Faster sensing large noise margin Smaller noise margin VDD VDD P BL BL BL BL o E ualizer PseudoNMOS q NO Clock Signal Better noise margin Fast rechar e More static 390 g VDD VDD ampsensing power FT t3 BL T E BL BL W Rhett Davis NC State University Slide 13 ECE 546 Fall 2008 Today s Lecture 0 SRAM Peripheral Circuitry Row Decoders Column Decoders and Multiplexers Bitline Conditioning gt 0 Dynamic RandomAccess Memories DRAM W Rhett Davis NC State University Slide 14 ECE 546 Fall 2008 3Transist0r DRAM Cell M3 RWL T RWL i J WWL M X X VDDZ V CS M2 T 8L1 VD L BL2 Vpszr DV No constraints on device ratios Reads are nondestructive Value stored at node X when writing a 1 VWWLVTquot W Rhett Davis NC State University Slide 15 ECE 546 Fall 2008 3TD7RAM Layout BL2 BL1 GND W Rhett Davis NC State University Slide 16 ECE 546 Fall 2008 1Transist0r DRAM Cell Write 1 Read 1 WL X GND VDDVTT VDD I BL Von2 C Von2 sensing Write C5 is charged or discharged by asserting WL and BL Read Charge redistribution takes places between bit line and storage capacitance Voltage swing is small typically around 250 mV W Rhett Davis NC State University Slide 17 ECE 546 Fall 2008 Sense Amp Operation VBL V1 VPRE IAVU V0 lSense amp activated 2 Word line activated o What are the key differences between 1T and 3T DRAMs W Rhett Davis NC State University Slide 18 ECE 546 Fall 2008 BitLine Swing 0 Terms of interest CBL Total capacitance on the BitLine CS Storage capacitance Vbit Voltage across CS Vlore Precharge voltage on BitLine 0 Remember that QCV 0 Find AV in terms of CBL CS Vbit and Vlore W Rhett Davis NC State University Slide 19 ECE 546 Fall 2008 DRAM Robustness o How should Vbit and Vlore be chosen to maximize AV 0 Charge Transfer Ratio CSCBLCS Usually kept to 1 10 Why not smaller 0 Why notjust make both CS and CBL very small What limits us W Rhett Davis NC State University Slide 20 ECE 546 Fall 2008 Alphaparticles Soft Errors or particle WL BL o 1 Particle 2 Million electronhole pairs 0 Critical Charge QC 2x106e39Collection Efficiency e39 Electron Charge Collection Efficiency 10 for a 64Mbit DRAM QC 30 fC o VbitCS must be large enough to handle soft error of 10C W Rhett Davis NC State University Slide 21 ECE 546 Fall 2008 1T DRAM Cell Capacitor Sio2 Id OXide Diffused bit line Poly lnverSIon layer Induced by Polysilicon Polysrllcon plate bias gate plate Crosssection Layout Uses PolysiliconDiffusion Capacitance Expensive in Area W Rhett Davis NC State University Slide 22 ECE 546 Fall 2008 SEM of polydiffusion capacitor 1TDRAM W Rhett Davis NC State University Slide 23 ECE 546 Fall 2008 Advanced 1T DRAM Cells mmmwgom quot9 Ce plate Capacltor dielectric layer Cell Plate Si V i f 4 07 l 615 Transfer gate lsolauon Capacitor Insu Re llmg Paly Storage electrode Storage Node I Si Substrate 2nd Field Oxide Trench Cell Stackedcapacitor Cell W Rhett Davis NC State University Slide 24 ECE 546 Fall 2008 Summary o Decoders NOR type faster more power NAND type slower lower power Combine dynamic amp tree decoders for optimum performance 0 In a DRAM Choose CS CBL Vb and Vpre to maximize AV Ensure that VbitCS is largerthan the critical charge to avoid soft errors W Rhett Davis NC State University Slide 25 ECE 546 Fall 2008
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