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# VLSI Systems Design ECE 546

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This 31 page Class Notes was uploaded by Miracle Jaskolski on Thursday October 15, 2015. The Class Notes belongs to ECE 546 at North Carolina State University taught by Staff in Fall. Since its upload, it has received 23 views. For similar materials see /class/223908/ece-546-north-carolina-state-university in ELECTRICAL AND COMPUTER ENGINEERING at North Carolina State University.

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Date Created: 10/15/15

Announcements ECE 546 VLSI Systems Design Lecture 3 Energy Power and Quality Metrics Fall 2008 W Rhett Davis NC State University with signi cant material from Rabaey Chandrakasan and Nikoli W Rhett Davis NC State University Slide 1 ECE 546 Fall 2008 o HW1 Due Tuesday 0 TA Office hours 1014 E82 1240240pm Mon Wed Fri W Rhett Davis NC State University Slide 2 ECE 546 Fall 2008 Summary of Last Lecture Today s Lecture o How do we define VOLVOHVM VIL and VIH o What effect does transistor width have on VM 0 Explain in simple terms how to calculate Req and propagation delay tp W Rhett Davis NC State University Slide 3 ECE 546 Fall 2008 gt o Propagation Delay Rise amp Fall Times 542 0 Dynamic Power 551 0 Quality Measures PDP amp EDP 553 o ShortCircuit Power 551 0 Static Power 552 W Rhett Davis NC State University Slide 4 ECE 546 Fall 2008 Inverter Transient Response The Transistor as a Switch 2 5 2 A i 5 3 gt 1 tPHL tpLH 0 5 0 70 0 0 5 1 5 2 2 5 t sec X wrer W Rhett Davis NC State University Slide 5 ECE 546 Fall 2008 w Rhett Davis dullquot W W S Iiln limit 39ili quotMm IiIuh ll lnl llwm w RUN V63 2 VT I VDD2 VDD a NC State University V E DD VDD2 2 10 14 st VDD Wm 4002st VDD Slide 6 ECE 546 Fall 2008 Propagation Delay Vout R f C Vout eqn I L it Van I Vanegm VDD 2 e7agl1 2 w Rhett Davis NC State University Slide 7 ECE 546 Fall 2008 Rise and Fall Times 0 Usually measured as the 1090 times VVhy Vout Why do we not recalculate Req 7 VDDe ew 01VDD 7 VDDe ew 09VDD I w Rhett Davis NC State University 09VDD 7 01VDD 7 Slide 8 Fall 2008 RON R How to Make A Gate Faster 1 Today s Lecture V min W V D k fVGS 7 VT Vmin 7 w Rhett Davis VDD VDD 2 eq 2 IDVDS VDDgt VGS VDD IDVDS VDD 2gtVGS VDD 2 Jam VDS minVGS V V V 7 DS DSAT 2m 0691qu o Propagation Delay Rise amp Fall Times 542 gt 0 Dynamic Power551 0 Quality Measures PDP amp EDP 553 o ShortCircuit Power 551 0 Static Power 552 NC State University Slide 9 ECE 546 Fall 2008 W Rhett Davis NC State University Slide 10 ECE 546 Fall 2008 Energy and Power Energy amp Power 0 How to find the Energy dissipated in an HOW much energy is stored 0 capacitor inverter VDD E All Power comes from the supply voltage l vmm C How much energy comes from supply T V0 CL VDD Ind15 EIVM EQ 541 i t T 0 Half of energy delivered is stored on capacitor Em Where did the rest go V What happens on I CL HL tranSItion T What is the energy per switching event EQ 540 v E W Rhett Davis NC State University Slide 11 ECE 546 Fall 2008 w Rhett Davis NC State University Slide 12 ECE 546 Fall 2008 Dynamic Power Dissipation Energytransition CL V 2 Power Energytransition fCL V 2 f 0 Not a function oftransistor sizes 0 How to reduce power of a gate W Rhett Davis NC State University Slide 13 ECE 546 Fall 2008 Node Transition Activity and Power ilill Consider switching a CMOS gate forNclock cycles EN CLond20nN EN the energy consumed forNcluck cycles nN the number of 07gt1 transition in N clock cycles E 7 N 7 nN 2 PavgeNlinoO Trclk 7NlinoO N OCLond rdk nN on 11m 0 1 Ngtoo W Rhett Davis NC State University Slide 14 ECE 546 Fall 2008 Today s Lecture Quality Measures o Propagation Delay Rise amp Fall Times 542 0 Dynamic Power 551 gt 0 Quality Measures PDP amp EDP 553 o ShortCircuit Power 551 0 Static Power 552 W Rhett Davis NC State University Slide 15 ECE 546 Fall 2008 0 Power Delay Product PDP Pavgtp in general assume oc0105 and fck1ltp PDP CLVDD22 ESWZ Lower PDP means lowerpower technology I How to lower PDP What happens to delay as PDP is lowered W Rhett Davis NC State University Slide 16 ECE 546 Fall 2008 Quality Measures Today s Lecture 0 Energy Delay Product EDP PDP ktp A measure that shows when supply scaling no longer pays off o Propagation Delay Rise amp Fall Times 542 0 Dynamic Power 551 0 Quality Measures PDP amp EDP 553 NW vltvgt gt o ShortCircuit Power551 in025iim 0 Static Power 552 W Rhett Davis NC State University Slide 17 ECE 546 Fall 2008 W Rhett Davis NC State University Slide 18 ECE 546 Fall 2008 Power The Whole Story Short Circuit Direct Path Current 0 Dynamic Power Consumption C d b o ause non Charging and Discharging CapaCItors w ut zero risef2 time I TcL of input 0 Short Circuit Direct Path Currents 0 P0Wergoes Short Circuit Path between Supply Rails Shrggfyt zgrpound during Switching Ipeak m getting wasted 39 IVDDmA 0 Does peak depend Leakage on the transition t39 Leaking diodes and transistors I 3 lme viv W Rhett Davis NC State University Slide 19 ECE 546 Fall 2008 W Rhett Davis NC State University Slide 20 ECE 546 Fall 2008 What affects Ipeak Predicting ESC from tr it tf o If you know Ipeak you can predict ESC for any transition time I l Era VDD PM SC V VDDVT quot 1 VT for either HL or i i LH transition 3980 V 72V I where ISCX time VD 0g For a larger transition time is ESC larger or smaller W Rhett Davis NC State University Slide 21 ECE 546 Fall 2008 o WL ratios of transistors 0 Load Capacitance Output risefall time why Fig 5 31 marlmm wrrm W Rhett Davis NC State University Slide 22 ECE 546 Fall 2008 How to keep directpath current low 0 Short circuit current goes to zero if tf gtgt tr 0 Plot shows how total power dissipation asymptotically approaches dynamic power as CL increases 0 Can t dothis for cascade logic W Rhett Davis NC State University Slide 23 ECE 546 Fall 2008 Minimizing Short Circuit Current Vdd 15 l 2 3 6 tant 0 Keep the input and output risefall times the same lt 10 of Total Consumption from Vundrickaal IEEE Journal a SolidState Circuits August 1984 I If Vddlt Vm le then shm lecircuit power can be eliminated W Rhett Davis NC State University Slide 24 ECE 546 Fall 2008 Today s Lecture 0 Propagation Delay Rise amp Fall Times 542 0 Dynamic Power 551 0 Quality Measures PDP amp EDP 553 o ShortCircuit Power 551 gt 0 Static Power 552 w Rhett Davis Mc sme university Slide25 ECE 546 Fall 2009 Leakage Vd d Vout Drain Junction Leakage SubThreshold Subthreshold current one of most compelling issues in lowenergy circuit design wRhettDavrs Nc smeumversity simezs ECESAG Faiizooa Reverse Bias Diode Leakage IanSxA 0 JS 10100 pAum2 at 25 deg C for 025 pm CMOS 0 JS doubles for every 9 deg C w Rhett Davis Mc sme university Slide27 ECE 546 Fall 2009 Subthreshold Leakage Most technology vendors offertwo or more thresholds View highspeed HS 5 lowpower L P V55 391 Which is which on plot I SSubthreshold m n az u navg9vns u u n Slope Similar for all devices on the same chip 100 mVdecade in our technology Leakage control is critical for lowvollage opeiation wRhettDavrs Nc smeumversity SlideZE ECESAG Faiizooa Subthreshold Example 514 Controling Threshold Voltage 0 Given a device with a certain leakage VT 05 v Ioff 1011 A S 100 mVdecade 0 Find lOff for VT 03 V o What can you do to reduce leakage VT V70 7 2 F VSBI2 F VSB0V1VTVTO Vsa 391 V VT gt VTU 1 V o BodyEffect o Altering VSB can be used to r reduce leakage negative BackBody Biasquot or Reverse Body Biasquot power increase speed positive ForwardBody Biasquot W Rhett Davis NC State University Slide 29 ECE 546 Fall 2008 W Rhett Davis NC State University Slide 30 ECE 546 Fall 2008 Static Power Consumption Summary V out Vin 5V C1 0 Pstatin1 VDD Istatin1 0 Pstatin0 VDD Istatin0 Pstat 12Fstatin1 Pstatin0 o Wasted Energy should be avoided W Rhett Davis NC State University Slide 31 ECE 546 Fall 2008 0 Putting it all together Ptot den Fsc Pstat Ptot CLVDD2 VDDIpeaktSCfO1VDDIIeak PDP Pmtp for HW1 ignore PSC and Pstat EDP Pmth W Rhett Davis NC State University Slide 32 ECE 546 Fall 2008 Announcements ECE 546 VLSI Systems Design Lecture 22 ThreeDimensional Integrated Circuits Fall 2008 W Rhett Davis NC State University with signi cant material from Rabaey Chandrakasan and Nikoli W Rhett Davis NC State University Slide 1 ECE 546 Fall 2008 0 Project Demonstrations Tuesday 9am6pm 1203a E82 0 Exam Review in Class Thursday 0 Project Reports due 5AM Thursday night Friday Morning Please limit filesize to 3MB W Rhett Davis NC State University Slide 2 ECE 546 Fall 2008 Outline Dueling PressReleases gt o 3DCs Why Do We Care 0 Cost considerations in 3DCs 0 Intro to Existing 3D Processes 0 Design Studies SRAM Dual Core Open Risc o Promising Theory Interconnect Networks W Rhett Davis NC State University Slide 3 ECE 546 Fall 2008 0 IBM is already running chips using the throughsilicon via technology in its manufacturing line and will begin making sample chips using this method available to customers in the second half of 2007 with production in IBlil Press Release Apr 12 2007 0 quotWe have a view that while 3 D stacking is very elegant it39s not for the faint of heart You better think hard about how you do it because it39s not a slam dunk Jerry Bautista Intel Associated Press Apr 12 2007 o How will 30 Interconnects affect design practices W Rhett Davis NC State University Slide 4 ECE 546 Fall 2008 Rent s Rule Predictions Haven t We Been Here Before o E F Rent 1960 r PKBr o W Donath 1979 Stochastic wirelength estimation 0 Extention to 3D Rongtian Zhang et al 2001 Bannerjee et al 2001 Joyner et al 2006 in1 ii in man ll nil Wirelength reduction of Rongtian Zhang etal ISQED 2001 VN ers but limited to about 2 for 5 to 8 tiers W Rhett Davis NC State University Slide 5 ECE 546 rm an grwquot I E El nitric oxide S39Zlcm Subramanian amp Neudeck 1991 o 3DIC and Systems Research has been ongoing 25 years but has yet to show a benefit that warrants the cost Slide 6 ECE 546 Fall 2008 What s Different Today The End of Moore s Law o ITRS 2005 lists Achieving ROI as a Lithography Difficult Challenge lt 32 nm 0 Currently using 193 nm wavelengths of light to print 45 nm features reaching the limit of what OPC can do 0 EUV Lithography is much more expensive than optical lithography o 3D integration is not cheap but may be the least expensive way to meet demand W Rhett Davis NC State University Slide 7 ECE 546 E Melnoaorslackmg 71 Cell slacking Advantages IIIIll W522 gtx Relative permit manuiaciurmg east lI Gblklml g s m umils lo runner reduction in rule Causes gt Hegmred pliglgllm systems may not he possmla gt Small almansloris make quotanslsmr loslll peristame axnm 3Xnm 2xnm Iwo memory cells p cammue pmvsn s technologywithnul 7 depending on e 7 7 ve aten tin 39quotMWE39 3 7quot mlclnl hrlcglmn mannered technology and Cunenlpaoe uroosl x Wm um sr gain same elteal as reduction perb smaller dESlgn rule manuiamurmg cosls s 3939 quot 39 quot quot 39 1 amps abou140 wrm Sr w cal each capacity mamas l 329 646 1236 25613 NAND Flash memory capauty all lecimology predictions by Nikkei Elecuonics shown ln parentheses Slide 8 ECE 546 Fall 2008 Outline Marginal Cost of Adding a Tier 0 3Dle Why Do We Care gt 0 Cost considerations in 3DCs 0 Intro to Existing 3D Processes 0 Design Studies SRAM Dual Core Open Rise 0 Promising Theory Interconnect Networks W Rhett Davis NC State University Slide 9 ECE 546 Fall 2008 0 Rule of Thumb Processing Cost CostTier Ntiers 1 o With this arguments marginal cost of 2nd Tier 50 increase in cost 3rd Tier 33 increase in cost etc o What about yield W Rhett Davis NC State University Slide 10 ECE 546 Fall 2008 Classic Yield Equation 3DICs Help Yield only w KGD Y1 ja 0 A Area mm2 d Defect density defectsmmZ o Clustering Parameter 0 a delta function Go a Poisson distribution 0 Typically a new process generation actually reduces cost by reducing area and increasing yield W Rhett Davis NC State University Slide 11 ECE 546 Fall 2008 Yield Comparison for Multiplie Tiers n 2n 4n an an l an 1 2n 1 4n Tnlzl Transislnr Area m m Zl o d 001 defectsmm2 o 05 0 Adding a tier improves yield but only if Known Good Diequot KGD testing is performed 0 For a yield wo KGD is identical to singletier case W Rhett Davis NC State University Slide 12 ECE 546 Fall 2008 KGD Testing is Expensive Die Anach 39lime SEE o KGD testing amp pickandplace can add 100 s to 1000 s to the cost of a wafer 0 Source Vitkavage FutureFab Jan 2007 W Rhett Davis NC State University Slide 13 ECE 546 Fall 2008 What Products are in the Works 0 3D DRAM Tezzaron expected 2008 gtgt With selfrepair circuitry confined to one tier a yield improvement is possible wo KGD testing May also apply to FPGAs 0 RF Power Ampli er IBM expected 2008 Uses 3D Interconnect to improve poweramplifier efficience presumably with a large groundplane Redundancy of the structure lends improvement wo KDG testing 0 Blue Gene Supercomputer IBM expected Puts memory wself repair circuitry on higher tiers W Rhett Davis NC State University Slide 14 ECE 546 Fall 2008 Outline 0 3DCs Why Do We Care 0 Cost considerations in 3DCs gt 0 Intro to Existing 3D Processes 0 Design Studies I SRAM Dual Core Open Rise 0 Promising Theory Interconnect Networks W Rhett Davis NC State University Slide 15 ECE 546 Fall 2008 Tezzaron 3D Process Single Tier Source Patti Proc IEEE 2006 0 3D Vias etched after transistors are fabricated ninimiqsimsm 2 SlawCuminquot 39 smsnainw mmninunw I wrrmpmwmmuui 0 Standard processing continues to complete metalization mimismzs m1 mt Po E39l39ushdlw rmmmuuam In w mum sums s 3942 Al 1M1 Mal m an rm Tap Mun W Rhett Davis NC State University Slide 16 ECE 546 Fall 2008 Alignment Tezzaron 3D Process Multi Tier Single tiers are then thinned in order to use optical alignment IBM Attaches to glass handle and thins to 10 um then bond amp remove glass Other processes Thin the silicon to 100 um then bond and further thin silicon to 10 um Photo IBM 2007 w Rhett Davis No state university Slide 17 ECE 545 Fan 2005 o FacetoFace Bonding o CopperPads for BackBonding w Rhett Dams No state university Slide 15 ECE 546 Fall 2005 Tezzaron 3D Process Complete Source Patti Proc IEEE 2006 0 Advantages Cheapest Process bulk Si Highest density Interconnect 25 um to 4 um pitches o Disadvantage r 3D Interconnect not a postprocess harder to engineer supplychain w Rhett Dams No state university Slide 15 ECE 546 Fan 2005 MITLL 3D Process 0 180 nm FDSOI 3tier 3metal throughvia process k m T 0 Advantages 3D Interconnect is post processe Small pitches 3 um 5 um kxm o Disadvantages Vias block routing Wequot Expensive technology w Rhett Dams No state university shaezo ECE 546 Fall 2005 Existing 3D Processes Summary 0 No one knows what the most costeffective 3D technology will be c To research applications need to make some assumptions Tierthickness via aspect ratio is typically 101 or 51 Process technology bqu or SOI Process flow postprocessed vias waferto wafer or dietowafer bonding no of tiers flipped or not flipped 0 Notice that none ofthese processes use dieto wafer bonding W Rhett Davis Nc stave University Slide21 EcE 546 Fall 2003 Outline 0 3DCs Why Do We Care 0 Cost considerations in 3DCs 0 Intro to Existing 3D Processes gt 0 Design Studies Dual Core Open Rise 0 Promising Theory Interconnect Networks WRhettDavis Nc smeUniversity Slide22 EcE546 Fallzooa Case Study 3D SRAM 0 Assume an ideal process flow w KGD testing 0 A 3D SRAM can reduce word and bitline lengths by 1 le 42 reduction for 3 tiers 0 Can we expectsimilar improvements in delay W Rhett Davis Nc stave University Slide23 EcE 546 Fall 2003 Design Results 0 Problem because RC delays get large memories are typically broken into many banks 0 Experiments with a For a 16Kbit memory 3Tier version reduced cycletime from 134 ns to 123 ns 82 nergy per access from single Tle 718 PJ t0 575 DJ 53 Double Ranked FlFO 3ch Triple anked FIFO both far below the 42 improvement predicted TierC WRhettDavis Nc smeUniversity slide24 EcE546 Fallzooa Dual Core OpenRISC 3D Partitioning Scheme o Startirliqd mint was Open C Reference Platform 8 stemon OpenRISC 1200 Microprocessor Wishbone Traf c Co Data and Instruction Memory Controllers Data and Instruction Memories o Interfaced a second OR1200 to Wishbone Traffic Cop Interesting case for power dissipation in 3DCs 0 Second OR1200 ave identical workload as irs w Rhett Dams No state university slide 25 ECE 546 Fall 2009 o Floorplanning Goal Focus on the improvement to memory bandwidth Tier A Tier B Tier C w RhettDaws No state university siiaezs Fall 2009 Dual Core OpenRISC Conclusions Area 198 mm2 ClockRae 392 MHz Power 386 W Energy 102 Efficiency MOPSW Performance Improvements 0 Memory Constrained Designs Show the Most Improvement from 3D Integration w Rhett Dams No state university slide 27 ECE 546 Fall 2009 Search for the Optinlum no of Tiers o Modi ed the MlTLL design ow to add an arbitrary number of tiers and more metal layers 0 Reran automated placeandroute flow with varying number of thermalvias to see if we could find an optimum w RhettDaws No state university siiaeze ECE 546 Fall 2009 Temperature Results Power Results FFTlemperalure temperature K 35m l Eesl power region Eesl power 39eGluh 330 320 310 5 E uHrevs o OR1200 Power Improvement 6 W Rhett Davis NC State University Slide 29 ECE 546 Fall 2008 W Rhett Davis NC State University Slide 30 ECE 546 Fall 2008 Timing Results PDP Results mum m Best llmmg I 39 v Eagllimmg eg oquot 1 K o OR1200 speed improvement 17 o Energyper operation improvement 25 W Rhett Davis NC State University Slide 31 ECE 546 Fall 2008 W Rhett Davis NC State University Slide 32 ECE 546 Fall 2008 3D Design Case Studies Timing 0 3D integration 30 with 58 tiers is A FFTZD 24 7 7 approxrmately I x ORFSOC 31 g 18 7 0Rpsoczg equrvalent to w L x in 7 7 two process 6 generations 0 90 45 technology node ns Hao Hua et al IITC 2006 W Rhat Davis NC Statue University SlldeSS ECE 546 Fall 2009 WireLength Reduction omoc Mrd lem nncan Experiments show that the theoretical reduction is happening How do we turn this into real performance improvement wRhettDavrs Nc StateUnIversIty snaeu ECESAG Faiizooa Outline 0 3DICs Why Do We Care 0 Cost considerations in 3DCs 0 Intro to Existing 3D Processes 0 Design Studies SRAM Dual Core Open Risc gt o Promising Theory Interconnect Networks w Rhett Davis Mc sme university Slide35 ECE 546 Fall 2009 Interconnect Networks on Chip NOC o Dally amp Towles DAC 2001 Multihop network gives power advantage over dedicated wires for some designs 0 Ideal for chipmulti processors CMP wRhettDavrs Nc StateUnIversIty CMP with 2cube N00 4 nearest neighbors per node snaess ECESAG Faiizooa Implications for 3D ICs 0 Applications that run well on a 2cube NOC will be limited to 2X improvement 0 To see more than 2X improvement need to focus on applications that need more than 4 LowDensity Parity Check LDPC o LDPC Codes are the best known to get to the biterrorrate vs signaltonoise ratio BER vs SNR performance of the Shannon Limit 0 Decoders are extremely complex 0 Belief Propagation Algorithm Best known LDPC Decoder Architecture 34 nearest neighbors does not fit Check Nodes nearest neighbors into mesh W Rhett Davis NC State University Slide 37 ECE 546 Fall 2008 W Rhett Davis NC State University Slide 38 ECE 546 Fall 2008 Advantage of 3D over 2D 3D Memory Stack 0 Architectural simulations suggest improvement from 3D interconnect gt 2X faster for same number of physical nodes 14 the number of physical nodes for same speed 2D and 3D LDPC NOC Simulations 0 Cycle Count n 100 AUD sun 2mm No of Parallel Physical Nodes W Rhett Davis NC State University Slide 39 ECE 546 Fall 2008 o Thejury is still out on MWSW whether or not logic onlogic applications my will be a win The most likely application for 3D le will be memory stacked o n processors W Rhett Davis NC State University Slide 40 ECE 546 Fall 2008 Conclusions o Unclear what kinds of 3D Processing will be available because no one knows what will provide the most cost benefit 0 Emerging products rely on selfrepair andor redundancy to get around yield issues no KGD testing 0 3DMultiProcessors still an active area of research Key question 2D network with memories stacked on top or 3D networks W Rhett Davis NC State University Slide 41 ECE 546 Fall 2008 ECE 546 VLSI Systems Design Lecture 20 Fast Adders Multipliers Fall 2008 W Rhett Davis NC State University with significant material from Rabaey Chandrakasan and Nikoli W Rhett Davis NC State University Slide 1 ECE 546 Fall 2008 Announcements 0 Project Milestone 2 Due in 1 week W Rhett Davis NC State University Slide 2 ECE 546 Fall 2008 Summary of Last Lecture How do the Ripplecarry and CarryBypass adders delay and area vary with the number of bits What is the most crucial aspect to optimize in orderto speedup the adder What is the inversion property ofthe full adder and how can it be exploited for a faster carry chain What is the criticalpath delay of a carrybypass adder in terms on N M tsetup tcarry tbypass and tsum W Rhett Davis NC State University Slide 3 ECE 546 Fall 2008 Today s Lecture 0 Fast Adders 113 gt Carry Lookahead Adder Carry Save Adder Compressor o Multipliers 114 Array Multiplier Carry Save Multiplier W Rhett Davis NC State University Slide 4 ECE 546 Fall 2008 LookAhead Basic Idea A0 50 A1 B1 AN1v BN1 I I I s0 s1 sIv1 Coak fAk7Bk7 Cogkel GkPkCoakel W Rhett Davis NC State University Slide 5 ECE 546 Fall 2008 Carry Lookahead Trees C070 2 G0 POCi O C01 G1 P1G0 PlPoci 0 C0 2 G2 132G1 PZPIGO PZPIPOCi 0 2 G2 P2 T1132P1Go POCiHO G21 P21C0 0 Can continue building the tree hierarchically W Rhett Davis NC State University Slide 6 ECE 546 Fall 2008 DotNotation for Lookahead Adders G19P1 G2P2 G1P1G0PRG10P1o o What is the criticalpath delay in terms of s W Rhett Davis NC State University Slide 7 ECE 546 Fall 2008 Logarithmic LookAhead Adder tp logzN W Rhett Davis NC State University Slide 8 ECE 546 Fall 2008 16bit Radix2 KoggeStone Tree IIIIII 33333T3 3TE E3 3 i iiii ii E ssssss o How does the area vary with the no of hits 0 What is the maximum fanout of a node 0 What ultimately limits the performance W Rhett Davis NC State University Slide 9 ECE 546 Fall 2008 Example Domino Adder Propagate Generate See remaining circuit diagrams in text W Rhett Davis NC State University Slide 10 ECE 546 Fall 2008 Today s Lecture 0 Fast Adders 113 Carry Lookahead Adder gt Carry Save Adder Compressor o Multipliers 114 Array Multiplier Carry Save Multiplier W Rhett Davis NC State University Slide 11 ECE 546 Fall 2008 Adding More than 2 numbers 0 What is the critical path delay of this structure a b c d Assuming ripplecarry adders Assuming carry lookahead adders sum 0 Can we do better W Rhett Davis NC State University Slide 12 ECE 546 Fall 2008 CarrySave Adder 42 Compressor abc d Coo Ci0 Co1 Cm sum carry o Ef ciently Compress 4 addends into 2 l l l d d d 0 Can be bunlt out offull 0 0 CO C a CF 0 CD adders 7cm c1 col cl ecu c 7 sum carry sum carry sum carry l l l l l l o What IS the criticalpath deay Weinberger IBM J ResDev 181 Santoro Horowitz JSSC 489 W Rhett Davis NC State University Slide 13 ECE 546 Fall 2008 Example sumg carryz suml carryl sumo carrya a o 1 o b g g 1 o Is this useful if the final adder is C 39 7 d O O 1 ripple carry 39sum carry lookahead carry total W Rhett Davis NC State University Slide 14 ECE 546 Fall 2008 Adder Summary Type Delay Area RippleCarry rc ON ON CarryBypass ON ON CarrySkip Smaller slope Small overhead than rc vs rc CarrySelect ON ON More than 2gtlt rc CarryLookahead Olog2 N ON log2 N CarrySave constant ON 42 Compressor when adding 4 nos same as rc o Exploit the properties ofthe Propagate and Generate signals for faster adders W Rhett Davis NC State University Slide 15 ECE 546 Fall 2008 Today s Lecture 0 Fast Adders 113 Carry Lookahead Adder Carry Save Adder Compressor gt o Multipliers 114 Array Multiplier Carry Save Multiplier W Rhett Davis NC State University Slide 16 ECE 546 Fall 2008 Binary Multiplication M71 I N71 XZXi2 Yzijzf j0 i0 MN71 Z XgtltY szzquot k0 M71 N71 N71 M71 139 39 i39 Ex2 2221 222102 10 j0 j0 10 W Rhett Davis NC State University Slide 17 ECE 546 Fall 2008 Binary Multiplication 2 sz 1 0 1 0 1 0 Multiplicand Y Y j X 1 0 1 1 Multiplier j0 j 1 O 1 O 1 O j1 1 O 1 O 1 O j2 O O O O O 0 Partial products j3 1 O 1 O 1 O 1 1 1 O O 1 1 1 0 Result N partial products M bits per partial product W Rhett Davis NC State University Slide 18 ECE 546 Fall 2008 The Array Multiplier W Rhett Davis NC State University Slide 19 ECE 546 Fall 2008 Array Multiplier Critical Path 7 Critical Path 1 m Critical Path 2 4 1 CIitical Path 1 amp 2 malt N W Rhett Davis NC State University Slide 20 ECE 546 Fall 2008 CarrySave Multiplier Every two partial product rows is essentially a carrysave adder Vector Merging Adder mulf W Rhett Davis NC State University Slide 21 ECE 546 Fall 2008 Multiplier Floorplan HA Multiplier Cell A Multiplier Cell ector Merging Cell X and Y signals are broadcasted through the complete array was W Rhett Davis NC State University Slide 22 ECE 546 Fall 2008 Multiplier Summary 0 Array Multipliers add partial products 0 CarrySave Multipliers can significantly reduce delay if a fastadder is used for the final merge W Rhett Davis NC State University Slide 23 ECE 546 Fall 2008

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