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Digital Electronics

by: Miracle Jaskolski

Digital Electronics ECE 733

Miracle Jaskolski
GPA 3.75


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Class Notes
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This 16 page Class Notes was uploaded by Miracle Jaskolski on Thursday October 15, 2015. The Class Notes belongs to ECE 733 at North Carolina State University taught by Staff in Fall. Since its upload, it has received 38 views. For similar materials see /class/223909/ece-733-north-carolina-state-university in ELECTRICAL AND COMPUTER ENGINEERING at North Carolina State University.

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Date Created: 10/15/15
Lecture 10 Latch and FlipFlop Design Slides orginally from Vladimir Stojanovic Computer Systems Laboratory Stanford University horowitzstanfordedu 572001 EE371 Outline Recent interest in latches and ip ops Timing and Power metrics Design and optimization tradeoffs Masterslave VS Pulsetriggered Latch Representative designs Comparison 572001 EE371 Recent Interest in FlipFlops Trends in highperformance systems D Higher clock frequency U More transistors on chip Consequences D Increased ip op overhead relative to cycle time Cycle time 10 20 F04 delays op overhead 2 4 F04 Difficult to control both edges of the clock Higher impact of clock skew u u a Higher crosstalk and substrate coupling a Higher power consumption expensive packages and cooling systems limit in performance Clock burns up to 40 flops up to 20 of total power a 572001 EE371 Requirements in the FlipFlop Design Small ClkOutput delay Narrow sampling window Low power Small clock load High driving capability increased levels of parallelism D Typical ip op load in a 018pm CMOS ranges from SOfF to over ZOOfF with typical values of lOOlSOfF in critical paths 2 8FO4s or even higher Integration of logic into the op Multiplexed or clock scan Crosstalk insensitivity dynamichigh impedance nodes are affected 572001 EE371 FlipFlop Delay Sum of setup time and Clkoutput delay is the only true measure of the performance with respect to the system speed Tsetup T Logic Tskew T TClkQ 572001 EE371 Delay vs SetupHold Times ilkOutput ps 50 0 DataClk ps 50 572001 EE371 Timing parameters details D Clk delay ps 410 Unstable C k Q region Stable ClkQ region 390 lt 4 370 7 8 DQ 3967 D CQU W 350 E E 2 q 330 e T minimum DQ lg LL ClkQ stable I 310 e D cc 290 7 l 270 39 Optimum setup time U 250 l l 80 60 40 20 0 20 40 60 80 100 The best point to pick on delay curve is minimum DQ 572001 EE371 7 Design amp optimization tradeoffs ED 0 Opposite Goals D Minimal Total power in consumption 0 g 40 u Minimal Delay 1 30 20 PowerDelay tradeoff 0 Minimize PowerDelay D 50 mo l50 200 prOduCt PDPtol Total Power uW SD in 70 7D q 60 E a 5 50 5 2 40 E A E 30 5 3U 20 N 10 in n 5 m 15 m 25 0 200 400 000 300 woo woo lMdth um Delay ps 572001 EE371 8 Types of FlipFlops MasterSlave Latch PulseTriggered Latch L D Q Data Data nsQ ClknR 572001 EE371 MasterSlave Latches Positive setup times Two clock phases D distributed globally D generated locally Small penalty in delay for incorporating MUX Some circuit tricks needed to reduce the overall delay 572001 EE371 TG MasterSlave Latch PowerPC 603 Gerosa JSSC 1294 Vdd Vdd 572001 EE371 TG MasterSlave Latch Low power feedback Unbuffered input D input capacitance depends on the phase of the clock D overshoot and undershoot with long routes D Wirelength must be restricted at the input Clock load is high Low power Small elkoutput delay but positive setup Easily embedded scan or muX 572001 EE371 CZMOS MS Latches Vdd Vdd Ck D Q Ckb Vdd Vdd Vdd Clk ck Vdd C Low power feedback Locally generated second phase Poor driving capability Robustness to clock slope 572001 EE371 SingleTransistorClocked MS latches Vdd W11 DSTC SSTC Yuan and Svennson JSSC Jan 97 Ratioed DCVS and SRPL based designs Relatively small clock load Very sensitive to input glitching Capacitive coupling and charge sharing related speed and power problems 572001 EE371 PulseTriggered Latches First stage is a pulse generator D generates a pulse glitch on a rising edge of the clock Second stage is a latch D captures the pulse generated in the first stage Pulse generation results in a negative setup time Frequently exhibit a soft edge property Must check for hold time Violations Note power is always consumed in the clocked pulse generator 572001 EE371 Hybrid Latch FlipFlop AMD K6 Partovi ISSCC 96 Clk 572001 EE371 HLFF Operation Lamar mmonnsanhzmpmm q pssemp m Hybnd Latch leerlop 5m ahsaxpnn 39T39 7 moussccvs Hybrid Latch FlipFlop Flip op features D single phase clock D edge triggered on one clock edge Latch features Soft clock edge property brief transparency equal to 3 inverter delays u a negative setup time u allows slack passing a absorbs skew Hold time is comparable to HLFF delay D minimum delay between ip ops must be controlled Fully static Possible to incorporate logic 572001 EE371 SemiDynamic FlipFlop SDFF Sun UltraSparc III Klass VLSI Circuits 98 Vdd Vdd 41 did J 3 6 W9 So edge conditioned by data since rst stage is precharged crosscoupled latch is added for robustness Small penalty for adding logic Latch has one transistor less in stack faster than HLFF but ll glitch exists 572001 EE371 20 Senseampli erbased ip op Matsui et al 1994 DEC Alpha 21264 StrongARM 110 First stage is a sense M ampli er On rising clock edge monotonic Sb or Rb trigger the SR latch Crosscoupled NAND speed bottleneck D 5 Big power savings in reduced swing designs 0quot Nice interface tofrom domino logic 572001 EE37l 21 Modi ed Sense AmplifierBased FlipFlop The rst stage is unchanged 3 sense ampli er Second stage is sized to provide maximum switching speed Driver transistors are large V E 6732 Keeper transistors are small and disengaged during transitions Nikolic amp Stojanovic ISSCC 99 572001 EE37l 22 Modified Sense AmplifierBased FlipFlop Delay of each of the outputs is independent of the load on the other output Delay of Q and Q is symmetrical as opposed to the NAND based design Convenient for dual rail logic and driving strength for standard CMOS is effectively doubled SAFF presents a small clock load small setup time and all the advantages of original design Possible tradeoffbetween speed and robustness to cross talk 572001 EE371 23 K6 DualRail ETL Vdd Selfreset property D increases dynamic power D drives domino logic Precharge increases speed Very fast but burns a lot of power Small clock load 572001 EE371 24 FlipFlop Performance Comparison Data D 20011 Test bench I 20011 E Total power consumed D intemal power D data power a clock power Delay is minimum D Q Measured for four cases Clk Q semp me D no activity 0000 and 1111 D maximum activity 0101010 U average activity random sequence 572001 EE371 Delay comparison L 300 3 K6 SAFF SlrongArm SSTC DSTC Pulsed design brings the fastest structures SDFF HLFF PowerPC mCZMOS 572001 EE371 Overall performance PDPm le PDPm le SArFF Strung KB SSTC DSTC HLFF SDFF PDWEIPC mCZMOS Arml 10 I Activitde 5 equal lransmnn pmbamhly I AE M H 5 equal vansmun prubabmw Real signals have the activity between 0 and 05 I Precharged hybrid structures are the fastest but their power consumption strongly depends on the probability of ones More ones above the I point 572001 EE371 27 Conventional ClkQ vs minimum DQ 0HLFF Fuwech E Strung Arm FF g rFF mczMos latch 5 K6 ETL SSTC o DSTC Delzylnsl 450 HLFF F0werFC E Strong Arm FF g SArFF a Hidden pOSitive mC2MOS latch 3 setup time vlte EFL Degradation of SSTC total delay mu an 2mm 25m sun 35m 39 DSTC Cler delay 25 6 SDFF 572001 EE371 28 Comparison of Clock power consumption DSTC MS latch SSTC MS latch K6 ETL FF 10 20 30 40 50 Local Clock power consumption pW 572001 EE371 29 Design goals Apply Avoid D Small clock load D Positive setuptime E Short direct path u u u u Sensitivity to clock slope and Reduced node swing Skew Lowpower feedback Pulsed design Optimization of both Master and Slave latch a Dynamic oating nodes Dynamic Master latch Conduct Power Delay optimizations on constant frequency really optim ize EnergyDelay product Take into account all sources of power dissipation ALWAYS use ClkQ setup time for max delay 572001 EE37 1 General characteristics D 60ps F04 delay in 2u technology D min gate Width l6u anditims transistors trmsistor pow power pow poms 572001 EE37 1


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