MICROPROCESSOR SYSTEM DESIGN
MICROPROCESSOR SYSTEM DESIGN ECE 473
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This 8 page Class Notes was uploaded by Marjorie Kulas on Monday October 19, 2015. The Class Notes belongs to ECE 473 at Oregon State University taught by R. Traylor in Fall. Since its upload, it has received 22 views. For similar materials see /class/224415/ece-473-oregon-state-university in Engineering Electrical & Compu at Oregon State University.
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Date Created: 10/19/15
AVR J TAG Interface J TAG development started about 1985 as a method to test populated circuit boards after manufacture The majority of manufacturing and field faults in circuit boards were due to bad solder joints J TAG was meant to provide a pinsout view from one IC pad to another so all these faults could be discovered Became an IEEE standard in 1990 IEEE Std 114911990 Now adopted by electronics companies all over the world Boundaryscan is mostly synonymous with J TAG In many ICs internal registers are on a scan chain This allows functionality to be tested completely even while an IC is in the circuit card and possibly while in a functioning system AVR J TAG Interface Boundaryrscnn Regusxe In the most basic implementation the boundary that is scanned is the io shell at the periphery of a chip The interfaces to the JTAG logic are very similar to What we have seen for SPI mm OW pm tck equiv to sck tdi equiv to mosi tdo equiv to miso tms no match UserDam I Bypass The JTAG scan chain forms a long I shift register AVR J TAG Interface Boundary scan principle of operation chip level Test Data In tTDl TTT fT39V lulua IIIrs IIIIn a Test Clo2k TICK Test Made Select TMS Test Data Out TDOJ Each boundaryscan cell can El Capture data on its parallel input PI III Update data onto its parallel output PO El Sena scan data from SCI to its neighbour39s Si El Behave transparently F39l passes to PO El Note all digital logic is contained inside the boundaryscan register PO AVR J TAG Interface Banndary scan principle of operation board level Emirifgtritgirjb L s V rig f2 CM r V r 7 AVR J TAG Interface J TAG is now primarily used as a method to access subblocks of integrated circuits programming nonvolatile memories EEPROM Flash a mechanism for debugging embedded systems a mechanism for checking for manufacturing defects As a debugging tool an I mcircuit emulator enables a programmer to access an onchip debug module integrated into the CPU The debug module enables the programmer to debug the software of an embedded system by setting breakpoints View CPU registers and other internal registers The J TAG scan chain generally does not help diagnose or test for timing temperature or other dynamic errors AVR J TAG Interface J TAG on the AVR allows access to all internal peripheral units internal and external RAM internal register file program counter EEPROM and Flash memory With the AVR Studio on chip debug is supported for AVR BREAK instruction break on change of program memory ow single step break memory breakpoints Onchip debug is Via private J TAG instructions Atmel propriatory AVR J TAG Interface ICE with AVR Descriptidn The AERE JTAGICE rninLII frbrn Atrnel Ei is a pcmerful development tool fer Onchip Debugging of all AVE Bbit RISE micrbbbntrdllers with IEEE 11491 mrnpliant JTAG interface or deb quIRE Interface debquIRE enables ranchip debug bf MFR micmntmllers in small pin gaunt packagee using Only a single wire fer the debug interface The AVR Studio onlinehelp mntains the must curTent infdn39natidn and a complete list bf supperth devices check Distributor Drderi ng Cede A39l39JTAGICEE lnve ntory Ddeumente AVR J TAG Interface J TAG 0n the AVR INJPIJHTD EE39IIEE DJLfDFH39I39 naumwr 51111 EHquot A I CF11 I H H511 EH 22 Ti L Fm PIE Fl 4 L JTirE We39d can GmNEJaTlC quotTGIFlei an sums mn CENTREL l39IZIPDRTn sigma EDIIIH ll Ebcl In