COMPUTER ARCHITECTURE ECE 472
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This 7 page Class Notes was uploaded by Marjorie Kulas on Monday October 19, 2015. The Class Notes belongs to ECE 472 at Oregon State University taught by Staff in Fall. Since its upload, it has received 11 views. For similar materials see /class/224422/ece-472-oregon-state-university in Engineering Electrical & Compu at Oregon State University.
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Date Created: 10/19/15
SPAM RISC Core Design 10 Revision History ver 10 10501 Original draft ver 11 10801 Fixed confusing write cycle description and references to SPAM periph erals 20 Background Highly integrated microcontrollers are in widespread use in many products These micro contollers have not only a microprocessor core but many peripherals to interface with the outside world This document describes the RISC core for the origninal SPAM design 30 SPAM RISC core description The acronym SPAM stands for Special Preipherally Assisted Microprocessor The SPAM RISC core hereafter referred to as the riscicore was based loosely on the MIPS architecture Its features include 16bit data path 12 bit address 8 general purpose registers with register R0 xed at 00001 18 instructions 31 risccore top level block diagram Shown below in Figure 10 is the riscicore Viewed from a high level risccore FIGURE 1 Top level View of SPAM RISC core SPAM RISC Core Design October 8 2001 1 32 risccore interface pin de nitions risc co re data15OH address110 resetin gt writein clk gt readin Pin datal 5 0 addressl l 0 writein readin resetin clk FIGURE 2 riisccore top level interface diagram Function Data bus 16bit MSB bit 15 This tristate bus is the external data interface to the riscicore Address bus 12bit MSB bit 12 The uP supplies the external address to memory or external peripherals via this bus This bus is always driven active riscicore uses this pin to validate external writes This signal is synchronous to clock Active low riscicore uses this pin to validate external reads This signal is synchronous to clock Active ow Input pin Provides asynchronous global reset to riscicore Input pin Global clock input TABLE 1 Pin De nition for 139isccore 33 System initial state When the global reset signal reset is asserted all internal state will be reset All internal state machines wi 11 be forced to their initial state After deassertion of resetin if the clock is running the riscicore will begin execution by fetching instruction data from memory address 0x000 When resetin is asserted and prior to any system clocks being supplied the riscicore out put signals will assume the following states pin state dataioutl 5 0 0xZZZZ high Z addressl l 0 0x000 read 0 deasserted write 0 deasserted TABLE 2 RISC Core Output Pin Reset State SPAM RISC Core Design October 8 2001 40 Instruction set architecture for the risccore The instruction set for riscicore is shown below in Table 3 instruction example function add add rd rs rt Add the contents of rs and rd39 place result into rd addi addi rs imm5 Add sign extended imm to the contents of rs and put result into rs sub sub rd rs rt Subtract the contents of rt from rs place result into rd subi subi rs imm Subtract sign extended imm from the contents of rs and put result into rs slt slt rd rs rt lfrs is less than rt then set rd to the value 0x0001 else set rd to the value 0x0000 The numbers in rs and rt are signed or or rd rs rt Logically OR the contents of rs and it place result into rd ori or rs imm Logically OR the contents of rs with zero extended imm39 place result into rs and and rd rs rt Logically AND the contents of rs and rt39 place result into rd andi andi rs imm Logically AND the contents of rs with zero extended imm39 place result into rs xor xor rd rs rt Logically XOR the contents of rs and it place result into rd xori xori rs imm Logically XOR the contents of rs with zero extended imm39 place result into rs jr jr rs Jump to the address speci ed in rs bits 1512 in rs are ignored lw lw rt immrs Load a 16bit word of data into rt from the address speci ed by adding the contents of rs with imm sw sw rt immrs Store a 16bit word of data in rt to the address speci ed by adding the contents of rs with imm lui lui rs imm Load the immediate value into the upper 8 bits of rs and set the lower 8 bits of rs to 0x0000 beq beq rs rt imm Compare rs and rt39 if rs is equal to rt branch to the address speci ed by adding the contents of the program counter with the value imm Since the riscicore is byte addressable and branches must be to even addresses a left shift of the immediate operand gives additional jump branch address range bne bne rs rt imm Compare rs and it if rs is not equal to rt branch to the address speci ed by adding the contents of the program counter with the value imm Since riscicore is byte addressable and branches must be to even addresses a left shift of the immediate operand gives additional jump branch address range j j imm Jump to the address speci ed by the immediate operand shifted left by one Since riscicore is byte addressable and branches must be to even addresses a left shift of the immediate operand gives additional jump branch address range TABLE 3 riscc0re Instruction Set SPAM RlSC Core Design October 8 2001 The format for the Rtype instructions is given below in Figure 6 5 3 3 3 2 add 00000 rs n rd nu add rdrsrt sub 00001 rs n rd nu sub rdrsrt slt 00010 rs n rd nu s1trdrsrt or 00011 rs n rd nu orrdrsrt and 00100 rs n rd nu and rdrsrt xor 00101 rs n rd nu xorrdrsrt 5 3 8 jr 00110 rs nu jr rs nu not used FIGURE 3 R Type Instruction Format The format for the Itype instructions is given below in Figure 7 5 3 3 5 1w 00111 rs n imm 1w rs n imm sw 01000 rs n imm sw rs n imm beq I 01001 I IS I It I imm I beq rs 1t imm bne I 01010 I IS I It I imm I bne rs 1t imm 5 3 8 addil 01011 rs imm addi rs imm subi I 01100 I rs I imm I subi rs imm ori I 01110 I IS I imm I ori rs imm andiI 01111 I IS I imm I andi rs imm xori I 10000 I rs I imm I xori rs imm 1ui 10001 rs imm 1ui rs imm SPAM RlSC Core Design October 8 2001 FIGURE 4 I Type Instruction Format The format for the Jtype instruction is given below in Figure 8 5 11 j 10010 imm j imm FIGURE 5 J Type Instruction Format 401 Register Set The register set for riscicore consists of 8 16bit registers Any register may be used as a operand source and all registers except R0 can be used as a destination Register zero R0 is readonly with a xed value of zero 0x0000 402 Addressing The riscicore will use byte addressing A alignment restriction must be inforced which is that words l6bits start on multiples of 2 bytes The byte order is bigendian For exam ple the byte ordering within a word appears as below This word has a word address which is also zero 15 0 FIGURE 6 Byte Ordering The riscicore has an address space of2110r 4K bytes ranging from 0x000 to OxFFF 403 Sign Extention for Immediate Instructions When executing the following instructions some type of operand size extention is required to correctly computer the arithmetic logical or address value addi subi signextended The immediate value is an eightbit signed number To do the math operation correctly the bit seven of the immediate value is replicated in bits eight through fteen in the word applied to the ALU beq bne signextended and shifted left The immediate address offset value is an vebit signed number To compute the branch address correctly bit four sign bit of the imme daite value is replicated in bits ve through fteen and then left shifted by one to generate a word address offset SPAM RlSC Core Design October 8 2001 5 lwsw signextended The immediate address offset value is an vebit signed number To compute the load or store address correctly bit four sign bit of the immedaite value is replicated in bits ve through fteen No shifting is done to this address offset as loads and stores to byte addresses is supported andi ori x01i zero extended The upper bits 158 of the immediate operand are forced to zero lui no sign extention Immediate operand is loaded into upper eight bits of destination register lower eight bits of destination register are set to zero 41 External Timing The riscicore runs off a synchronous lOMhz clock The clock signal is free running ie never stops The reset signal reset is asserted early before any clock or enable signals begin to assert It is used to reset all synchronous logic Reads and writes to external offchip memory are by de nition to addresses OXOOOO through address 0X07if 411 Read cycle The riscicore begins an memory read cycle by placing a valid memory address on its address lines One cycle later the read output is asserted At the clock edge which marks the deassertion of read the input data is sampled Ilt100nsgtI clock J l l g I addressl 1 IO gt391 I address validgt5 2quot 3 4 39 valid I 12112 44 5 s data150 I highZ a readn FIGURE 7 Timing for riscc0re read cycle SPAM RlSC Core Design October 8 2001 6 description min ns maxns l delay from clock edge to address valid 5 2 hold time addressl l 0 changing 5 3 setup time data valid before rising edge of clock 10 4 hold time for datal50 after clock rising edge 10 5 delay from clock edge to readin 5 TABLE 4 Timing for riscc0re read cycle 412 Write Cycle The riscicore begins a memory write cycle by placing a valid memory address on its address lines One cycle later the writein output is asserted One cycle after that writein is deasserted terminating the write cycle I 100nsgt clock J l g l g I addressl 1 0 gt1lt addrl ss validgt5 2quot 3 14 h datal 5 0 39t 39 WU 6 H FIGURE 8 Timing for riscc0re write cycle description min ns maxns l delay from clock edge to address valid 5 2 hold time addressl l 0 changing 5 3 delay to data valid after rising edge of clock 10 4 hold time for datal50 after clock rising edge 10 15 5 delay from clock edge to writein 2 5 TABLE 5 Timing for riscc0re write cycle SPAM RlSC Core Design October 8 2001 7
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