ELECTRONICS II ECE 323
Popular in Course
Popular in Engineering Electrical & Compu
This 69 page Class Notes was uploaded by Sam Robel on Monday October 19, 2015. The Class Notes belongs to ECE 323 at Oregon State University taught by Staff in Fall. Since its upload, it has received 15 views. For similar materials see /class/224427/ece-323-oregon-state-university in Engineering Electrical & Compu at Oregon State University.
Reviews for ELECTRONICS II
Report this Material
What is Karma?
Karma is the currency of StudySoup.
You can buy or earn more Karma at anytime and redeem it for class notes, study guides, flashcards, and more!
Date Created: 10/19/15
aw Chapter 28 Performing Library Encryption Library encryption allows you to distribute proprietary StarHspice models parameters and circuits to other people without revealing your company s sensitive information Recipients of an encrypted library can run simulations that use your libraries but StarHspice does not print encrypted parameters encrypted circuit netlists or internal node voltages Your library user sees the devices and circuits as black boxes which provide terminal functions only Use the library encryption scheme primarily to distribute circuit blocks with embedded transistor models such as ASIC library cells and IO buffers Star Hspice uses subcircuit calls to read encrypted information To distribute device libraries only create a unique subcircuit le for each device This chapter describes Avant s Library Encryptor and how to use it to protect your intellectual property The following topics are covered in the chapter I Understanding Library Encryption I Knowing the Encryption Guidelines I Installing and Running the Encryptor StarHspice Manual Release 19982 281 Understanding Library Encryption Performing Library Encryption Understanding Library Encryption The library encryption algorithm is based on that of a fiverotor Enigma machine The encryption process allows the user to specify which portions of subcircuits are encrypted The libraries are encrypted using a key value that Star Hspice reconstructs for decryption Controlling the Encryption Process To control the beginning and end of the encryption process insert PROTECT and UNPROTECT statements around text to be encrypted in an StarHspice subcircuit The encryption process produces an ASCII text le in which all text that follows PROTECT and precedes UNPROTECT is encrypted Note The Star Hspice PROTEC T and UNPROTEC T statements often are abbreviated to PROT and UNPROT respectively Either form may be used in Star Hspice input les Library Structure The requirements for encrypted libraries of subcircuits are the same as the requirements for regular subcircuit libraries Subcircuit library structure requirements are described in Chapter 2 Getting Started Refer to an encrypted subcircuit by using its subcircuit name in a subcircuit element line of the StarHspice netlist The following example provides the description of an encrypted IO buffer library subcircuit This subcircuit is constructed of several subcircuits and model statements that you need to protect with encryption Figure 281 shows the organization of subcircuits and models in libraries used in this example 282 StarHspice Manual Release 79982 Performing Library Encryption Understanding Library Encryption Design View File System Top Level ltLibraryDirgt iobuf Fast Typical Slow ioinv iobufinc ioinvinc ioinvinc iobufinc ltmodelsgt iobufinc ioinvinc ltmodelsgt ltmodelsgt Figure 281 Encrypted Library Structure The following input le fragment from the main circuit level selects the Fast library and creates two instances of the iobuf circuit Option Search ltLibraryDirgtFast Corner Spec Xl drvin drvout iobuf Cload2pF Driver ul drvout O recvin O PCBMOdel Trace X2 recvin recvout iobuf Receiver StarHspice Manual Release 79982 283 Understanding Library Encryption Performing Library Encryption The le ltLibraryDirgtF astiobuf inc contains Subckt iobuf Pinl Pin2 CloadlpF iobufinc model 2001 improved iobuf PROTECT cPinl Pinl O lpF Users can t change this Xl Pinl Pin2 ioinv Italics here means encrypted Model pMod pmos Level28 Vto ltFastModelsgt Model nMod nmos Level28 Vto ltFastModelsgt UNPROTECT cPin2 Pin2 O Cload give you some control Ends The le ltLibraryDirgtF amtioinv inc contains Subckt ioinv Pinl Pin2 PROTECT mp1 Vcc Pinl Pin2 Vcc pMod ItalicsProtected mnl Pin2 Pinl Gnd Gnd nMod ItalicsProtected UNPROTECT Ends After encryption the basic layout of the subcircuits is the same However the text between PROTECT and UNPROTECT statements is unreadable except by StarHspice The protection statements also suppress printouts of encrypted model information from StarHspice Only StarHspice knows how to decrypt the model 284 StarHspice Manual Release 79982 Performing Library Encryption Knowing the Encryption Guidelines Knowing the Encryption Guidelines In general there are no differences between using the encrypted models and using regular models However you must test your subcircuits before encryption You will not be able to see what has gone wrong after encryption because of the protection offered by StarHspice Use any legal StarHspice statement inside your subcircuits to be encrypted Refer to SUBCKT or MACRO Statement on page 229 for further information on subcircuit construction You must take care when structuring your libraries If your library scheme requires that you change the name of a subcircuit you must encrypt that circuit again Placement of the PROTECT and UNPROTECT statements allows your customers to see portions of your subcircuits If you protect only device model statements in your subcircuits your users can set device sizes or substitute different subcircuits for lead frames protection circuits and so on This requires your users to know the circuits but it reduces the library management overhead for everyone Note If you are running any version of the encryptor prior to Star H spice Release H 93A03 there is a bug that prevents Star H spice from correctly decrypting a subcircuit if that subcircuit contains any semicolon characters even in comments In the following example the subcircuit baalsemialat is encrypted into baalsemiinc Sample semicolon bug Subth BadSemi A B PROT Semicolons cause problems rl A B lk UNPROT Ends StarHspice Manual Release 79982 285 Knowing the Encryption Guidelines Performing Library Encryption StarHspice responds with the following message reading include filebadsemi inc error ends card missing at readin gterrcgtr difficulty in reading input To solve this problem remove the semicolon from badsemidat and encrypt the le again Some versions of StarHspice cannot decrypt les with lines longer than 80 characters Avant strongly recommends that all encrypted les be limited to an 80character line length because at encryption time the StarHspice version that the customer uses is unknown You cannot gather the individuallyencrypted les into a single le or include them directly in the StarHspice netlist Place them in a separate directory pointed to by the OPTION SEARCH ltdirgt named ltsubgtinc for correct decryption by StarHspice 286 StarHspice Manual Release 79982 Performing Library Encryption Installing and Running the Encryptor Installing and Running the Encryptor This section describes how to install and run the Encryptor Installing the Encryptor If StarHspice is already installed on your system place the Encryptor in the directory installdirbin to install it Add the lines that allow the Encryptor to operate to your permit hsp le in the installdirbin directory If StarHspice is not installed on your system rst install StarHspice according to the installation guide and Star H spice Release Notes included in your Star Hspice package and then follow the instructions in the previous paragraph Note If you are running a oating license server you must stop and restart the server to see the changes to the permit le Running the Encryptor The Encryptor requires three parameters for each subcircuit encrypted ltInFileNamegt ltOutFileNamegt and the key type specifier F reelz39 b Enter the following line to encrypt a le metaencrypt i ltInfileNamegt cgt ltOutFileNamegt t Freelib As the Encryptor reads the input le it looks for PROTUNPROT pairs and encrypts the text between them You can encrypt only one le at a time StarHspice Manual Release 79982 Installing and Running the Encryptor Performing Library Encryption To encrypt many les in a directory use the following shell script to encrypt the les as a group This script produces a 1710 encrypted le for each dat le in the current directory The procedure assumes that the unencrypted les are suf xed with dat lbinsh for i in dat do Base basename i dat metaencrypt i Basedat o Baseinc t Freelib done SUBCKT ioinv Pinl Pin2 PROT FREELIB Encryption starts here X344327A3rx34ampAl A 1 HJHDH1 amp dFE234lampamp3 and stops here UNPROT is encrypted ENDS 288 StarHspice Manual Release 79982 CD4OZOBMCD4OZOBC CD404OBMCD404OBC CD406OBMCD406OBC General Description National Semiconductor The CD4020BMCD4OZOBC CD4060BMCD4OGOBC are 14stage ripple carry binary counters and the CD404OBM CD404OBC is a 12 stage ripple carry binary counter The counters are advanced one count on the negative transition of each clock pulse The counters are reset to the zero state by a logical 1quot at the reset input independent of clock February 1988 14Stage Ripple Carry Binary Counters 12Stage Ripple Carry Binary Counters 14Stage Ripple Carry Binary Counters Features I Wide supply voltage range I High noise immunity I Low power TTL compatibility I Medium speed operation I Schmitt trigger clock input 10V to 15V 045 VDD typ Fan out of 2 driving 74L or 1 driving 74LS 8 MHz typ at VDD 10V Connection Diagrams DualInLine Package CD40203MCD40203C Top View V00 011 010 as 19 RESET m 01 1s 15 14 13 12 11 I10 I9 Von Vss I1 2 3 4 5 5 1 s 012 013 014 015 05 07 04 Vss TLF59531 TopView DualInLine Package CD404OBMCD404OBC V00 011 010 us 119 RESET m 111 16 15 14 13 12 11 I10 I97 Vnn Vss I1 2 3 4 5 a 7 a D12 16 15 17 14 13 12 Vss TLF5953 2 Order Number CD40203 CD404OB or CD4OBOB DualInLine Package CD40603MCD40603C Von 01o 011 09 RESET 1 M 111 15 14 13 12 11 111 I 9 VDD P Vss I 1 2 3 4 5 6 7 s 012 013 014 E1 5 07 04 Vss TLF5953 3 Top View 1995 National Se miconductor Corporation TL F5953 RRD B30M105Printed in U S A Sietunoa Aieuig A1123 eddia a etsn agwgogovaa Sietunoa Aieuig meg eddia GBBISZL OElWEIOVOVGOSJGIUI39IOO Meuia MJBO elddll a eisw OElINEIOZOVGO Absolute Maximum Ratings Noles1 and 2 Recommended Operating If MilitaryAerospace s ec led devices are required Conditions lea e contact the National Semic OfficseDistributors for availability and Eggitiiigarliosnaslfs supply V Hage VDD 3V1 15V Supply Voltage V99 7 05V to 1sv npm V age V39N 0V1 VD lnpu1VollageVN 7 05V to VDD 05V O39Eegjgfxgi mpe39amre Range TA 755010 1250 Storage Temperature Range T5 765 to 150 C CD40XXBC 740 10 55ac Package Dissipation PD DuallnLine 700 mW Small Outline 500 mW Lead Temperature TL Soldering 10 seconds 260 C DC Electrical Characteristics CD40XXBM Note 2 a e e symbol Parameter Conditions 55 c 25 c 125 c quot quot Min Max Min Typ Max Min Max lDD Quiescent Device Current VDD 5V VIN VDD or V55 5 5 150 0A VDD 10v VIN VDD or v55 10 10 300 0A VDD 15v VIN VDD or v55 20 20 600 0A VOL Low Level Output Voltage VDD 5V 005 0 005 005 V VDD 10v 005 0 005 0 05 v VDD 15v 005 0 005 0 05 v VOH High Level OutpulVollage VDD 5V 495 495 5 495 V VD 10V 995 995 10 995 V VDD 15V 1495 1495 15 1495 V VIL Low Level lnpulVollage VDD 5V V0 05V or 45V 15 2 15 15 V vDD 10vvo 10V or 90V 30 4 30 30 v VDD 15v v0 15V or 135v 40 6 40 40 v VIH High Level input Voltage VDD 5V V0 05V or 45V 35 35 3 35 V VDD 10v v0 10V or 90V 70 70 6 70 v VDD 15V0Vo 15Vor135V 110 110 9 110 V 10L Low Level Output Current VDD 5v v0 04V 064 051 055 036 mA See Note 3 VDD 10v v0 05V 16 13 225 09 mA VDD 15V V0 15V 42 34 88 24 mA 10H High Level ompul Current VDD 5v v0 46V 7064 7051 7055 7036 mA See Note 3 VD 10vvo 95V 716 713 7225 709 mA vDD 15v vo 135v 742 734 755 724 mA 1m lnpulCurrenl vDD 15vvIN 0v 7010 710 5 7010 710 0A VDD 15vvN 15v 010 10 5 010 10 0A Note 1 should be operated at these limits The tables dl Recommended Operating Conditionsquot and Electrical Characteristicsquot pmvlde edndmdns 1m actual devlce dpevalldn Note 2 v55 0v unless otherwlse speemed DSEliialDV 4 I mil ave DC Electrical Characteristics 40xch Note 2 e e e symbol Parameter Conditions 40 c 25 c 85 c Units Min Max Min Typ Max Min Max lDD Quiescent Device Current VDD 5V VIN VDD or V55 20 20 150 0A VDD 10v VIN VDD or v55 40 40 300 0A VDD 15v VIN VDD or v55 50 50 600 0A VOL Low Level OutpulVollage VDD 5V 005 0 005 005 V VDD 10v 005 0 005 005 v VDD 15v 005 0 005 005 v DC Electrical Characteristics 40XXBCNole 2 Coniinued symbol Parameier Conditions 740 c 250C 85 c Uniis Min Max Min Typ Max Min Max VOH High Level OuipuiVoliage VDD 5V 495 495 5 495 V D 10V 995 995 10 995 V VDD 15V 1495 1495 15 1495 V VIL Low Level lnpui Voliage VDD 5V V0 05V or 45V 15 2 15 15 V DD 10v v0 10v or 90V 30 4 30 3 0 v VDD 15v v0 15V or 135v 40 5 40 40 v VIH High Level lnpui Voliage VDD 5V V0 05V or 45V 35 35 3 35 V D 10VLVO 10V or 90V 70 70 6 70 V VDD 15vyvo 15Vor135V 110 110 9 110 v 10L Low Level Oulpul Curreni VDD 5v v0 04v 052 044 055 035 mA See Noie 3 D 10v v0 05V 13 11 225 09 mA VDD 15v v0 15V 35 30 55 24 mA 10H High Level Oulpul Curreni VDD 5v v0 46V 7052 7044 7055 7035 mA See o1e VDD 10v v0 9 av 713 711 225 709 mA VDD 15v v0 135v 735 730 55 724 mA 1m lnpui Curreni VDD 15v VIN 0v 7030 710 5 7030 710 0A VDD 15v VIN 15v 030 10 5 030 10 0A AC Electrical Characteristics CD402OBMCD402OBC CD404OBMCD404OBC TA 25 C CL 50 pF RL 200k ir if 20 ns unless oiherwise noied symbol Parameier Conditions Min Typ Max Uniis lpHL lpLH Propagaiion Delay Time 10 Q VDD 5V 250 550 ns VDD 10v 100 210 ns VDD 15v 75 150 ns lpHL lpLH lniersiage Propagaiion Delay Time VDD 5V 150 330 ns lrom On 10 On VDD 10V 60 125 ns VDD 15V 45 90 ns iTHL iTLH Transiiion Time VDD 5V 100 200 ns VDD 10v 50 100 ns VDD 15V 40 80 ns iWL iWH Minimum Clock Pulse Widih VDD 5V 125 335 ns VDD 10V 50 125 ns VDD 15V 40 100 ns ircL 1ch Maximum Clock Rise and Fall Time VDD 5V No Limii ns VDD 10V No Limii ns VDD 15V No Limii ns lGL Maximum Clock Frequency VDD 5V 15 4 MHZ VDD 10v 4 10 MHz VDD 15v 5 12 MHZ lpHLR Resei Propagaiion Delay VDD 5V 200 450 ns vDD 10v 100 210 ns VDD 15V 80 170 ns iWHm Minimum Resei Pulse Widih VDD 5V 200 450 ns VDD 10v 100 210 ns VDD 15V 80 170 ns Cm Average lnpui Capaciiance Any lnpui 5 75 pF Power Dissipaiion Capaciiance 50 pF 9 quotAC Pavamelevs are guavameed by DC eenelaied lesiing AC Electrical Characteristics CD406OBMCD406OBC TA 25 C CL 50 pF RL 200k tr tf 20 ns unless otherwise noted Symbol Parameter Conditions Min Typ Max Units tpHL4 tpLH4 Propagation Delay Time to Q4 VDD 5V 550 1300 ns VDD 10V 250 525 ns VDD 15V 200 400 ns tpHL tpLH lnterstage Propagation Delay Time VDD 5V 150 330 ns from Qn t0 Qn 1 VDD 10V 60 125 ns VDD 15V 45 90 ns 1211 L tTLH Transition Time VDD 5V 100 200 ns VDD 10V 50 100 ns VDD 15V 40 80 ns tWL tWH Minimum Clock Pulse Width VDD 5V 170 500 ns VDD 10V 65 170 ns VDD 15V 50 125 ns trCL thL Maximum Clock Rise and Fall Time VDD 5V No Limit ns VDD 10V No Limit ns VDD 15V No Limit ns fCL Maximum Clock Frequency VDD 5V 1 3 MHz VDD 10V 3 8 MHz VDD 15V 4 10 MHz tpHLR Reset Propagation Delay VDD 5V 200 450 ns VDD 10V 100 210 ns VDD 15V 80 170 ns tWHR Minimum Reset Pulse Width VDD 5V 200 450 ns VDD 10V 100 210 ns VDD 15V 80 170 ns Cin Average Input Capacitance Any Input 5 75 pF de Power Dissipation Capacitance 50 pF AC Parameters are guaranteed by DC correlated testing CD4060B Typical Oscillator Connections RC Oscillator Crystal Oscillator RESETO1L T0 COUNTER RESETO1 T0 COUNTER STAGES STAGES 11 10 9 93gt R2 R1 TL F 5953 4 TL F 5953 5 Schematic Diagrams CD40203MCD40203C Schematic Diagram 95 dgt 2 3 4 5 El 7 TMTHTd l 4 J i V I T T T gt 1 quot R 99 w 10 El 3 lt3 3 5A TLF5953 6 6 6 8 el 5 9 1 0 RESET 1 4 who Vss R R45 R as 1 1 a 6 9 6I cl V CD4OGOBMCD4OGOBC Schematic Diagram TLF5953 7 a l b u x 3 9 n a lt e D Im e u o uH Vss r R v an1 6 3 9 E ltl I I a T TLF5953 8 CD4020BM BC 14Stage Ripple Carry Binary CountersCD4040BM BC 12Stage Ripple Carry Binary Counters CD4060BMBC 14Stage Ripple Carry Binary Counters Physical Dimensions inches gimmeters 0 1994 MAX gt I 15 9 0220 0510 559 787 1 0 R 025 03964 0 005 0 020 R 013 0 51 WP 0037 0005 TYP 0005 01941043 0290 0520 39 2 0055 i 0005 737 01 3 T T e 140 013 P GLASS SEALANT I 0020 0000 I TYP 0200 I I 051 152 Mao MAX 500 457 MAX TYP 001020002 TYP I H 63318510 Mm TYP I 0251005 01250200 TYF 909i f 0 O ME 5523080 TYP 49511 5 BOlTZl39IOEIIIDMSAX F I I 001320005 gt 0395390 lt 04610108 WP 7398739o394I 1154 REV L 010010010 NP 254 1 025 Ceramic DualInLine Package J Order Number CD4OZOBMJ CD4OZOBCJ CD404OBMJ CD404OBCJ CD4OGOBMJ or CD4OGOBCJ NS Package Number J16A 07400780 O 090 15001001 quotI 2205 I II E E 025020010 5350 1 0254 PIN No 1 IDENT 391 OPTION 01 OPTION 02 0065 M 0000 40 TYP 0300 0320 1651 1 3302f0127 quotI I 15 24 W I I OPTIONAL j I 01450200 Iquot I I quot 35835080 E I L I I I 95 5 00080016 39 90 14 TYP 3 MIN 0200 1 01039405 M 0125 0150 003010015 7412 3175 3010 m MIN 0014 0023 010010010 0040 035P0554 T 005010010 2 54ng025 0393253931 N16E sz F 127P0254 8255 4381 Molded DuallnLine Package N Order Number CD4OZOBMN CD4OZOBCN CD404OBMN CD404OBCN CD4OGOBMN or CD4OGOBCN NS Package Number N16E LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which a are intended for surgical implant support device or system whose failure to perform can into the body or b support or sustain life and whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with instructions for use provided in the labeling can effectiveness be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd Japan Ltd 1111 West Bardin Road Fax 49 0400530 05 86 1301 Floor Straight Block Tel 01 043 299 2309 Arlington TX 76017 Email cnngetevm2nsccom Ocean Centre 5 Canton Rd Fax 81043299 2408 Tel 1800 2729959 Deutsch Tel 49 0180530 85 85 Tsimshatsui Kowloon Fax 1000 737 7010 English Tel 49 0400532 70 32 Hong Kong Francais Tel 49 0400532 93 50 Tel 052 27371600 Italiano Tel 49 0400534 16 00 Fax 052 27369960 quot 1mg 0 uiuyu51iuunor irr llilnalpnl39 39 39 39 g 39 0quot 1 For the following transistor amplifier circuit VDD 10V 3 RD 8 k9 RSS 10 k9 RL 2 k9 v Rs 50 2 0 ci 10 HF RL CL 5 Transistor t Kn 350 uAVZ v5 VT 1 V Cgs 20 pF T VSS 10V ng 10 pF a 10 pts Determine the DC bias conditions IDS and gm L Assam Sm UTN H MI IDS Haww VrL KNKIUV 1 SRSS avf I r 39 L 0 ng ZKnRssL in Ll Mk V R531 3 14 qu o Inst WWW 05 315 t Mum 325 I 1 325 I H 3 IDS Wzo ij Mm1 C Me kt Z 39 ixquot V63 lUv39 441 9m 1 2 H 5 7m r 3v 3 w uw VD iic v 047Mb s m HEM mull gtZ74LIV IDS gm y quot395 5 H01 lha V957VQVr WV b 10 pts Sketch the smallsignal AC model with all capacitors including the internal capacitors of the transistor CL 1 Note it may be helpful at this point to redraw the smallsignal diagram with all ground nodes at the bottom I am leaving you space for that here R 3 3m Var c 5 pts List the capacitors that will provide highpass function 41 I CL d 5 pts List the capacitors that will provide lowpass function gel e 10 pts Calculate the mid band gain vovSA Write down the mathematical expression in terms of circuit elementsparameters first Then evaluate MHX Eat16Kquot g L She439 3quot 32x Open Rs PM I 4 v J V K5 9 1396 g V RD L 39 1 I x L m h we 1 WWIRt xv RS 6 4 KS 1 Rs H y jivn cg Roma VoVs RaslUyn r i mathematical expression value f 10 pts Calculate the approximate lower 3dB cut off frequency You may use the dominant pole approximation but make note of any other low frequency poles for use in the Bode plot later Jill rv v f I S bu 4 Yuk SMQ P o KB C an 5 C0 Rsl CV5 g L 0 RI L L tux r gt mS LL quot 1 i5 L l gh39 tv39 4 t 3 M m K Rssll 394 C 5 IZZ Hg mathematical expression value g 10 pts Calculate the approximate upper 3 dB cut off frequency You may use the dominant pole approximation but make note of any other low frequency poles for use in the Bode plot later In rm 5 Mei lefvul 54 Ksll ssllglm R13 RDI RL 1 35 339 l v 5 WIquot l gtliR l Lm9s N7 39 RD39IKLL 6J 39 L 1Q JUL V 4 he 39 039 0 7 lslo WV 3 GWJ39 fH 277 Route Cad 7513 M Hz mathematical expression value h 10 pts Sketch the Bode plot magnitude and phase of the transfer function Label the axes appropriately Label the slopes appropriately Label the midband gain appropriately Identify fL and fH as well as any other poles you may have found v 39 RH quot IM QM IUJ A 396 Va Ms Cquot ac O L 1 392 39 0quot 2 m er gtT59 4 H z tM NM NM let 39 3 0 0 SN5404 SN54LSO4 SN54SO4 SN7404 SN74LSO4 SN74SO4 HEX NVERTERS SDLSOZQC DECEMBER 1983 REVISED JANUARY 2004 O Dependable Texas Instruments Quality and SN5404 J PACKAGE Reiiabiiity SN54Lso4 SN54so4 J OR w PACKAGE SN7404 SN74so4 D N OR NS PACKAGE SN74Lso4 D DB N OR NS PACKAGE TOP VIEW descriptionordering information These devices contain six independent inverters SN54LSU4 SN54SU4 FK PACKAGE TOP VIEW 0 O lt 9 Z 1 2019 2A 4 13 BY NC 5 17E NC 2Y 5 15 5A NC 7 15 NC 3A 3 4 EN 1 910111213 59 9 NC No internal connection Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet PRODUCTION DATA inlormation is current as M publication date Copyright 2004 Texas Instruments Incorporated Products coniorm to speciiications per tne terms or Texas instruments 0 Moms Empire to MLPRF33535 an palamele39s are tested duninn processing do or nenuise siartdavdwanamvPm 95quot quotenessavilvinnlude I T uniess ot noted On all ottrer products production testing or all parameters I EXAS processing does not necessarily incruue testing or all parameters POST OFFICE BOX 655303 DALLAS TEXAS 75265 1 SN5404 SN54LSO4 SN54SO4 SN7404 SN74LSO4 SN74SO4 HEX INVERTERS SDLSOZQC DECEMBER 1983 REVISED JANUARY 2004 ORDERING INFORMATION TA PACKw p i lf n WEEKS Tube SN7404N SN7404N PDIP N Tube SN74LSO4N SN74LSO4N Tube SN74SO4N SN74SO4N Tube SN7404D Tape and reel SN7404DR 7404 Tube SN74LSO4D 0 C to 70 C SOIC D Tape and reel SN74LSO4DR L804 Tube SN74SO4D Tape and reel SN74SO4DR 804 Tape and reel SN7404NSR SN7404 sop NS Tape and reel SN74LSO4NSR 74LSO4 Tape and reel SN74SO4NSR 74804 SSOP DB Tape and reel SN74LSO4DBR L804 Tube SN5404J SN5404J Tube SNJ5404J SNJ5404J Tube SN54LSO4J SN54LSO4J CDIP J Tube SN54SO4J SN54SO4J Tube SNJ54LSO4J SNJ54LSO4J 55 C to 125 C Tube SNJ54SO4J SNJ54SO4J Tube SNJ5404W SNJ5404W CFP VV Tube SNJ54LSO4W SNJ54LSO4W Tube SNJ54SO4W SNJ54SO4W Tube SNJ54LSO4FK SNJ54LSO4FK LCCC FK Tube SNJ54SO4FK SNJ54SO4FK TPackage drawings standard packing quantities thermal data symbolization and PCB design guidelines are available at wwwticomscpackage FUNC39I10N TABLE each inverter INPUT OUTPUT A Y I TEXAS INSTRUMENTS 2 POST OFFICE BOX655303 DALLAS TEXAS 75265 SN5404 SN54LSO4 SN54SO4 SN7404 SN74LSO4 SN74SO4 HEX INVERTERS SDLSOZQC DECEMBER 1983 REVISED JANUARY 2004 logic diagram positive logic 1A 4 w 2A gto 2v 3A gto 3v 4A gt0 4Y 5A gto 5v 6A gto BY YA 399 INSTRUMENTS POST OFF CE BOX 655303 DALLAS TEXAS 75265 3 SN5404 SN54LSO4 SN54SO4 SN7404 SN74LSO4 SN74SO4 HEX INVERTERS SDLSOZQC DECEMBER 1983 REVISED JANUARY 2004 schematics each gate 04 Vcc 4 k9 39 130 9 Input A lt Output Y K GND LSU4 504 v Voc ltgt ltgt 20 k9 8 kg 8 120 9 23 m 0 Input A Output Y GND Input A Resistor values shown are nominal I TEXAS INSTRUMENTS 4 POST OFFICE BOX655303 DALLAS TEXAS 75265 SN5404 SN54LSO4 SN54SO4 SN7404 SN74LSO4 SN74SO4 HEX NVERTERS SDLS029C DECEMBER 1983 REVISED JANUARY 2004 absolute maximum ratings over operating freeair temperature range unless otherwise noted139 Supply voltage VCC see Note 1 7 V Input voltage Vl 04 SO4 7 V Package thermal impedance eJA see Note 2 D package 86 CNV DB package 96 CNV N package 80 CNV NS package 76 CNV Storage temperature range Tstg 65 C to 150 C T Stresses beyond those listed under absolute maximum ratingsquot may cause permanent damage to the device This are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditionsquot is not implied Exposure to absolutemaximumrated conditions for extended periods may affect device reliability NOTES 1 Voltage values are with respect to network ground terminal The package thermal impedance is calculated in accordance with JESD 517 recommended operating conditions see Note 3 SN5404 NOTE 3 All unused inputs device must be held at VCC or GND ensure proper device operation Refer to the TI application report Implications of Slow or Floating CMOS Inputs literature number SCBA004 electrical characteristics over recommended operating freeair temperature range unless otherWIse noted PARAMETER TEST CONDITIONS conditions shown as MIN or MAX use the appropriate value specified under recommended operating conditions All typical values are at VCC 5 V T TINot more than one output should be shorted at a time IF TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 5 SN5404 SN54LSO4 SN54SO4 SN7404 SN74LSO4 SN74SO4 HEX INVERTERS SDLSOZQC DECEMBER 1983 REVISED JANUARY 2004 switching characteristics Vcc 5 V TA 25 C see Figure 1 SN5404 FROM TO SN7404 PARAMETER INPUT OUTPUT TEST CONDITIONS MIN TYP MAX UNIT t 12 22 PLH A Y RL4009 CL15pF ns tpHL 8 15 recommended operating conditions see Note 3 SN54LSU4 NOTE 3 All unused inputs of the device must be held at VCC or GND to ensure proper device operation Refer to the TI application report Implications of Slow or Floating CMOS Inputs literature number SCBA004 electrical characteristics over recommended operating freeair temperature range unless otherwise noted PARAMETER TEST CONDITIONST VccMN VH2V For conditions shown as MIN or MAX use the appropriate value speci ed under recommended operating conditions All typical values are at VCC 5 V T Not more than one output should be shorted at a time and the duration of the shortcircuit should not exceed one second switching characteristics Vcc 5 V TA 25 C see Figure 2 FROM SN54Lso4 SN74LSU4 PARAMETER INPUT OUTPUT TESTCONDITIONS MIN TYP MAX UNIT tpLH 9 15 A Y R 2k c 15 F tpHL 39 Q 39 p 10 15 quot5 I TEXAS INSTRUMENTS 6 POST OFFICE BOX655303 DALLAS TEXAS 75265 SN5404 SN54LSO4 SN54SO4 SN7404 SN74LSO4 SN74SO4 HEX NVERTERS SDLSOZQC DECEMBER 1983 REVISED JANUARY 2004 recommended operating conditions see Note 3 SN54SU4 NOTE 3 All unused inputs of the device must be held at VCC or GND to ensure proper device operation Refer to the TI application report Implications of Slow or Floating CMOS Inputs literature number SCBA004 electrical characteristics over recommended operating freeair temperature range unless otherwise noted PARAMETER TEST CONDITIONST For conditions shown as MIN or MAX use the appropriate value specified under recommended operating conditions iAll typical values are at VCC 5 V TA 25 C Not more than one output should be shorted at a time and the duration ofthe shortcircuit should not exceed one second switching characteristics Vcc 5 V TA 25 C see Figure 1 FRO To SN54SU4 SN74SU4 PARAMETER INPUT OUTPUT TEST CONDITIONS MIN TYP MAX UNIT tpLH 3 45 A Y R 280 C 15 F tpHL L Q L p 3 5 n5 tpLH 45 A Y R 280 Q C 50 pF ns tPHL 39 L 5 IF TEXAS INSTRUMENTS POST OFFlCE BOX 655303 DALLAS TEXAS 75265 7 SN5404 SN54LSO4 SN54SO4 SN7404 SN74LSO4 SN74SO4 HEX INVERTERS SDLSOZQC DECEMBER 1983 REVISED JANUARY 2004 PARAMETER MEASUREMENT INFORMATION SERIES 5474 AND 54S74S DEVICES Vcc Test RL Test Point 51 Point Vcc V From Output cc Under Test see Note 3 RL cL From Output RL see Note A Under Test 5 Note B From Output Test CL Under Test Point T see Note A CL see Note A I 152 L CU T LOAD CIRCUIT LOAD CIRCUIT FOR 2STATE TOTEMPOLE OUTPUTS FOR OPENCOLLECTOR OUTPUTS FOR 3STATE OUTPUTS HighLevel TIming 3 V Pulse 15 V 15 V Input 15 V I t I f l jh 0 V H w H I I tsu H 3 v LowLevel 15V 15V Data 15V 15V Pulse Input 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATIONS SETUP AND HOLD TIMES Output 3 V Control 1 lovwlevel 15 v 15 v Input 15v enabling 0v I tPZL D lt DI tPLZ tPLH I1 gt1 l I Waveform 1 I Z15 V 39quotg htaset see Notes c I 15 v up 15V andD voo5v see Note D I VOL l thH I4 gtI H tPHZ tPHL I 39I i VOH OutofPhase I Waveform 2 I XCVOH 05 V utput 15 v 99 mist 1395 V 215 v an see Note D VOL VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES 3STATE OUTPUTS NOTES A CL includes probe and jig capacitance B All diodes are 1N3064 or equivalent C Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control D S1 and S2 are closed fortpLH tpHL tpHZ andtpLZ S1 is open and S2 is closed forthH S1 is closed and S2 is open for thL E All input 39 quot quot H L 39 the following 39 39 PRR 51 MHz Z02 50 9 tr and tfs 7 ns for Series 5474 devices and tr and tf S 25 ns for Series 54S74S devices F The outputs are measured one at a time with one input transition per measurement Figure 1 Load Circuits and Voltage Waveforms I TEXAS INSTRUMENTS 8 POST OFFICE BOX655303 DALLAS TEXAS 75265 SN5404 SN54LSO4 SN54SO4 SN7404 SN74LSO4 SN74SO4 HEX NVERTERS SDLSOZQC DECEMBER 1983 REVISED JANUARY 2004 PARAMETER MEASUREMENT INFORMATION SERIES 54LS74LS DEVICES Test Point Vcc RL From Output Under Test see Note B From Output Under Test CL see Note A LO D CIRCUIT LOA FOR 2STATE TOTEMPOLE OUTPUTS HighLevel Pulse 13 V 13 V H tw H LowLevel 13 V 13 V Pulse VOLTAGE WAVEFORMS PULSE DURATIONS see Note D tPHL I 39I OutofPhase I 13 V H Dt tPLH VOH see Note D VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES A CL includes probe and jig capacitance All diodes are 1N3064 or equivalent 0W CL see Note A I D CIRCUIT FOR OPENCOLLECTOR OUTPUTS Vcc Test RL Point 0 S1 From Output Under Test CL see Note A est Point see Note B RL LOAD CIRCUIT FOR 3STATE OUTPUTS Timing 3 V Input 13 v o v 11 pi th tsu H D t 3 v a a 13 v 13 V Input 0 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output 3 V Control lovwevel 13 v 13 v enabling I 0 V tPZL D1 1 D lt tPLZ Waveform 1 l 215 V see Notes C l 1393 V andD I 3 Vavouosv tPZH gt r gt 1 tPHZ v Waveform 2 I o H VOH 05 V see Notes C 13 V and o 515 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES 3STATE OUTPUTS Waveform 1 is for an output with internal conditions such that the output is low except when disabled bythe output control Waveform 2 is for an output with internal conditions such that the output is high except when disabled bythe output control QTWU S1 and S2 are closed for tpLH tpHL tsz and hug S1 is open and S2 is closed for thH S1 is closed and S2 is open forthL Phase relationships between inputs and outputs have been chosen arbitrarily for these examples All input pulses are supplied by generators having the following characteristics PRR 51 MHz Z0 2 50 9 tr 5 15 ns tf S 26 ns The outputs are measured one at a time with one input transition per measurement Figure 2 Load Circuits and Voltage Waveforms IF TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 J R GDlP T CERAMIC DUAL IN LINE PACKAGE 14 LEADSSHOWN PINS n W M m m m B 0300 0300 0300 0300 762 762 762 762 1 a 380 380 380 380 1 1 1 1 B MAX 0785 840 0960 1060 1994 2134 2436 2692 B MIN C i 0 MAX 0300 0300 0310 0300 762 762 787 762 39J 7 0 245 0 245 0 220 0 245 0065 165 0 MIN 39 39 39 0045 114 622 622 559 622 0060 152 0005 013 MIN 0015 038 0200 508 MAX I Seating Plane 0130 330 MIN 4L7 0026 066 L W 039 1539 0100 254 0014 036 0008 020 4040083F 0303 NOTES All linear dimensions are in inches millimeters This drawing is subject to change without notice This package is hermetically sealed with a ceramic lid using glass frit Index point is provided on cap for terminal identi cation only on press ceramic glass frit seal only Falls within MIL STD 1835 GDIPl T14 GDlPl TIS GDIP1 T18 and GDIP1T20 mpow MECHANICAL DATA MCFPOOZA JANUARY 1995 REVISED FEBRUARY 2002 W RGDFPF14 CERAMIC DUAL FLATPACK 0260 660 0045 114 0235 597 f 0026 066 Base and Seating Plane r 2 0008 020 0080203 0004 010 0045 114 4 0280 711 MAX gt 1 14 0019 048 V i 0015 038 I I I I I I I I 0050 127 I I I I 0390 991 I I I I 0335 851 I I I I 0005 013 MIN 4 Places i 7 8 0360 914 0360 914 0250 635 0250 635 NOTES A All linear dimensions are in inches millimeters B This drawing is subject to change without notice C This package can be hermetically sealed with a ceramic lid using glass frit D Index point is provided on cap for terminal identi cation only E Falls Within MIL STD 1835 GDFP1F14 and JEDEC MO092AB 40401 802 C 0202 9 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 MECHANICAL DATA MLCC006B OCTOBER 1996 FK SCQCCN LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN N00F A B 18 17 16 15 14 13 12 TERMINALS MIN MAX MIN MAX 20 0342 0358 0307 0358 869 909 780 909 28 0442 0458 0406 0458 1123 1163 1031 1163 44 0640 0660 0495 0560 1626 1676 1258 1422 52 0739 0761 0495 0560 1878 1932 1258 1422 68 0938 0962 0850 0858 2383 2443 216 218 84 1141 1165 1047 1063 2899 2959 266 270 0020 051 0080 203 0010 025 l 0064 163 I I I I I I I f 0020051 0010 025 0055 140 0045 114 0045 114 0035 089 0028 071 l L 0045 114 0022 054 0035 089 0050 127 4040140D 1096 NOTES A All linear dimensions are in inches millimeters B This drawing is subject to change without notice C This package can be hermetically sealed with a metal lid D The terminals are gold plate E Falls Within JEDEC MS 004 39 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 MECHANICAL MPDIoo2c JANUARY 1995 REVISED DECEMBER 20002 N RPDlP1quot PLASTIC DUALlNLINE PACKAGE 16 PINS SHOWN 14 16 18 20 0775 0775 0920 1060 AMAX 1969 1969 2337 2692 16 9 A MIN 0745 0745 0850 0940 N rJH rJH rJH rJH rJH rJH 11 1892 1892 2159 2388 0260 660 M3400 W A VARIATION AA BB AC AD A LVJ LVJ LVJ Lu J Lu J Lu J H 1 1 L7 0070 178 A 0045 114 0045 114 0325 8 26 gt 0020 051 MIN I 0030 076 0300062 l 0200 508 MAX 0015 038 Gauge Plane 0010 025 NOM Seating Plane 0125 318 MIN 4 1092 L 0021 053 0015 038 39 1418 PIN ONLY A 20 pin vendor option 4040049E 122002 NOTES A All linear dimensions are in inches millimeters B This drawing is subject to change without notice amp Falls within JEDEC MS 001 except 18 and 20 pin minimum body lrngth Dim A g The 20 pin end lead shoulder width is a vendor option either half or full width IF TEXAS INSTRUMENTS POST OFFlCE BOX 655303 DALLAS TEXAS 75265 MECHANICAL DATA MSOI002B JANUARY 1995 REVISED SEPTEMBER 2001 D RPDSOG PLASTIC SMALLOUTLINE PACKAGE 8PINSSHOWN 0020051 39 0014035 Ii i if H H H H T 0244 620 0008 020 NOM 0228 580 0157 400 0150 381 Gage Plane i E 0010 025 0044 112 0016 040 0 8 Seating Plane 0010 025 E a 0004 010 PINS 8 14 16 DIM 0197 0344 0394 A MAX 500 875 1000 0189 0337 0386 A M39quot 480 855 980 4040047E 0901 NOTES A All linear dimensions are in inches millimeters B This drawing is subject to change without notice Body dimensions do not include mold ash or pr Falls Within JEDEC MS012 otrusion not to exceed 0006 015 00 5 TEXAS INSTRUMENTS POST OFFlCE BOX 655303 DALLAS TEXAS 75265 MECHANICAL DATA NS FlPDSOGquot PLASHC SMALLOU11INE PACKAGE 14 PINS SHOWN 051 7 m m jFIHrHHH T 015 NOM O IHHHHHg A H 005 Seating Plane 200 MAX PINS a DIM 16 A MAX 1050 1290 A MIN 990 1230 40400620 0303 NOTES A All linear dimensions are in millimeters This drawing is subject to change without notice C Body dimensions do not include mold ush or protrusion not to exceed 015 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except Where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding thirdparty products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Amplifiers Data Converters DSP Interface Logic Power Mgmt Microcontrollers amplifierticom dataconverterticom dspticom interfaceticom logicticom powerticom microcontrollerticom Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video amp Imaging V reless wwwticomaudio wwwticomautomotive wwwticombroad band wwwticomdigitalcontrol wwwticommilitary wwwticomopticalnetwork wwwticomsecurity wwwticomtelephony wwwticomvideo wwwticomwireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2004 Texas Instruments Incorporated National Semicondu CD4013BMCD4013BC Dual General Description The CD40138 dual D flipflop is a monolithic complementa ry MOS CMOS integrated circuit constructed with N and Pchannel enhancement mode transistors Each flipflop has independent data set reset and clock inputs and Q and 5 outputs These devices can be used for shift regis ter applications and by connecting 5 output to the data input for counter and toggle applications The logic level present at the D input is transferred to the Q output during the positivegoing transition of the clock pulse Setting or resetting is independent of the clock and is accomplished by a high level on the set or reset line respectively Cror D FlipFlop Features I Wide supply voltage range I High noise immunity I Low power TTL compatibility Applications I Automotive I Data terminals I Instrumentation I Medical electronics February 1988 30V to 15V 045 VDD typ fan out of 2 driving 74L or 1 driving 74LS I Alarm system I Industrial electronics I Remote metering I Computers Connection Diagram DualInLine Package T Level change x Don t care case VDD 02 62 CLOCKZ RESETZ DATAZ SETZ I 14 13 12 11 1o 9 a FF FF 1 2 1 2 3 4 5 6 7 11 1 CLOCK 1 RESET 1 DATA 1 SET 1 v33 TLF5946 1 Top View Truth Table CLT D R s Q 6 f O O O O 1 f 1 O O 1 Q X X 0 0 Q Q x x 1 O O 1 x x O 1 1 O x x 1 1 1 1 No change Order Number CD40133 1995 National Se miconductor Corporation TL F5946 RRD B30M105Printed in U S A doi1d111 a land oaaiovaomasiovao Absolute Maximum Ratings Notes1 192 If MilitaryAerospace s ec led lease contact t39 nal OfficeDistributors for availability and specifications the N DC Supply Voltage VDD lnput Voltage VIN Storage Temp Range Ts devices are required Semiconductor sales 705 Vpcto 18VDG 705 VDG to VDD 05VDG 65 C10 150 C Recommended Operating Conditions Note 2 DC Supply Voltage VDD lnput Voltage VIN Operating Temperature Range TA 013BM 3VDGto 15VDG 0 VDG to V99 V93 55 C10 125 C CD4013BC 740 Cto 85 Power Dissipation PD DuallnLine 700 mW Small Outline 500 mW Lead Temperature TL Soldering 10 seconds 260 C DC Electrical Characteristics CD401BBM Note 2 symbol Parameter Conditions 75 ac 25 l 1255c Units Min Max Min Typ Max Min Ma 11313 Quiescent Device VDD 5V VIN VDD or V55 10 10 30 HA Current VD 10V VIN VDD or V55 20 20 60 LA VDD 15V VIN VDD or V55 40 40 120 LA VOL liol lt 10 0A Output Voltage VDD 5V 005 005 005 V VDD 10V 005 005 005 V VDD 15V 005 005 005 V VOH High Level liol lt 10 0A Output Voltage VDD 5V 495 4 95 495 V VDD 10V 995 995 995 V VDD 15V 1495 1495 1495 V VIL liol lt 10 0A lnput Voltage VDD 5V 0 05V or 45V 15 15 15 V VDD 10VLV 10V or 90V 30 30 30 V VDD 15V Vo 15V or 135V 40 40 40 V VIH High Level liol lt 10 0A lnput Voltage VDD V0 V0 0 5V or 45V 35 35 35 V VDD 10V V0 10V or 90V 70 70 70 V VDD 15VLV0 15V or135V 110 110 110 V 10L Low Level Output VDD 5V V0 04V 064 051 055 036 mA Current Note 3 VDD 10V V0 05V 16 13 225 09 mA VDD 15V V0 15V 42 34 88 24 mA lOH High Level Output VDD 5VVo 46V 7064 7051 7055 7036 mA Current Note 3 VDD 10VV 95V 716 713 7225 709 mA VDD 15V V0 135V 742 734 755 724 mA lm lnput Current VDD 15V VIN 0V 701 e 10 5 701 710 LA VD 15V VIN 15V 01 10 5 01 10 LA DC Electrical Characteristics CD401BBC Note 2 symbol Parameter Conditions 74 c 25 8 c Units Min Max Min Typ Max Min Max 1913 Quiescent Device VDD 5V VIN VDD or V55 40 40 30 HA Current VDD 10V VIN VDD or V55 50 50 60 LA VDD 15V VIN VDD or VSS 160 160 120 LA VOL Low Level 1101 lt 10 0A Output Voltage VDD 5V 005 005 005 V VDD 10V 005 005 005 V VDD 15V 005 005 005 V VOH Hi h Leve liollt10 0A Output Voltage VDD 5V 495 495 495 V VDD 10V 995 995 995 V VDD 15V 1495 1495 1495 V VIL Low Level liol lt 10 0A lnput Voltage VDD 5V V0 05V or 45V 15 15 15 V VDD 10V V0 10V or 90V 30 30 30 V VDD 15V V0 15V or 135V 40 40 40 V DC Electrical Characteristics CD4013BCNoie 2 Coniinued symbol Parameier Conditions 740 25 c 85 c Uniis Min Max Min Typ Max Min Max VIH High Level iioi lt 10 11A inpui Voliage VDD 5V V0 05V or 45V 35 35 35 V VDD 10v v0 10V or 90V 70 70 70 v VDD 15VLV0 15Vor135V 110 110 110 V 10L Low Level Ouipui VDD 5v v0 04V 052 044 055 036 mA Curren1Noie 3 VDD 10v v0 05V 13 11 225 09 mA vDD 15v v0 1 5v 36 30 55 24 mA lOH High Level Ouipui vDD 5v vo 46V 7052 7044 7055 7036 mA Curren1Noie 3 VDD 10v v0 95V 713 71 1 7225 709 mA DD 15v v0 135v 736 730 755 724 mA lN inpuiCurreni VDD 15vvN 0v 703 710 5 703 710 0A VDD 15vvN 15v 03 10 5 03 10 0A Mom 1 shouid he opevaied a1 lhese lvnlls The lahles ol Recommended Opevailng Condlllonsquot and Eiecivlcai Chavacievlsilcsquot pmvlde oondlllons 1m aciuai devloe opevallon Mom 2 v55 0v uniess olherw1se soeollled Mme a IDH and IOL are measured one ouipui a1 a llme I I I A 25 L 5 p e L 2 yun ess oi erwise noie AC Electrlcal Characterlstlcs T c c 0 F R 00k l h d symbol Parameier Conditions Min Typ Max Uniis CLOCK OPERATION ipHL ipLH Propagaiion Delay Time VDD 5V 200 350 ns VDD 10v 50 160 ns VDD 15V 65 120 ns 1THL01TLH Transiiion Time VDD 5V 100 200 ns VDD 10v 50 100 ns VDD 15V 40 80 ns 1WL01WH Minimum Clock VDD 5V 100 200 ns Pulse Widih VDD 10V 40 80 ns VDD 15V 32 65 ns inch 1ch Maximum Clock Rise and VDD 5V 15 LS allTime VDD 10v 10 us VDD 15V 5 us isu Minimum SeiUp Time VDD 5V 20 40 ns VDD 10V 15 30 ns VDD 15V 12 25 ns iGL Maximum Clock VDD 5V 25 5 MHZ Frequency VDD 10V 62 125 MHZ VDD 15V 76 155 MHz SET AND RESET OPERATION ipHURy Propagaiion Delay Time VDD 5V 150 300 ns ipLHS VDD 10V 65 130 I15 VDD 15V 45 90 ns llHm Minimum Sei and VDD 5V 90 180 ns 1WHS Resei Pulse Widih VDD 10V 40 80 ns VDD 15V 25 50 ns Average inpui Capaciiance Any inpui 5 75 pF IN quotAC Pavameievs ave guavameed by DC oonelaled lesllng Schematic Diagram SET 0 MASTER SECTION on J RESETC LJ T T 13 Vss SLAVE SECTION LI 7 V LI CLOCK TALL PSUBSTRATES 39gt39 CONNECTED TO VDD I ALL NSU BSTRATES VDD Vss 39 TLF5946 4 1 CONNECTED TO V33 V33 TLF5946 3 TLF5946 2 Logic Diagram SLAVE SECTION D SETCgt47 CL MASTER SECTION CL TG T DATAO G CL f7 CL 1 L TG CL nessrc CL CL CLOCK Vss 2 gt E 4 DI 10R 6 quot33 tpLH I 7 10R 5 Va 90 50 10 Vss BUFFERED OUTPUTS gtu3ltgtu TLF5946 5 TLF5946 6 CD4013BMCD4013BC Dual D FlipFlop Physical Dimensions inches millimeters 0105 10930 mm mm IV ITEI WI ITTI WI TI 8 quot3153 0220 0310 5530 1014 U1 ILI 11 Ill Lil IiI LEI 0290 0320 ELF 0200 1360 0120 1012 GLASS 0050 0005 5000 MI SEALANT quotquot 39 MAX 1524 0121 0020 0050 0100 MA I 39 0500 1524 4512 00 94 1vn I 10 MAX 0000 0012 4 r 0310 0410 I0203nn3 5I 0010 50003 1 WM 4 1 was 9 0125 0200 0451 50015 1439 0115 5000 MAX BOTH ENDS 0100 50010 045 2540 511254 MN 0141015505 Ceramic DuallnLine Package J Order Number CD4013BMJ or CD4013BCJ NS Package Number J14A 074070770 1811071956 0090 2286 INDEX AREA 1250 i0010 O 6350i0254 PIN N0139 PIN N01 IDENT m m La m 5 0 7 IDENT 0092 NA 0030 MAX 2337 0752 DEPTH OPTION 1 OPTION 02 01350005 0 3004 320 042910127 1520 0120 1145 0200 gt MTYP 40 quotP Igt 0065 300315000 1524 OPTIONAL 1051 95050 0003 0016 m 08 90 4 TYP I 439 Iquot0203 0400 05 MIN quot39IZSTO39ISO I 39 00750015 0175 0010 gt go iolasn 0014 0023 e gt 03564554 TY 010010010 MIN 0 050 i39 o m 2540i0254 ltT0210 70254 quotP 0325 1016 8255 0381 Molded DuallnLine Package N Order Number CD4013BMN or CD4013BCN NS Package Number N14A N14A IREV FI LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION AS used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which a are intended for surgical implant support device or system whose failure to perform can into the body or b support or sustain life and whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with instructions for use provided in the labeling can effectiveness be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd Japan Ltd 1111 West Bardin Road Fax 49 0180530 85 86 13th Floor Straight Block Tel 810432992309 Arlington TX 76017 Email cnngetevm2nsccom Ocean Centre 5 Canton Rd Fax 810432992408 Tel 1800 2729959 Deutsch Tel 49 0180530 85 85 Tsimshatsui Kowloon Fax 1800 7377018 English Tel 49 0180532 78 32 Hong Kong Frangais Tel 49 0180532 93 58 Tel 852 27371600 Italiano Tel 49 0180534 16 80 Fax 852 27369960 National does not assume any respons bility for use of any circuitry described no circuit patent censes are implied and National reserves the right at any t me without notice to change said circuitry and specificat ons ECE 323 Midterm Exam Tuesday Nov 1 2005 1 For the s domain gain expression below sketch the Bode plot magnitude and phase Label the axes appropriately label all breakpoints and slopes Label the calculated value of gain in dB on the magnitude plot 1 s22210011122 1 s27er1 5 27510000 Hz Ava z 1000 lAvl dB 60 dB El n I 1 i a i I in M m I03V Fl HE A PhsAv l WFUlz a quot i 01 l 390 Hot N 1w mm 2 Consider the ampli er circuit shown below Use 33100 Vgpxm 07 V Vomit 02 V Ignore r0 10 R3 kg RS10kQ a Draw the complete small signal model including internal capacitances of the transistor Include the coupling capacitors in your diagram Label all components n9 9 b Calculate gm and r1 5 V 7 M V v jig quot it w KE3 HRE lg 1RE a q W4 339 4 3 an a ARMquotrm 33 7 Sean expression value expression value c Which capacitors will determine the highfrequency rolloff low pass function and which capacitors will determine the low frequency rollwo highpass function Notez four capacitors total Highpass capacitors C C C 39 Lowpass capacitors 1 Draw the corresponding high frequency smallsignal model assuming the frequency is high enough that the impedance of the coupling capacitors can be neglected Combine all ground nodes at the bottom of the circuit diagram 3 For the circuit shown here RSSOQ Rssle RD2kQ RLSOOQ v For the transistor 0 RL gm 001 mho quot Ri Vss SV 21 Draw the complete small signal model including internal capacitances of the transistor Include the coupling capacitors in your diagram Label all components b Which capacitors will determine the highfrequency roll off low pass tnction and which capacitors will determine the lowfrequency rolloff high pass function Notez four capacitors total Highpass capacitors C i C t Lowpass capacitors 35 Casi 0 Draw the corresponding highfrequency small signal model assuming the frequency is high enough that the impedance of the coupling capacitors can be neglected Combine all ground nodes at the bottom of the circuit diagram 1 Find the input resistance and output resistance of the ampli er circuit E mi Vale m Ki gm C10 11 R0 Z KJL expression value expression value e What value of capacitance for C1 will guarantee that the ampli er will pass a 20 Hz signal with only 3 dB loss with respect to the maximum gain Viv n5 I 41 j C il 6 WJWW 21T 2017 s quot 3 amiss l m W C39 MFR Hz Rules l C1 Mr L as as m z W MF expression value f Is this the minimum or maximum value for the capacitance in order for the ampli er to pass 20 Hz YV H HMU VH 9 What is the upper cutoff frequency for this ampli er use dominant pole Kl A I 1 0 1 iv 392 35 Q k q rout H 3 WA Zhl m 4 quot3 0 4 do wt r4 ft IV fH 24739 nglt oll ngt 90 MHz expression value 714742 Chapter 21 Using Transmission Lines A transmission line delivers an output signal at a distance from the point of signal input Any two conductors can make up a transmission line The signal which is transmitted from one end of the pair to the other end is the voltage between the conductors Power transmission lines telephone lines and waveguides are examples of transmission lines Other electrical elements which should be thought of as transmission lines include traces on printed circuit boards and multichip modules MCMs and within integrated circuits With current technologies that use highspeed active devices on both ends of most circuit traces all of the following transmission line effects must be considered during circuit analysis I Time delay Phase shift Power voltage and current loss Distortion Reduction of frequency bandwidth I Coupled line crosstalk StarHspice provides accurate modeling for all kinds of circuit connections including both lossless ideal and lossy transmission line elements This chapter covers these topics Selecting Wire Models Performing HSPICE Interconnect Simulation Understanding the Transmission Line Theory References StarHspice Manual Release 1 9982 21 1 Selecting VWe Models Using Transmission Lines Selecting Wire Models Various terms are used for electrical interconnections between nodes in a circuit Common terms are I Wire I Trace I Conductor I Line The term transmission line or interconnect generally can be used to mean any of the above terms Many applications model electrical properties of interconnections between nodes by their equivalent circuits and integrate them into the system simulation to make accurate predictions of system performance The choice of electrical model to simulate the behavior of interconnect must take into account all of the following Physical nature or electrical properties of the interconnect Bandwidth or risetime and source impedance of signals of interest Interconnect s actual time delay Complexity and accuracy of the model and the corresponding effects on the amount of CPU time required for simulations Choices for circuit models for interconnects are I No model at all Use a common node to connect two elements I Lumped models with R L and C elements as described in Chapter 12 Using Passive Devices These include a series resistor R a shunt capacitor C a series inductor and resistor RL and a series resistor and a shunt capacitor RC I Transmission line models such as an ideal transmission line T element or a lossy transmission line U element 272 StarHspice Manual Release 79982 Using Transmission Lines Selecting VWe Modes As a rule of thumb follow Einstein s advice Everything should be made as simple as possible but no simpler Choosing the simplest model that adequately simulates the required performance minimizes sources of confusion and error during analysis Generally to simulate both low and high frequency electrical properties of interconnects select the U element transmission line model When compatibility with conventional versions of SPICE is required use one of the discrete lumped models or the T element The best choice ofa transmission line model is determined by the following factors Source properties trise source risetime Rsource source output impedance Interconnect properties Z0 characteristic impedance TD time delay of the interconnection or R equivalent series resistance C equivalent shunt capacitor L equivalent series inductance Figure 211 is a guide to selecting a model based on the above factors StarHspice Manual Release 79982 273 Selecting VWe Models Using Transmission Lines Initial information required trise source risetime TD time delay of the interconnect Rsource source resistance Selection Criterion R gt 10 Rsource gt R R RsourceC gt 10 trise gt C1 trise 2 5 TD low frequency gt 10 trise gt L L R Rsource Default gt U 39 Compatibility with conventional SPICE T In nite bandwidth UISe lt 5 TD hlgh required for gt T frequency ideal sources Consider crosstalk gt U effects Consider line losses gt U TDs are very long gt or very short U Default gt U Figure 211 Wire Model Selection Chart Use the U model with either the ideal T element or the lossy U element You can also use the T element alone without the U model Thus StarHspice offers both a more exible de nition of the conventional SPICE T element and more accurate U element lossy simulations 274 StarHspice Manual Release 79982 Using Transmission Lines Selecting VWe Modes Physical Geometry gt U Model Calculated 39 39 RCl Precalculated RCL gt Held SOIUuon gt Impedancgj Delay gt Inverse Solution ZOTD L05bmeal LOSy T Element U Element Figure 212 U Model T Element and U Element Relationship The T and U elements do not support the ltMValgt multiplier function If a U or T element is used in a subcircuit and an instance of the subcircuit has a multiplier applied the results are inaccurate A warning message similar to the following is issued in both the status le stO and the output le lis if the smallest transmission line delay is less than TS TOP 1 0e6 warning the smallest T line delay TD 0245E l4 is too small Please check TD L and SCALE specification This feature is an aid to finding errors that cause excessively long simulations Ground and Reference Planes All transmission lines have a ground reference for the signal conductors In this manual the ground reference is called the reference plane so as not to be confused with SPICE ground The reference plane is the shield or the ground plane of the transmission line element The reference plane nodes may or may not be connected to SPICE ground StarHspice Manual Release 79982 275 Selecting VWe Models Using Transmission Lines Selection of Ideal or Lossy Transmission Line Element The ideal and lossy transmission line models each have particular advantages and they may be used in a complementary fashion Both model types are fully functional in AC analysis and transient analysis Some of the comparative advantages and uses of each type of model are listed in Table 211 Table 211 Ideal versus Lossy Transmission Line Ideal Transmission Line Lossy Transmission Line lossless includes loss effects used with voltage sources used with buffer drivers no limit on input risetime prefiltering necessary for fast rise less CPU time for long delays less CPU time for short delays differential mode only supports common mode simulation no ground bounce includes reference plane reactance single conductor up to five signal conductors allowed AC and transient analysis AC and transient analysis The ideal line is modeled as a voltage source and a resistor The lossy line is modeled as a multiple lumped lter section as illustrated in Figure 213 in E K out in out ref re p A T A A T AAAT fout vvv vvv vvv vvv ref Ideal Element Circuit Lossy Element Circuit Figure 213 Ideal versus Lossy Transmission Line Model 276 StarHspice Manual Release 79982 Using Transmission Lines Selecting VWe Modes Because the ideal element represents the complex impedance as a resistor the transmission line impedance is constant even at DC values On the other hand you may need to pref11ter the lossy element if ideal piecewise linear voltage sources are used to drive the line U Model Selection The U model allows three different description formats geometricphysical precomputed and electrical This model provides equally natural description of vendor parts physically described shapes and parametric input from field solvers The description format is specified by the required model parameter ELEV as follows I ELEV1 7 geometricphysical description such as width height and resistivity of conductors This accommodates board designers dealing with physical design rules ELEV2 7 precomputed parameters These are available with some commercial packaging or as a result of running a field solver on a physical description of commercial packaging ELEV3 7 electrical parameters such as delay and impedance available with purchased cables This model only allows one conductor and ground plane for PLEV l The U model explicitly supports transmission lines with several types of geometric structures The geometric structure type is indicated by the PLEV model parameter as follows I PLEV1 7 Selects planar structures such as microstrip and stripline which are the usual conductor shapes on integrated circuits and printedcircuit boards I PLEV2 7 Selects coax which frequently is used to connect separated instruments I PLEV3 7 Selects twinlead which is used to connect instruments and to suppress common mode noise coupling StarHspice Manual Release 79982 277 Selecting VWe Models Using Transmission Lines PLEV1 PLEV1 PLEV2 El E El I PLEV3 PLEV3 PLEV3 O 0 Figure 214 U Model geometric Structures Transmission Line Usage Example The following StarHspice le fragment is an example of how both T elements and U elements can be referred to a single U model as indicated in Figure 212 The le speci es a 200 millimeter printed circuit wire implemented as both a U element and a T element The two implementations share a U model that is a geometric description ELEV1 of a planar structure PLEV1 T1 in grid tcgtut grid microl L200m Ul in grid ucgtut grid microl L200m model microl U LEVEL3 PLEV1 ELEV1 wd2m ht2m th025m KD5 StarHspice Manual Release 79982 Using Transmission Lines The next section provides where Tl U1 microl in gnd tiout and uiout L wd ht th KD StarHspice Manual Release 79982 Selecting VWe Modes details of element and model syntax are element names is the model name are nodes is the length of the signal conductor are dimensions of the signal conductor and dielectric and is the relative dielectric constant 27 9 Performing HSPICE Interconnect Simulation Using Transmission Lines Performing HSPICE Interconnect Simulation This section provides details of the requirements for T line or U line simulation Ideal T Element Statement The ideal transmission line element contains the element name connecting nodes characteristic impedance Z0 and wire delay TD unless Z0 and TD are obtained from a U model In that case it contains a reference to the U model ref Figure 215 Ideal Element Circuit The input and output of the ideal transmission line have the following relationships Vinlt Vout7 refoutt7TD tout XZ0t7TD Voutlt Vz39n 7 refintiTD iin gtlt ZOt7TD T Element Statement Syntax The syntax is Txxx in refin out refout Z0val TDval ltLvalgt ltICvlilv2i2gt or Txxx in refin out refout Z0val Fval ltNLvalgt ltICvlilv2i2gt 01 2770 StarHspice Manual Release 79982 Using Transmission Lines Performing HSPCE Interconnect Simulation Txxx in refin out refout mname Lval F NL mname TD re n refout Tm v1 v2 Z 0 StarHspice Manual Release 79982 frequency at which the transmission line has electrical length NL initial conditions keyword initial branch current for input port initial branch current for output port signal node in side physical length of the transmission line meter default 1 meter normalized electrical length of the transmission line with respect to the wavelength in the line at the frequency specified with the F parameter Default025 which corresponds to a quarterwave frequency U model reference name signal node ou side transmission delay secmeter TDeffTDgtL or TDeffNLF or TDeffTD computed from U modelgtL ground references for input and output transmission line lossless element Must begin with a T which may be followed by up to 15 alphanumeric characters initial voltage across input port initial voltage across output port characteristic impedance 2777 Performing HSPCE Interconnect Simulation Using Transmission Lines The ideal transmission line only delays the difference between the signal and the reference Some applications such as a differential output driving twisted pair cable require both differential and common mode propagation If the full signal and reference are required a U element should be used However as a crude approximation two T elements may be used as shown in Figure 216 Note that in this figure the two lines are completely uncoupled so that only the delay and impedance values are correctly modeled Figure 216 Use of Two T Elements for Full Signal and Reference You cannot implement coupled lines with the T element so use U elements for applications requiring two or three coupled conductors StarHspice uses atransient timestep that does not exceed half the minimum line delay Very short transmission lines relative to the analysis time step cause long simulation times Very short lines can usually be replaced by a single R L or C element see Figure 211 Lossy U Element Statement StarHspice uses a U element to model single and coupled lossy transmission lines for various planar coaxial and twinlead structures When a U element is included in your netlist StarHspice creates an internal network of R L C and G elements to represent up to five lines and their coupling capacitances and inductances For more information see Chapter 12 UsingPassive Devices The interconnect properties may be specified in three ways 2772 StarHspice Manual Release 79982 Using Transmission Lines Performing HSPCE Interconnect Simulation I The R L C and G conductance parameters may be directly specified in matrix form ELEV 2 I Common electrical parameters such as characteristic impedance and attenuation factors ELEV 3 may be provided I The geometry and the material properties of the interconnect may be specified ELEV 1 This section initially describes how to use the third method The U model provided with StarHspice has been optimized for typical geometries used in ICs MCMs and PCBs The model s closed form expressions have been optimized via measurements and comparisons with several different electromagnetic field solvers The StarHspice U element geometric model can handle from one to five uniformly spaced transmission lines all at the same height Also the transmission lines may be on top of a dielectric microstrip buried in a sea of dielectric buried have reference planes above and below them stripline or have a single reference plane and dielectric above and below the line overlay Thickness conductor resistivity and dielectric conductivity allow for calculating loss as well The U element statement contains the element name the connecting nodes the U model reference name the length of the transmission line and optionally the number of lumps in the element Two kinds of lossy lines can be made lines with a reference plane inductance LRR controlled by the model parameter LLEV and lines without a reference plane inductance Wires on integrated circuits and printed circuit boards typically require reference plane inductance The reference ground inductance and the reference plane capacitance to SPICE ground are set by the HGP CMULT and optionally the CEXT parameters StarHspice Manual Release 79982 27 7 3 Performing HSPCE Interconnect Simulation Using Transmission Lines U Element Statement Syntax The syntax is One wire with ground reference UXXX in refin out refout mname Lval ltLUMPSvalgt Two wires with ground reference UXXX inl in2 refin outl out2 refout mname Lval ltLUMPSvalgt Two or more wires with ground reference UXXX inl inn refin outl outn refout mname Lval ltLUMPSvalgt Uxxx lossy transmission line element name in inn input signal nodes 1 through 71 re n refout input or output reference name out outn output signal node 1 through 71 mname lossy transmission line model name Lval element length in meters LUMPSval number of lumps lumpedparameter sections in the element 2774 StarHspice Manual Release 79982 Using Transmission Lines Performing HSPICE Interconnect Simulation Lossy U Model Statement The schematic for a single lump of the U model with LLEV0 is shown in Figure 217 If LLEV is l the schematic includes inductance in the reference path as well as capacitance to HSPICE ground See Reference Planes and HSPICE Ground for more information about LLEVl and reference planes in W out refin AM VW refout Figure 217 Lossy Line with Reference Plane HSPICE netlist syntax for the U model is shown below Model parameters are listed in Tables 212 and 213 U Model Syntax The syntax is MODEL mname U LEVEL3 ELEVval PLEVval ltDLEVvalgt ltLLEVvalgt ltPnamevalgt LE VFL3 selects the lossy transmission line model ELEVval selects the electrical specification format including the geometric model val l PLEVval selects the transmission line type DLEVval selects the dielectric and ground reference con guration LLEVval selects the use of reference plane inductance and capacitance to HSPICE ground Pnameval specifies a physical parameter such as NL or WD see Table 212 or a loss parameter such as RHO orNLAY see Table 213 StarHspice Manual Release 79982 27 7 5 Performing HSPCE Interconnect Simulation Using Transmission Lines Figure 218 shows the three dielectric con gurations for the geometric U model You use the DLEV switch to specify one of these con gurations The geometric U model uses ELEV1 surrounding medium IIl conductor a b c d X reference plane Figure 218 Dielectric and Reference Plane Configurations a sea DLEV0 b microstrip DLEV1 c stripline DLEV2d overlay DLE 3 Lossy U Model Parameters for Planar Geometric Models PLEV1 ELEV1 2776 StarHspice Manual Release 79982 Using Transmission Lines Performing HSPCE Interconnect Simulation Common Planar Model Parameters The parameters for U models are shown in Table 212 Table 212 U Element Physical Parameters Parameter Units Default req 0 for sea 1 for microstrip 2 stripline 3 overlay default is 0 to omit 1 to include default is 0 default for DLEV2 is 2 HT TH TS is not used when DLEV0 used when LLEV1 this overrides the computed characteristic ground default is 1 only used when LLEV1 computing reference plane inductance and capacitance to ground default is 15HT HGP is only used when LLEV1 per StarHspice Manual Release 79982 27 7 7 Performing HSPCE Interconnect Simulation Using Transmission Lines There are two parametric adjustments in the U model XW and CORKD XW adds to the width of each conductor but does not change the conductor pitch spacing plus width XW is useful for examining the effects of conductor etching CORKD is a multiplier for the dielectric value Some board materials vary more than others and CORKD provides an easy way to test tolerance to dielectric variations Physical Parameters The dimensions for one and twoconductor planar transmission lines are shown in Figure 219 va4 ilt gti TH TH va SP llt gtl THKZ KDZ i 7 7 HT t i l mm KDl T J NP reference Plane T THGP HSPICE ground Figure 219 U Element Conductor Dimensions 2778 StarHspice Manual Release 79982 Using Transmission Lines Performing HSPCE Interconnect Simulation Loss Parameters Loss parameters for the U model are shown in Table 213 Table 213 U Element Loss Parameters Parameter Units Description copper core resistance 2 for core and skin resistance at skin effect frequency Losses have a large impact on circuit performance especially as clock frequencies increase RHO RHOB SIG and NLAY are parameters associated with losses Time domain simulators such as SPICE cannot directly handle losses that vary with frequency Both the resistive skin effect loss and the effects of dielectric loss create loss variations with frequency NLAY is a switch that turns on skin effect calculations in StarHspice The skin effect resistance is proportional to the conductor and backplane resistivities RHO and RHOB The dielectric conductivity is included through SIG The U model computes the skin effect resistance at a single frequency and uses that resistance as a constant The dielectric SIG is used to compute a fixed conductance matrix which is also constant for all frequencies A good approximation of losses can be obtained by r these 39 and J at the frequency of maximum power dissipation In AC analysis resistance increases as the square root of frequency above the skineffect frequency and resistance is constant below the skin effect frequency C Geometric Parameter Recommended Ranges The U element analytic equations compute quickly but have a limited range of validity The U element equations were optimized for typical IC MCM and PCB applications Table 214 lists the recommended minimum and maximum values for U element parameter variables StarHspice Manual Release 79982 27 7 9 Performing HSPICE Interconnect Simulation Using Transmission Lines Table 214 Recommended Ranges Parameter Min Max The U element equations lose their accuracy when values outside the recommended ranges are used Because the singleline formula is optimized for single lines you will notice a difference between the parameters of single lines and two coupled lines at a very wide separation The absolute error for a single line parameter is less than 5 when used within the recommended range The main line error for coupled lines is less than 15 Coupling errors can be as high as 30 in cases of very small coupling Since the largest errors occur at small coupling values actual waveform errors are kept small Reference Planes and HSPICE Ground Figure 21 10 shows a single lump ofa U model for a single line with reference plane inductance When LLEV1 the reference plane inductance is computed and capacitance from the reference plane to HSPICE ground is included in the model The reference plane is the ground plane of the conductors in the U model in W quot r out 7 refin AM m h refout 1 r OR can HSPICE ground Figure 2110 Schematic of a U Element Lump when LLEV1 2720 StarHspice Manual Release 79982 Using Transmission Lines Performing HSPICE Interconnect Simulation The model reference plane is not necessarily the same as HSPICE ground For example a printed circuit board with transmission lines might have a separate reference plane above a chassis HSPICE uses either HGP the distance between the reference plane and HSPICE ground or Cext to compute the parameters for the groundtoreference transmission line When HGP is used the capacitance per meter of the groundtoreference line is computed based on a planar line of width NL2WDSP and height HGP above SPICE ground CMULT is used as the dielectric constant of the ground toreference transmission line If Cat is given then Cext is used as the capacitance per meter for the groundtoreference line The inductance of the groundtoreference line is computed from the capacitance per meter and an assumed propagation at the speed of light Estimating the Skin Effect Frequency Most of the power in atransmission line is dissipated at the clock frequency As a first choice StarHspice estimates the maximum dissipation frequency or skin effect frequency from the risetime parameter The risetime parameter is set with the OPTION statement for example OPTION RISETIME0 lns Some designers use 035m39se to estimate the skin effect frequency This estimate is good for the bandwidth occupied by a transient but not for the clock frequency at which most of the energy is transferred In fact a frequency of 035m39se is far too high and results in excessive loss for almost all applications StarHspice computes the skin effect frequency from l15trise If you use precomputed model parameters ELEV 2 compute the resistance matrix at the skin effect frequency When the risetime parameter is not given StarHspice uses other parameters to compute the skin effect frequency StarHspice examines the TRAN statement for tstep and delmax and examines the source statement for trise If any one of the parameters tstep delmax and trise is set StarHspice uses the maximum of these parameters as the effective risetime StarHspice Manual Release 79982 2727
Are you sure you want to buy this material for
You're already Subscribed!
Looks like you've already subscribed to StudySoup, you won't need to purchase another subscription to get this material. To access this material simply click 'View Full Document'