CMOS INTEGRATED CIRCUITS I
CMOS INTEGRATED CIRCUITS I ECE 422
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This 15 page Class Notes was uploaded by Marjorie Kulas on Monday October 19, 2015. The Class Notes belongs to ECE 422 at Oregon State University taught by Staff in Fall. Since its upload, it has received 24 views. For similar materials see /class/224431/ece-422-oregon-state-university in Engineering Electrical & Compu at Oregon State University.
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Date Created: 10/19/15
HSPICE HELP The HSPICE analog circuit simulator is used for simulating the circuits in transient steady state and frequency domains Circuits can be accurately simulated for frequencies from DC to frequencies greater than 100 GHz HSPICE is one tool that can be used for accurate circuit and behavioral simulations The size of the circuits that can be simulated is only limited by the virtual memory of the computer used Many of you may choose to use a student version of PSPICE and that will also work for at least the first several assignments To begin the design entry and simulation process an input netlist file has to be created The analyses specified in the input netlist file are executed during the HSPICE run The results are posted in an output listing le If OPTIONS POST is specified then the data is stored in a graph data file If POST is specified the complete circuit solution is stored The HSPICE program has a textual command line interface To execute a netlist at the UNIX command prompt type hspice ltinputfile namegt HSPICE by default creates two standard output files to describe the initial conditions ic le and the output status stO file The input netlist file should have a sp extension Declaring a MOSFET ltInsmnce namegt d g s b ltinstance type wKl lK2 The above statement shows a general declaration for a MOSFET Instance name Every transistor used is an instance of a particular type of MOSFET PMOSNMOS So each and every transistor should have a distinct instance name Instance type This refers to the name of the prototype transistor NMOSPMOS mentioned in the model file In our case it is CMOSN for NMOS transistor and CMOSP for a PMOS transistor In the above syntax d refers to the drain g refers to the gate s refers to the source and b refers to the bulk Always ground should be referred to as 0 The parameter w39 and 1 refer to the width and length of the transistor used and are in units of meters Eg MI I 2 3 0 CMOSN w10u 1035u Independent source elements Use source elements to specify either DC AC transient or mixed independent voltage and current sources Some types of analysis use the associated analysis sources For example for a DC analysis if both the DC and AC sources are specified in one independent source the AC source is taken out General form Vxxx 11 11 ltltDCgt dcvalgt lttram mgt ltACacmag ltacphasegtgt Or Zvyy n n ltltDCgt dcvalgt lttranfungt ltACacmag ltacphasegtgt ltMvalgt where Vxxx independent voltage source element name Must begin with a V which can be followed by up to 15 alphanumeric characters Iyyy independent current source element name Must begin with an I which can be followed by up to 15 alphanumeric characters n positive node n negative node DC source value dcval The tranfun value at time zero overrides the DC value default00 tranfun transient source function AC ACI AM DC EXP PE PL PU PULSE PWL R RD SFFM SIN AC indicates source is to be used in an AC smallsignal analysis acmag AC magnitude acphase AC phase default00 M multiplier used for simulating multiple parallel current sources The current value is multiplied by M defau1t10 Passive elements The most commonly used elements are resistors and capacitors General form Rmx n n2 value Cxxx n n2 value Rxxx is a resistor connected between the nodes ml and n2 its resistance is given by the number value All the instance names of a resistor should start with R Cxxx is a capacitor connected between the nodes nl and 112 its capacitance is given by the number value All the instance names of a capacitor should start with a C Analysis The most commonly used analyses are the DC and AC analysis DC statement is used in DC analysis to 0 Sweep any parameter value 0 Sweep any source value etc General form DC var START start STUPstopl STEP incrl Eg dc v1 0 5 0 1 varl is the source to be swept start is the initial value of the sweep stopl is the max value to be swept to incrl is the increment value AC statement General form AC type ill fstartfsz op fstart is the starting frequency fstop is the ending frequency np number of points type can be any of the following keywords DEC decade variation OCT octave variation LIN Linear variation PRINT amp PLOT statements The PRJNT statement prints numeric analysis results The PLOT statement generates low resolution printer plots in the output listing le Examples PRINT ac vtype node vtypemodeZ PLOT dc v node vtype can be vdb the voltage of the node is printed in db vp the phase of the node is printed v gives the voltage of that node The inc statement This statement is used to include a file that has model parameters General form inc ltfilenamegt Example Lets assume that Vdd3 v and WIL10u2u The HSPICE code for the above circuit is op options post inc modelstxt transistor declaration M1 3 2 I O CMOSN w10u 12u sources V1 4 0 dc3v V2 2 0 dc2v ac0v II 1 O dc10u elements R13 410k C13 010p dc v2 0 2 01 print dc v3 end The above code sweeps the dc bias of the circuit and prints the operating point of the output node If an ac signal greater than zero was applied in the above example an ac analysis can be done with the following statements ac DEC 100 100 100x The above statement sweeps the signal frequency from 100 Hz to 100 MHz 1 Analog Integrated Circuit Design 4 C49 Current Sources Current Sources 0 Active loads 0 Bias currents and voltages Desirable Characteristics Low input resistance High output resistance DC balance Good matching of 10m to Iin TM Simple Current Source a Input Resistance 24 397 7quot rquot 3 M 39 r a g b Output Resistance rod 39 yJquot 3 c Matching Considerations 1 V s VYJ C39anv b 39 394 V 39 V s W 11 I J5 J l l KIg3939 v s l r t 39 inalog Integrated Circuit Design 31 QZ i C H39A VJh AoV 51 2 First order 4 Recall for bipolar Ass 1quot km 139 neglecting early effects Top view of MOS transistor 3971 BK Vn v39l z I r n5 so l I Pt 0T L W Accuracy of MOS Current Mirror w I quot39 AI n as 0 4 TIA 0 Suppose VDSI VDSZ Thenwe want A 12 L L2 Design current mirror so L1 L2 ex hCE l LAZ39VJ Q l A VA w W m k YM 39I39d39JJa u 39 malog Integrated Circuit Design 39139L Poo A I m 1 3 r 39I39 d 2 w L a I wMu Qjquot43 11quot M I L AL 4 H 67 MI DA Maquot 2wMI 2o H quotZw c a quot ElfLonst Do 140 west 3 um39o l 3 I 4 quott m 41 3 H w NI t ww M15 mz39 23 3 AJ Au aem 63 6mm Mm MI I30 KA39n39o 1 Matching Considerations for Bipolar Current Sources Mismatches inaF IS RE39s an Q3 Inf Fan Q9 131 E1 VB39V39A IMquot F4 H Subtraction of those currents yields 3392 55 4 29 0 Vrlmzur Wlm yqala 4134 1 54 39 133 9 FqF4 M gage 39 v lXnalog Integrated Circuit Design Suppose A k2 7L but VDSI at VDsz Error Term E 1 MVDSI VDSI Want 1 small L1 L2 Long Devices Ia ws hm39r 1 n1 quot we 1 7 V s Process Variations a Random u fow J Pol quot i 4 it 7 A Typical random variations for W and L 01 p Statistically distributed Variations in all parameters a L K 7 VTn b Systematic Biased Over etch diffusion mask error overexposed mask All edges equally affected AW AL Process gradients tox gas ow pwell in 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