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by: Sam Robel


Sam Robel
GPA 3.68


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Class Notes
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This 64 page Class Notes was uploaded by Sam Robel on Monday October 19, 2015. The Class Notes belongs to ECE 323 at Oregon State University taught by Staff in Fall. Since its upload, it has received 32 views. For similar materials see /class/224427/ece-323-oregon-state-university in Engineering Electrical & Compu at Oregon State University.

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Date Created: 10/19/15
National Semiconductor LM741 Operational Amplifier General Description The LM741 series are general purpose operational amplifi ers which feature improved performance over industry stan dards like the LM709 They are direct plugin replacements for the 7090 LM201 M01439 and 748 in most applications The amplifiers offer many features which make their appli cation nearly foolproof overload protection on the input and November 1994 output no latchup when the common mode range is ex ceeded as well as freedom from oscillations The LM741CLM741E are identical to the LM741LM741A except that the LM741CLM741E have their performance guaranteed over a 0 C to 70 C temperature range in stead of 55 C to 125 C Schematic Diagram 3 2 INVERTING NONINVERTING INPUT 01 f INPUT 03 l1 Q4 07 J OFFSET NULL Z v 08 09 012 013 1 014 1 R5 gt 39K M VV R7 015 45K 01 1 30pF R8 0 R9 75K 1 25 AA VV I p 5 15 oOUTPUT 3 R10 50 1 017 06 010 l 05 011 ozil Iozo 1 5 OFFSET NULL R1 R3 R2 R4 5 R12 1 R11 1K gt50K 1K 5K 50K quot50 4 H v v V Offset Nulling Circuit 3 TLH9341 1 TLH9341 7 1995 National Semiconductor Corporation TLH9341 RRD BSOM115Printed in U S A 161111de Ieuonwedo mm Absolute Maximum Ratings If MilitaryAerospace specified Distributors for availability and specifications te 5 LM741A Supply Voltage 22V Power Dissipation Note 1 500 mW Dillerential input Voltage 30V input Voltage Note 2 15V Output Short Circuit Duration Continuous 755 C10 125 C 765 Cto 150 C Operating Temperature Range Storage Temperature Range LM741E i 22V 500 mW 30V i 15V Continuous 0 C to 70 C 765 C to 150 C devices are required please contact the National Semiconductor LM741 i22V 500 mW 30V i15V Continuous 759C 10 125 C 765 C to 150 C LM741C 18V 500 mW 30V 15V sales Office Continuous 0 C to 70 C 7 65 C to 150 C Junction Temperature 150 C 100 C 150 C 100 C Soldering inlormation ackage 10 seconds 260 C 260 C 260 C 260 C J or HPackage 10 seconds 300 C 300 C 300 C 300 C P ck e Vapor Phase 60 seconds 215 C 215 C 215 C 215 C inlrared 15 seconds 215 C 215 C 215 C 215 C See AN450 Surlace Mounting Methods and Their Eflect on Product Reliabilityquot lor other methods ol soldering surlace mount devices ESD Tolerance Note 6 400V 400V 400V 400V Electrical Characteristics Note 3 Parameter Conditions LM7 1ALM741E LM741 M741 Units Min Typ Max Min Typ Max Min Typ Max input Ollset Voltage TA 25 C Rs S 10 kn 10 50 20 60 mV Rs S 509 08 30 mV TAMIN S TA S TAMAx Rs son 40 mV Rs 10 kn 60 75 mV Average input Ollset a Voltage Drilt 15 PV C a input Ollset Voltage TA 25 C Vs 720V 10 15 15 mv Adlustment Range input Ollset Current TA 25 C 30 30 20 200 20 200 nA TAMIN TA TAMAX 70 55 500 300 nA Average input Ollset a Current Drilt 0395 IV C input Bias Current TA 25 C 30 80 80 500 80 500 nA TAMIN TA TAMAX 0210 15 05 0A input Resistance TA 25 C Vs 20V 10 60 03 20 03 20 Mn TAMIN S TA S TAMAX VS HOV 05 Mn input Voltage Range TA 25 C 12 13 V TAMINSTASTAMAX 12 13 V Large Signal Voltage Gain TA 25 C RL 2 2 kn V i20V Vo i15V 50 VmV Vs i15V Vo 10V 50 200 20 200 VmV TAMIN S TA S TAMAX RL 2 2 kn vs 20v0vo 15v 32 VmV vs 15v0vo 10v 25 15 VmV vS 5v vo 2v 10 VmV Electrical Characteristics Note 3 Continued LM741ALM741E LM741 LM741C Parameter Conditions Units Min Typ Max Min Typ Max Min Typ Max Output Voltage Swing Vs 20V RL 2 1o kn 16 v RL 2 2 kn 15 V vs 15V RL210kn 12 14 12 14 V RL22k 10 13 10 13 V Output Short Circuit TA 25 C 10 25 35 25 25 mA Current TAMIN TA TAMAX 1o 40 mA CommonMode TAMIN TA T Rejection Ratio Rs 1o kn VGM 12v 70 90 70 90 dB Rs 5021ch 12V 50 95 dB Supply Voltage Rejection TAMIN TA TAMAXgt Ratio Vs 20V to Vs 5V RS S 5 86 96 dB RS S 10 kn 77 96 77 96 dB Transient Response TA 25 C Unity Gain Rise Time 025 08 03 03 as Overshoot 60 20 5 5 Bandwidth Note 4 TA 25 C 0437 15 MHZ Slew Rate TA 25 C Unity Gain 03 07 05 05 Vps Supply Current TA 25 C 17 28 17 28 mA Power Consumption TA 25 C VS 20V 80 150 mW VS i 15V 50 85 50 85 mW LM741A VS i 20V TA TAMIN 165 mW TA TAMAX 135 mW LM741 E vS 20v TA TAMIN 150 mW TA TAMAX 150 mW LM741 vs 15V TA TAMIN so 100 mW TA TAMAX 45 75 mW Note 1 For operation at eievated tempevatuves these dewees must he devated based on thermai veststahee and TJ max itsted under Absoiute Maxtmum Ratingsquot TJ TA 91A PD Cerdip 1 DIP N HOB H 5013 M i eJA Junction to Ambient moow tDD CW t7D CW 195 CW 910Juncttonto Case NA NA 25 CW NA me r 1 W than 15v to the suppiy voitage e uhtess otherwtse speemed these Speciiicaiions appty iost 15v 55 lt TA lt 125 LM7AtLM7A1A For the LM7AtCLM7ME these Speciiicaiions aveitmttedt 010 lt T lt 7010 Note 4 Caicuiated vaiue ivom aw MHz 035R1se Timeps Note 5 Human body modet 15 ha m sevtes wtth 100 pF Connection Diagrams Metal Can Package TLH9341 2 Order Number LM741H LM741H883 LM741AH883 or LM741CH See NS Package Number H080 DualInLine or 80 Package V OFFSET NULL 1 8 NC INVERTING INPUT 2 7 V NONINVERTING 3 6 0UTPUT INPUT V39 4 5 0FFSET NULL TLH9341 3 Order Number LM741J LM741J883 LM741CM LM741CN or LM741EN See NS Package Number J08A M08A or N08E LM741 H is available per JM3851010101 Ceramic DuallnLine Package NC i U 14 NC NC Z I3 NC 0FFSET NULL 3 12 NC lN 4 11 V IN 5 10 OUT V 6 9 0FFSET NULL NC 7 8 NC TLH9341 5 Order Number LM741J14883 LM741AJ14883 See NS Package Number J14A also available per JM3851010101 Malso available per JM3851010102 Ceramic Flatpak NC 0 NC 0FFSET NULL NC NPUT LM741w v NPUT OUTPUT V OFFSET NULL TLH9341 6 Order Number LM741W883 See NS Package Number W10A Physical Dimensions inches millimeters lt 0350 0370 88909398 B 0315 0335 0001 0509 MAX 0025 01050105 a 0635 ngggwusn 41914699 I l v REFERENCE PLANE it 0035 7 if 7 78mm PLANE 0500 1339 t 0015 0040 11270 MAX 0381 11316 7 0016 0019 A 1 wi406039483 DIA TYP 0195 0205 001 0100 4053 5207 PC 2540 quotP 0029 0045 0737 1143 0020 0034 0115 0145 2921 3683 DIA W 4 45 EuuALLY SPACED Metal Can Package H Order Number LM741H LM741H883 LM741AH883 LM741CH or LM741EH NS Package Number H080 HUBC REV E Physical Dimensions inches millimeters Continued i 0400 MAX gt R0010 TYP m 171 ITI m l i 0220 0510 MAX 0291 GLASS R0025 TYP I I ILIILIILIILI 0045 gt 0065 TYP 0290 lt 0005 GLASS 0320 MIN SEALANT I I I I pI 0200 39 MAX MAX T 0050 39 f I 0150 I 0125 MIN 0200 I 90 l 4 TYP l 95 l 5 TYP II 0510 39 0055 MAX gt NI 0410 39I BOTH ENDS I39 0003 TYP J L 0013 I 0003 TYP 0012 0100 I 0010 TYP 1031sz K Ceramic DuallnLine Package J Order Number LM741CJ or LM741J883 NS Package Number J08A 0705 10939 MAX mm W T30 Ti l l l Tl m 352 0220 0310 5530 1874 D1 Iii Iii Ill Lil Iii LTJ 0290 0320 01105 A 0200 73553323 10 Fuss 0000 iDDU5 m h Arm 15240127 MAX 0020 0000 0100 M i 39 0500 1524 4512 WWW 1 ii 10 MAX 39Dll18 0D12 M F 0310 0410 02030005 LF187410411 W L 333335ll 1112511209 m6quot 39 13475 5080 MAX BOTH ENDS quot100 i011quot M50 2540 0254 m MIN 01411111015110 Ceramic DuallnLine Package J Order Number LM741J14883 or LM741AJ14883 NS Package Number J14A Physical Dimensions inches millimeters Continued 0150 0157 3010 1903 0010 0020 X450 02544508 3 MAX TYP ALL LEADS 0109 D197 4000 51104 8 M 0220 0244 5791 6198 9 MMAX 0254 H U 1 2 3 LEAD No1 4 30 10501 W 0053 0069 1046 1153 0004 0010 0102 0254 LmU n i f 0004 f A f 0102 0014 ALL LEAD TIPS 13154350 0356 1111103 m Small Outline Package M Order Number LM741CM NS Package Number M08A 0373 0400 9474 1016 0090 2286 M 01A 2337 FIN 00 10ENT M 635i 0127 om 023 0040 gt MIN 7112 m MAX 1016 TYP I I 0300 0320 0752 0 0 762 3128 2 950150 A 0125 0000 0015 gt lt 3175 0229 0381 BIA NIJM 0325g39g 139g 1015 55 4331 0100i0010 2540i0254 DuallnLine Package N Order Number LM741CM or LM741EN NS Package Number N08E i SEATING f PLANE 0014 0020 gt lt TYP 0356 0508 0008 TYP 0203 MOBA REV H 003210005 0813 t 0127 RAD PIN N0 1 WENT OPTION 2 0145 0 200 3603 5080 NOSE REV F LM741 Operational Amplifier Physical Dimensions inches millimeters Continued LIFE SUPPORT POLICY 0080 0055 0035 0026 TYP 0006 0004 0270 MAX39gt 0050l0005 gtl llt gt lt 0005 MIN TYP TYP I I 10 6 I i 0270 MAX 0 GLASS 0238 I I DETAIL A PIN 1 IDENT ill I 5 0019 TYP gtl 0045 MAX 0015 TYP 10Lead Ceramic Flatpak W Order Number LM741W883 NS Package Number W10A 0012 0008 DETAIL A W10A REV E NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can effectiveness be reasonably expected to result in a significant injury to the user 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or b7 National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1800 2729959 Fax 1800 7377018 National Semiconductor Europe Hong Kong Ltd Fax 49 0180530 85 86 Email cnngetevm2nsccom National Semiconductor 13th Floor Straight Block Ocean Centre 5 Canton Rd Deutsch Tel 49 0180530 85 85 Tsimshatsui Kowloon English Tel 49 0180532 78 32 Hong Kong Francais Tel 49 0180532 93 58 Tel 852 27371600 Italiano Tel 49 0180534 16 80 Fax 852 27369960 National Semiconductor Japan Ltd Tel 810432992309 Fax 810432992408 National does not assume any respons bility for use of any circuitry described no circuit patent censes are implied and National reserves the right at any t me without notice to change said circuitry and specificat ons LM555LM555C Timer General Description The LM555 is a highly stable device for generating accurate time delays or oscillation Additional terminals are provided for triggering or resetting if desired In the time delay mode of operation the time is precisely controlled by one external resistor and capacitor For astable operation as an oscilla tor the free running frequency and duty cycle are accurately controlled with two external resistors and one capacitor The circuit may be triggered and reset on falling waveforms and the output circuit can source or sink up to 200 mA or drive TTL circuits Features I Direct replacement for SE555NE555 l Timing from microseconds through hours I Operates in both astable and monostable modes National Semiconductor Applications February 1995 Adjustable duty cycle Output can source or sink 200 mA Output and supply TTL compatible Temperature stability better than 0005 per C Normally on and normally off output Precision timing Pulse generation Sequential timing Time delay generation Pulse width modulation Pulse position modulation Linear ramp generator Schematic Diagram THRESHOLD CUNTROL VOLTAGE GNU TRIGGER RESET 7 DISCHARGE IJUTP UT TLH7851 1 1995 National Semiconductor Corporation TLH7851 HHD BSOM1 15Printed in U S A Jew GSSSIN39ISSSIN39I Absolute Maximum Ratings If MilitaryAerospace s ec lea e conlacl lhe vices are required d de Sem39conduclor sales 5 N l I OfficeDistributors for availabilin and specifications Supply Vollage Power Dissipalion Nole 1 LM555H LM555CH LM555 LM555CN Operaling Temperalure Ranges LM555C 760 mW 1 180 mW 0 C lo 70 C Slorage Temperalure Range 765 Clo 150 C Soldering lnlormalion DuallnLine Package Soldering 10 Seconds Small Oulline Package Vapor Phase 60 Seconds 215 C lnlrared 15 Seconds 220 C See AN450 Surlace Mounling Melhods and Their Ellecl on Producl Reliabililyquot lor olher melhods ol soldering sur lace mounl devices 260 C LM555 755 Clo 125 C Electrical Characteristics 29c v 5v lo 15v unless olhewise speci ed A CD Lirr ils Parameler Conditions LM555 LM5556 Unils Min Typ Max Min Typ Max Supply Vollage 45 18 45 16 V Supply Currenl v33 5v RL w 3 5 3 6 mA V33 15V RL w 10 12 10 15 mA Low Slale Nole 2 Timing Error Monoslable lnilial Accurac 05 1 Drill wilh Temperalure RA 1k lo 100 km 30 50 ppm C c 01 pFNo1e 3 Accuracy over Temperalure 15 15 Drill wilh Supply 005 01 N Timing Error Aslable lnilial Accurac 15 225 Drill wilh Temperalure RA RB 1klo 100 km 90 150 ppm c 01 pFNo1e 3 Accuracy over Temperalure 25 30 Drill wilh Supply 015 030 N Threshold Vollage 0667 0667 x V33 Trigger Vollage V33 15V 48 5 52 5 V V33 5V 145 167 19 167 V Trigger Currenl 001 05 05 09 pA ReselVoIlage 0 4 0 5 1 04 0 5 1 V Resel Currenl 01 04 01 04 mA Threshold Currenl Nole 4 01 025 01 025 LA Conlrol Vollage Level V33 15V 96 10 104 9 10 11 V V33 5V 29 333 38 26 333 4 V Pin 7 Leakage Oulpul High 1 100 1 100 nA Pin 7 Sal Nole 5 ulpul Low V33 15V 17 15 mA 150 180 mV Oulpul Low V33 45V 17 45 mA 70 100 80 200 mV Electrical Characteristics TA 25 C Vcc 5V to 15V unless othewise specified Continued Limits Parameter Conditions LM555 LM555C Units Min Typ Max Min Typ Max Output Voltage Drop Low Vcc 15V ISINK 10 mA 01 015 01 025 V I5NK 50 mA 04 05 04 075 V I5NK 100 mA 2 22 2 25 V ISINK 200 mA 25 25 V VCC 5V ISINK 8 mA 01 025 V ISINK 5 mA 025 035 V Output Voltage Drop High ISOURCE 200 mA Vcc 15V 125 125 V ISOURCE 100 mA VCC 15V 13 133 1275 133 V Vcc 5V 3 33 275 33 V Rise Time of Output 100 100 ns Fall Time of Output 100 100 ns Note 1 For operating at elevated temperatures the device must be derated above 25 C based on a 150 C maximum junction temperature and a thermal resistance of 164 cw TO5 106 cw DIP and 170 cw SO8 junction to ambient Note 2 Supply current when output high typically 1 mA less at VCC 15V Note 3 Tested at VCC 5V and VCC 5V Note 4 This will determine the maximum value of RA R3 for 15V operation The maximum total RA R3 is 20 Ma Note 5 No protection against excessive pin 7 current is necessary providing the package dissipation rating will not be exceeded Note 6 Refer to RETSSSSX drawing of military LM555H and LM555J versions for specifications Connection Diagrams Metal Can Package RESET Top View Order Number LM555H or LM555CH See NS Package Number H08C TLH7851 2 DuallnLine and Small Outline Packages GND Z TRIGGER 3 OUTPUT 4 RESET l Vac 7 DISCHARGE 6 THRESHOLD L CONTROL VOLTAGE Top View TLH7851 3 Order Number LM555J LM555CJ LM555CM or LM555CM See NS Package Number J08A M08A or N08E Typical Performance Characteristics MINIMUM PULSE WIDTH its PROPAGATION DELAV ns Minimuim Pulse Width Required for Triggering I 01 02 113 04 LOWEST VOLTAGE LEVEL OF TRIGGER PULSE X Vcci Low Output Voltage vs Output Sink Current 10 39smx MA Output Propagation Delay vs Voltage Level of Trigger Pulse 1200 T02539C a o a an o o m 1 a c a o N a a I 0 I11 02 03 LOWEST VOLTAGE LEVEL OF TRIGGER PULSE X Vcc PROPAGATION DELAY us VouT V SUPPLV CURRENT mA Vs mV PIN 7 Supply Current vs Supply Voltage 12 10 a N 10 15 SUPPLV VOLTAGE V at Low Output Voltage vs Output Sink Current 10 11 11 100 ISINK quotIU Output Propagation Delay vs Voltage Level of Trigger Pulse 1200 1000 300 Elli 400 200 I 11 Ill 02 113 LOWEST VOLTAGE LEVEL OF TRIGGER PULSE X Vac Discharge Transistor Pin 7 Voltage vs Sink Current 1000 ISINK mlU PIN 7 Vcc 4 VOUT V Vow V Vs mV PIN 7 High Output Voltage vs Output Source Current 2 13 16 14 39 12 1 00 00 04 02 I 1 10 100 ISOURCE MA Low Output Voltage vs Output Sink Current 10 10 01 001 1 0 10 100 sum quot1quot Discharge Transistor Pin 7 Voltage vs Sink Current 1000 m IIIIIIIII III 10 10 001 01 11 10 100 ISINK mAl PIN 7 TLH7851 4 Applications Information MONOSTABLE OPERATION In this mode of operation the timer functions as a oneshot Figure 1 The external capacitor is initially held discharged by a transistor inside the timer Upon application of a nega tive trigger pulse of less than 13 VCC to pin 2 the flipflop is set which both releases the short circuit across the capaci tor and drives the output high 5v TO 15v W i RESET CC 1 I I A 1 4 s TRIGGER DISCHARGE NURMALLY R o 2 7 quotONquot LOAD L THRESHOLD I LM555 e I CONTROL OUTPUT VOLTAGE 3 5 C NORMALLY R 1 1 quotOFFquot LOAD L 001 I TLH7851 5 FIGURE 1 Monostable The voltage across the capacitor then increases exponen tially for a period oft 11 RA C at the end of which time the voltage equals 23 VCC The comparator then resets the flipflop which in turn discharges the capacitor and drives the output to its low state Figure 2 shows the wave forms generated in this mode of operation Since the charge and the threshold level of the comparator are both directly proportional to supply voltage the timing internal is inde pendent of supply TLH7851 6 VCC 5V Top Trace Input 5V Div TIME 01 msDIV Middle Trace Output 5VDiv RA 91 km Bottom Trace Capacitor Voltage 2V Div C 001 0F FIGURE 2 Monostable Waveforms During the timing cycle when the output is high the further application of a trigger pulse will not effect the circuit so long as the trigger input is returned high at least 10 us be fore the end of the timing interval However the circuit can be reset during this time by the application of a negative pulse to the reset terminal pin 4 The output will then re main in the low state until a trigger pulse is again applied When the reset function is not in use it is recommended that it be connected to VCC to avoid any possibility of false triggering Figure 3 is a nomograph for easy determination of R C values for various time delays NOTE In monostable operation the trigger should be driv en high before the end of timing cycle 100 A 10 LI 3 5 1 2 E 0 E 01 lt O I 0 001 0001 10ys100uslms10m5100ms1s 1051005 id TIME DELAY TLH7851 7 FIGURE 3 Time Delay ASTABLE OPERATION If the circuit is connected as shown in Figure 4 pins 2 and 6 connected it will trigger itself and free run as a multivibrator The external capacitor charges through RA RB and dis charges through RB Thus the duty cycle may be precisely set by the ratio of these two resistors Vcc 1 lt RA 1 IVW u N J N gt lt lt an gt LM555 5 I F i 51 c I IlllluF I v 1 TLH7851 8 FIGURE 4 Astable In this mode of operation the capacitor charges and dis charges between 13 VCC and 23 VCC As in the triggered mode the charge and discharge times and therefore the frequency are independent of the supply voltage Applications Information Continued Figure 5 shows the waveforms generated in this mode of operation TLH7851 9 VCC 5V Top Trace Output 5V Div TIME 20 LSDIV Bottom Trace Capacitor Voltage 1VDiv RA 39 k R3 3 k C 001 F FIGURE 5 Astable Waveforms The charge time output high is given by t1 0693 RA RB C And the discharge time output low by t2 0693 RB C Thus the total period is T t1 t2 0693 RA 2RBC The frequency of oscillation is 1 144 7 RA 2 RB C Figure 6 may be used for quick determination of these RC values f RB The dut c cle is y y RA 2R3 100 10 C CAPACITANCE HF 001 A 2 RB 0001 01 1 10 100 1k 10k 10le f FREERUNNING FREQUENCY Hz TLH7851 10 FIGURE 6 Free Running Frequency FREQUENCY DIVIDER The monostable circuit of Figure 1 can be used as a fre quency divider by adjusting the length of the timing cycle Figure 7 shows the waveforms generated in a divide by three circuit TLH7851 11 V00 5V Top Trace Input 4VDiv TIME 20 LSDIV Middle Trace Output 2VDiv RA 91 kn C 001pF Bottom Trace Capacitor 2V Div FIGURE 7 Frequency Divider PULSE WIDTH MODULATOR When the timer is connected in the monostable mode and triggered with a continuous pulse train the output pulse width can be modulated by a signal applied to pin 5 Figure 8 shows the circuit and in Figure 9 are some waveform examples lTTT T W 4 RA 4 a gt 7 DISCHARGE TRIGGERO 2 LM555 6 THRESHOLD MODULATION INPUT OUTPUT o 3 5 o 1 l L TLH7851 12 FIGURE 8 Pulse Width Modulator TLH7851 13 V00 5V Top Trace Modulation 1VDiv TIME 02 msDIV Bottom Trace Output Voltage 2VDiv RA 91 kn C 001 pF FIGURE 9 Pulse Width Modulator PULSE POSITION MODULATOR This application uses the timer connected for astable opera tion as in Figure 10 with a modulating signal again applied to the control voltage terminal The pulse position varies with the modulating signal since the threshold voltage and hence the time delay is varied Figure 11 shows the wave forms generated for a triangle wave modulation signal Applications lnformation Continued if 139Vm 1 RA 4 2 7 P R B LM555 5 MODULATION 0UTPUTO 3 5 O TLH7851 14 FIGURE 10 Pulse Position Modulator TLH7851 15 V00 5V Top Trace Modulation Input 1VDiv TIME 01 msDIV Bottom Trace Output 2VDiv RA 39 km R3 3 kn C 001 MF FIGURE 11 Pulse Position Modulator LINEAR RAMP When the pullup resistor RA in the monostable circuit is replaced by a constant current source a linear ramp is gen erated Figure 12 shows a circuit configuration that will per form this function TRIGGER 2 2N4250 DR EQUIV LM555 5 ourruro a 5 c TLH7851 16 FIGURE 12 Figure 13 shows waveforms generated by the linear ramp The time interval is given by 23 VCC RE R1 R2 C R1VCC VBE R1 R2 VBE 2 06V TLH7851 17 V00 5V Top Trace Input 3VDiv TIME 20 MSDIV Middle Trace Output 5VDiv R1 47 k9 Bottom Trace Capacitor Voltage 1V Div R2 100 kn RE 27 kn C 001 MF FIGURE 13 Linear Ramp 50 DUTY CYCLE OSCILLATOR For a 50 duty cycle the resistors RA and RB may be connected as in Figure 14 The time period for the out Applications Information Continued put high is the same as previous t1 0693 RA C For the output low it is t2 RB ZRA R R R R C In A BA 8 ZRBiRA Thus the frequency of oscillation is f 11 12 O Vrzc lt R 51k 3 22 2 7 AVAVA LM555 6 OUTPUT o 3 5 c 1 now I 001uF TLH7851 18 FIGURE 14 50 Duty Cycle Oscillator Physical Dimensions inches millimeters Note that this circuit will not oscillate if R3 is greater than 12 RA because the junction of RA and RB cannot bring pin 2 down to 1 3 VCC and trigger the lower comparator ADDITIONAL INFORMATION Adequate power supply bypassing is necessary to protect associated circuitry Minimum recommended is 01 iiiF in parallel with 1 pF electrolytic Lower comparator storage time can be as long as 10 MS when pin 2 is driven fully to ground for triggering This limits the monostable pulse width to 10 MS minimum Delay time reset to output is 047 MS typical Minimum reset pulse width must be 03 its typical Pin 7 current switches within 30 ns of the output pin 3 voltage lt 11350 0370 88909398 DIA M M 8001 8509 MAX 0025 mas0185 a 0635 ngggltrusn 41914599 I 39 77v REFERENCE PLANE it o 035 7 7 f 78mm PLANE 0500 1339 0015 0040 1270 MAX 0381 1016 w 0100 2540 mm0045 0737 1143 0028 0034 W 4 45 EDUALLY SPACED gt A 1 DIA TYP BABE 0483 0195 0205 DIA 4953 5207 RC 0115 0145 2921 3683 DIA HUBC REV E Metal Can Package H Order Number LM555H or LM555CH NS Package Number H08C Physical Dimensions inches millimeters Continued i 0400 MAX gt R0010 TYP W W ITI m l i 0220 0510 MAX 0291 GLASS R0025 TYP l l ILIILIILIILI 0045 gt 0065 TYP 0290 lt 0005 GLASS 0320 MIN SEALANT 0180 T I I I 1 0200 4 0020 MAX MAX 0050 f 1 0150 39 0125 MIN 0200 I A 90 l4 TYP 95 l 5 TYP II 0510 39 0055 MAX gt I 0410 39I BOTH ENDS a 0008 0018l0003 TYP 0012 TYP 0100i0010 TYP JogA REV K Ceramic DuallnLine Package J Order Number LM555J or LM555CJ NS Package Number J08A A 0139 0197 4300 5004 113 0220 0244 5791 0190 MMAX 0254 LEAD No1 1 2 3 4 IDENT 3 0150 0157 39 3010 3303 39 0010 0020 a w MW 1346 1153 3 MAX m 0004 0010 ALL LEADS 0102 0254 f i Lexy 0124 7 SEATlNG f m I A f 11 f PLANE 0102 0014 0008 0010 0050 0014 0020 ALL LEAD TIPS 0356 gt TYP gggaL o ms gt mfgggg 1 1210 0008 0356 0508 L L AD TYP ALL LEADS TYP mTYP lt M08AREV H Small Outline Package M Order Number LM555CM NS Package Number M08A LM555LM555C Timer Physical Dimensions inches millimeters Continued 0373 0400 0474 1016 0090 2286 10320005 0002 A 2337 00130127 PIN N0 1 IDENTW i quot25quot 39 5 RAD I 535i01127 PIN No 1 IDENT Ill IAI Lil I4I 0280 0040 gt lt 7112 mm 0030 MAX 1 016 TYP gtI 0PTION2 0 300 0 320 0752 L033 M 39 quot 2l i1 gt lt 1099 3 6335 030 762 0126 I quotquot v quot 39l 013010005 i j l l 30020127 950550 0125 0140 f 0065 3175 3556 T 25 m 90 4 m Lung 0015 39 0500 lt 3175 0229 0301 39 I I TYP MIN 0040 quot0 gt w quot325 4015 0457i0076 1015 20m 55 4301 2540 0254 r i ffai l n lt 0060 0050 39 1524 39gt 1270 an REV F Molded DuallnLine Package N Order Number LM5550N NS Package Number N08E LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to c support device or system or to affect its safety or effectiveness ause the failure of the life National Semiconductor National Semiconductor Corporation Europe 1111 West Bardin Road Fax 49 0180530 85 86 Arlington TX 76017 Email cnngetevm2nsccom Tel 1800 2729959 Fax 1800 7377018 Deutsch Tel 49 0180530 85 85 English Tel 49 0180532 78 32 Frangais Tel 49 0180532 93 58 Italiano Tel 49 0180534 16 80 National Semiconductor Hong Kong Ltd 131h Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kon Tel 852 27371600 Fax 852 27369960 National Semiconductor Japan Ltd Tel 810432992309 Fax 810432992408 National does not assume any respons bility for use of any circuitry described no circuit patent censes are implied and National reserves the right at any t me without notice to change said circuitry and specificat ons December 1994 National Semiconductor ADC0801ADC0802ADC0803ADC0804ADC0805 8Bit juP Compatible AD Converters General Description The ADCOBO1 ADCOBOZ AD00803 ADCOBO4 and ADCOBOS are CMOS 8bit successive approximation A D converters that use a differential potentiometric ladder similar to the 256R products These converters are de signed to allow operation with the NSCBOO and IN88080A derivative control bus with TFtISTATE output latches di rectly driving the data bus These ADs appear like memory locations or IO ports to the microprocessor and no inter facing logic is needed Differential analog voltage inputs allow increasing the com monmode rejection and offsetting the analog zero input voltage value In addition the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution Differential analog voltage inputs Logic inputs and outputs meet both M08 and TTL volt age level specifications Works with 25V LM336 voltage reference Onchip clock generator 0V to 5V analog input voltage range with single 5V supply No zero adjust required 03quot standard width 20pin DIP package 20pin molded chip carrier or small outline package Operates ratiometrically or with 5 VDC 25 VDC or ana log span adjusted voltage reference Key Specifications Features I Resolution 8 bits I Compatible with 8080 MP derivatives no interfacing 39 Total er or I 54 L88 52 L88 and i1 LSB logic needed access time 135 ns l ConverSIon time 100 us I Easy interface to all stand alone microprocessors or operates Typical Applications TRANSDUCER BIT RESOLUTION OVER ANV DESIRED ANALOG INPUT VOLTAGE RANGE SEE SECTION 241 ViiiiM INPUTS 7 VmIi 8 A GND SPAN ADJ SECTION 241 VREFZ D GND TLH5671 1 8080 Interface Error Specification Includes FullScale Zero Error and NonLinearity Part vREFz 2500 ch vREFz No Connection Number No Adjustments No Adjustments mm Adjusted ADCOBO1 i 14 L88 ADCOBOZ i 12 L88 ADCOBOs i 12 L88 ADCOBO4 i1 LSB ADCOBOS i1 LSB TLH5671 31 TFlI STATE is a registered trademark of National Semiconductor Corp 2 80 is a registered trademark of Zilog Corp 1995 National Semiconductor Corporation TLH5671 FIRD BSOM1 15Printed in U S A SJeiJeAuoo av eiqtiedwoo ciii tie8 90800CIVI70800CIVSO800CIVZO8OOCIV l 0800CIV Absolute Maximum Ratings Notes1 112 If MilitaryAerospace s ec ied devices are required lea e contact at39 nal Semic Storage Temperature Range 765 C to 150 C 5 quot 9 N ndu 3907 sales Package Dissipation at TA 25 C 875 mW OfficeDistributors for availability and specifications ESD Suscep bimy Nae 10 80W Supply Voltage V33 Note 3 6 V age r tin R tin N 1 1amp2 Logic Control inputs 703v to 1sv 9pe a n9 a gs es T ltT ltT AtOther r 4 r 703w r We A7 MAX Lead Temp Soldering 10 seconds W ADC080102LJ ADC0802LJ883 essachA 125 c Dualin Line Package Plastic zeoac Agggggljgzjggjg g gig1 25 Dualin Line Package ceramic 300 C DCOBOZLCZN 5 4OOCltTA2 730 A 5 309 M quot PaCkage a ADC08020304LCV oachA 7crc vap quot Phase 60 sewn 2 5f ADC08020304LCWM oach 7cm inirared 15 seconds 220 C Range 039 V66 45 VDG 10 63 VDG Electrical Characteristics The iollowing specilications apply ior V33 5 V33 TMINSTASTMAX and i3LK 640 kHz unless otherwise specilied Parameter Conditions Min Typ Max Units ADC0801 Total Adjusted Error Note 8 With FullScale Adj y LSB See Section 252 7 ADC0802 Total Unadjusted Error Note 8 VREF2 2500 VD3 yz LSB ADC0803 Total Adjusted Error Note 8 With FullScale Adj y2 LSB See Section 252 ADC0804 Total Unadjusted Error Note 8 VREF2 2500 V33 1 LSB ADC0805 Total Unadjusted Error Note 8 VREF2No Connection 1 LSB VREF2 input Resistance Pin 9 ADC0801020305 25 80 kn ADC0804 Note 9 075 11 kn Analog input Voltage Range Note 4 V or V ind 005 V33 005 VD3 DC CommonMode Error Over Analog input Voltage y r LSB Range Power Supply Sensitivity v i 10 Over wE x LSB Allowed mm and VINE Voltage Range Note 4 AC Electrical Characteristics The iollowing specilications apply ior V33 5 VD3 and TA 25 C unless otherwise specilied symbol Parameter Conditions Min Typ Max Units T3 Conversion Time i3LK 640 kHz Note 6 103 114 ps T3 Conversion Time Note 5 6 66 73 1i3LK i3LK Clock Frequency V33 5V Note 5 100 640 1460 kHz Clock Duty Ocle Note 5 40 60 CR Conversion Rate in FreeRunning MR tied to Wwith 8770 9708 convs Mode 0 V i3LK 640 kHz twmn Width oi W input Start Pulse Width a 0 VD3 Note 7 100 ns 1A33 Access Tifme Delay irom Falling CL 100 pF 135 200 ns Edge oi RDto Output Data Valid 1 10 TRiSTATE Control DJIay L 10 F RL 0 125 200 ns irom Rising Edge oi RD to See TRiSTATE Test HiZ State Circuits lWL 1m Delay irom Falling Edge 300 450 ns oim orWto Reset oi iNTR CIN input Capacitance oi Logic 5 75 pF Control inputs cOUT TRiSTATE Output 5 75 pF Capacitance Data Buiiers CONTROL INPUTS Note CLK iN Pin 4 is the input oi a Schmitt trigger circuit and is thereior VIN 1 Logical 1quot input Voltage V33 Except Pin 4 CLK W 525 VD3 01 lt D n AC Electrical Characteristics Continued The lollowing specilications apply lor V33 5VD3 and TMIN S TA S TMAXgt unless otherwise specilied symbol Parameter Conditions Min Typ Max Units CONTROL INPUTS Note CLK lN Pin 4 is the input ol a Schmitt trigger circuit and is therelore specilied separately VIN 0 Logical 0quot input Voltage V33 475 VD3 08 VD3 Except Pin 4 CLK lN llN 1 Logical 1quot input Current VIN 5 VD3 0005 1 pAD3 All inputs W 0 Logical 0quot input Current VIN 0 V33 1 70005 pAD3 All inputs CLOCK IN AND CLOCK R VT CLK lN Pin 4 Positive Going 27 31 35 VD3 Threshold Voltage VTi CLK lN Pin 4 Negative 15 18 21 VD3 Going Threshold Voltage VH CLK lN Pin 4 Hysteresis 06 13 20 VD3 VT VT VOUT 0 Logical 0quot CLK R Output lo 360 LA 04 VD3 Voltage V33 475 VD3 VOUT 1 Logical 1quotCLK R Output lo 7360 LA 24 VD3 Voltage V33 475 VD3 DATA OUTPUTS AND INTR VOUT 0 Logical 0quot Output Voltage 0 tputs Data u lour 16 mA V33 475 VD3 04 VD3 lNTR Output lour 10 mA v33 475 VD3 04 VD3 VOUT 1 Logical 1quot Output Voltage lo 7360 HA V33 475 VD3 24 VD3 VOUT 1 Logical 1quot Output Voltage lo 710 HA V33 475 VD3 45 VD3 lour TRlSTATE Disabled Output VOUT 0 V33 73 pAD3 Leakage All Data Bullers VOUT 5 V33 3 pAD3 lSOUR3E VOUT Short to and TA 25ac 45 6 mAD3 lsNlt VOUT Short to V33 TA 25 C 90 16 mAD3 POWER SUPPLY l33 Supply Current includes l3LK 640 kHz Ladder Current VREFZ NC TA 25 C and a 5V ADCOBO1020304LCJ05 11 18 mA ADCOBO4LCNLCVLCWM 19 25 mA Note ills dsuios beyond iis sosoiiisd ooslaiing conditions Nols 2 All Tlls ssoalais A lo ills D Grid Nols 3 A zsnsl diods exlsls inislnally ilom v00 io Grid and llas a typical bieakdown uoliags oi 7 VDG Nols 4 FDVViN gt ViNlhe digiial output oods Will be 0000 0mm iolwalu n ills n l iii 00 lsusls 45V i Tlls p g p my a soso allows 50 mv iolwald bias oi siillsl diods Tllis msans illai as long as ills analog viN doss noi sxossd ills supply uoliags by mols illan 50 mv ills output oods Will be oonsoi iiag i 4950 V33 ousl ismoslaiuls uanaiions iniiial iolslanos and loading Nols 5 Aooulaoy is gualanissd ai is 640 KHz Al lligllsl lime iill i a i illan 275 ns sian lsgussi is inislnally laiollsd sss Flguls 2 and ssoiion 20 Nuts 7 Wain inill ills oonusrlsi in a isssi mods and ills siarl ol oonusision is iniiiaisd by ills low io lligll iiansiiion ol ills W pulss sss iiming diagiams Note is Nons o Nols 9 Tlls VREFZ pin is ills osnisl point oi a lworveslslm diuidsl oonnsoisd ilom V331o glound in all uslsions oi ills ADcosoi ADcosoz ADcosos and ADcosos and in ills ADCDBDALCJ saoll lssisiol is typically 16 m in all uslsions oi ills ADCDBDA except ills ADCDBDALCJ saoll lssisiol is typically 22 m Nols ID Human body modsl 100 pF disollalgsd illlougll a 15 kn lssisiol Typical Performance Characteristics ICLK kHz LOGIC INPUT THRESHOLD VOLTAGE V OUTPUT CURRENT mAI Logic Input Threshold Voltage vs Supply Voltage 450 475 500 525 550 vcc sumv VOLTAGE vac fCLK vs Clock Capacitor 1000 100 10 100 1000 CLOCK CAPACITOR BF Output Current vs Temperature 3 04 2 50 25 0 25 50 75 100 125 TA AMBIENT TEMPERATURE C OELAV ns LINEARITV ERROR LSBS lcc POWER SUPPLY CURRENT mADcI Delay From Falling Edge of R D to Output Data Valid vs Load Capacitance CLK IN THRESHOLD VOLTAGE V 0 200 400 600 800 1000 LOAD CAPACITANCE FF FullScale Error vs Conversion Time Tc E 3 E D E I u c a II D Tc CONVERSION TIME us Power Supply Current vs Temperature Note 9 t a 13 a O n I W gt I I 5 s l 50 25 0 25 50 75 I00 125 TA AMBIENT TEMPERATURE C CLK IN Schmitt Trip Levels vs Supply Voltage I 450 475 500 525 550 vcc sumv VOLTAGE chl Effect of Unadiusted Offset Error VS VREF2 Voltage 15 2 mV THIS FOR A ZERO ADJ IF 001 01 10 5 VREFZ vac Linearity Error at Low VREF 2 Voltages AND FULL 1 SB VALUE mV I 480 10 977 9 122 12 0 1 2 25 VREFZ VOLTAGE VDc TLH5671 2 TRlSTATE Test Circuits and Waveforms t1H t1H CL 10 PF t0H t0H CL 10 PF V V Vcc cc cc W DATA 1le CS OUTPUT RD cs DATA gt 0H CL 10k V0 90 OUTPUT Vcc DATA cl DATA OUTPUTS OUTPUTS a g 8ND VOL 1 W tr 20 ns tr 20 n6 TLH5671 3 TImIng Dlagrams All timing is measured from the 50 voltage points START CONVERSION E WR e th lt 39gt twiw Rn lt BUSY ACTUALINTERNAL K DATAIS VAme quot OUTPUT LATCHES STATUS OF THE NOT BUSY CONVERTER 1T0 a x lfCLK lt INTERNAL Tc gt LAST DATA WAS READ III R LAST DATA WAS NOT READ I INT ASSERTED Output Enable and Reset INTR INTR RESET W W nmf TBE I OUTPUTS r 7 gt 1A t 1 lt gt 1H UH TLH5671 4 Note Read strobe must occur 8 clock periods 8fCLK after assertion of Interrupt to guarantee reset of INTR Typical Applications Continued 6800 Interface Ratiometric with FullScale Adjust Vcc 5 Vac 0 xon 39 quot I j v I V VIIIM cc I I J I 1 I l I 32k L I c I quotr R IUMF I I 4 L 1 AIJ 39 I 01 I l I 1 I I 1 I v H v 12 t 39 39 I J m net I I l E quot quot DVTIDNAL 31139quot rs ADJUST Note before using caps at VIN or VREF2 39539 see section 232 Input Bypass Capacitors Absolute with a 2500V Reference Absolute with a 5V Reference Vcc v v 5 Vac v93quot 0 quot 391 39 l 039 VmM 39u o vmw u 39 L mur tour a l T 39 gt 1quot I I l AID 12k gm 1 m I J I I l I 2k 1 2 I p I 500 Vtquot 0 VmH VREFI thl VIMz 39 J I 3939 fquot m L J mass F OPTIONAL Am rs ADJUST For low power see also LM38525 139 e ZeroShift and Span Adiust 2V VIN g 5V Span Adiust ovg VIN g 3V Vi i no III was Vm Vcc vm VmW Vcc T10 I vm I In T 1on 39 39 2n AIJ 2 quot quot m 12 mm I I mass I VIM Vnsru I lit I I s 7L v H v 2 I Lav 4 ADJ I 39quot Hquot mm I r 1MP I sns zenu m I snsvmuc sun 39 can vonAsE v v v AVAquot s5 sscnou u 1k LJ 2V0 1 1 m zzno ADJ TLH5671 5 Typical Applications Continued Directly Converting a LowLevel Signal va av g vm g 512 mV va Vcc 5 vac Vcc AD VREFZ 24k AAA vvv r LMBSG 39k quot5VucC v v v 39 v v v v v v 100 Vos 1quot ADJ quot1 VREFZ 256 mV 1 mV Resolution with HP Controlled Range VREFZ 128 mV g ggc 1 L88 1 mV VDAciVN VDAc 256 mV 2500 vac RBIT DAC Minnomcm nAcoaan VnAc A MP lnterfaced Comparator VINW 0 Vm Vcc AD VREFZ For VNgtVN Output For VNltVN Output VmW AD va vnEFzt D ATA BUS 0 S VDAC lt 25V Digitizing a Current Flow A v N r 2 1k SPAN rms FFHEX 00HEX sunvnc 6 Vcc CR 21 a 39LOAD 2A FULLSCALE was 77 mo lel Vcc Z4 k 2k AD mu 3 mass zzno lt vmm vanz ADJ 4 b j 120k Vcc 5vnc T 1 TLH5671 6 Typical Applications Continued MD 1 ND 2 SelfClocking Multiple ADs NC 0 ELK A cum cu in All 5quotquot CLK m m 0 CLK n 3 pF Use a large R value gt CNNquot to reduce loading at CLK R output v IF MORE TuAusAomTiouAL ADs usE A was BUFFER NOT 1le SelfClocking in FreeRunning Mode 0 VmM CLK n O VmH mquot CLK m a Am I 150 pF R W W no sTAnT After powerup a momentary grounding of the W input is needed to guarantee operation SVS RESEI l 8 Operating with Automotive Ratiometric Transducers Vcc 5 Von lel Vcc lt vmi i39 AID 3k 51000805 VnEEZ T39 12 LMJEBA 0 35 vcc ILAI VIN 015 V00 15 Of V00 VXDR 85 Of V00 4 IHF D 1 F 1 quotI ADJ D 39 llk gt IL A u v 5 External Clocking 39CLK AD 39cLK gt cLK m 100 kHzifCLKi1460 kHz MP Interface for FreeRunning AD 0 E anmpr 7 i RESET AGE v AID CLKR 4 Ex quot xagn 10k V 7 W CLKIN Taopr READY TOM l ye mxmm v07 I PREVENTSRD nunmn An DATA UPDATE To RESET quot2 we RESET Ratiometric wuth VREF 2 Forced V isvnci mm quot vmm v I TM 2 b 1 man Mn 4 12 mam lel vnEFz i 7 gt if tm TLH5671 7 use 0 mm mm AID o vmi i VnErZ DB7 1 for VNgtVN hysteresis is not needed HOV 1 wkquot 4 5 VIII Vcc VIN V Iwu AID VmH Beckman Instruments 6943R10K resistor array Typical Applications Continued I See Figure 5 to select R value Handling i1OV Analog Inputs m gt i r vi OUTPUT V ELK D FF 12 LMJEEA uP Compatible DifferentialInput Comparator with PreSet V05 with or without Hysteresis Vcc 5 V93 1 5k 12 304016 VREF 2 Omit circuitry within the dotted area if Vcc 5 Vac LM335 II A quotF LMJIG vr on vos 1le LowCost uP lnterfaced TemperaturetoDigital Converter Vcc SVDc VIN quotu 1 TM AID 5Vnc blllk r rill 4 v H n TAM Ani 39quot quotquot5quot 391 Am 1 Vcc 5 VDcl Can calibrate each sensor to allow easy replacement then AD can be calibrated with a preset input voltage uP lnterfaced TemperaturetoDigital Converter IIJ L 39 I 3k A vv TA 1 ouu I vv v 39 VmM u LM335 zsavezrc I 1umV K 39quotquot 10w E 39 39 AD 25V 1k TA Mlquot VIN quotHUM ADJ Circuit values shown are for 0 C TA 128 C 100 l UF 12 LM358 TLH5671 8 Typical Applications Continued Handling i 5V Analog Inputs Vcc 5 Van 1 I k39 1 wk A t n V V V III 39 bl Vm IBuF II Al D f VmI TLH5671 33 Beckman Instruments 6943R10K resistor array pP lnterfaced Comparator with Hysteresis Vmii MS 33 VIN use gt OUTPUT 39 An VIN VnEFZ 1 Wait D 4 1 TLH5671 35 Analog SelfTest for a System o r VINW O O a SVSTEM 0 CHANNEL nc TEST ANAan N PDINTS o mux CMIISI o O o f th l l 1393 CHANNEL SELECT FROM OUTPUT PORT our TLH5671 36 ReadOnly Interface HP BUS DATA AD DATA IS STARTS uEw OUTPUT CONVERSION TLH5671 34 Protecting the Input Vcc 5 Vac Diodes are 1N914 I VIN H TLH5671 9 A LowCost 3Decade Logarithmic Converter 1n mv 2 vA2 10v 10k 10 V99 3 VMAX n E F LMSBQ transistors A B C D VmU All LM324A quad op amp 20k D TUE5671 a7 Typical Applications Continued 3Decade Logarithmic A D Converter A B C D LM324A Vm Hn mV T0 710v 1M ZERO ADJ IIJIJ f0 20 H2 Uses Chebyshev implementation for steeper rolloff unitygain 2nd order lowpass filter Adding a separate filter for each channel increases system response time if an analog multiplexer is used Output Buffers with AD Data Enabled 12 LMSM 11 LM394 Vin 100 ALL le vvv MD I m nzr vvv II AAA L TWP Multiplexing Differential Inputs D O W VmM VINE 4 CHANNEL DIFFERENTIAL MUX CD4052 le39 AD quotquotH NO DATA 0 5 TRISTATE wn AD W gt numns ii To MP DATA BUS AD output data is updated 1 CLK period prior to assertion of INTR 1A FROM OUTPUT PORT 0R yP 15 CHANNEL SELECT Increasing Bus Drive andor Reducing Time on Bus ED r O I i AIJ DATA OUT TD 1 DATA BUS TRlSTATE surrsns an Ta TLH5671 10 Allows output data to setup at falling edge of a Typical Applications Continued Sampling an AC Input Signal 1quot MAX 0 as FILTER 5mg v SKIRT gt How gt VIN um um Um so To lll as l su m gt 39 SH All LOWPASS MULTIPOLE CONTROL 0i FILTER I le l W E ES iui l 3 l Ms J Note 1 Oversample whenever possible keep fs gt 2f 60 to eliminate input frequency folding aliasing and to allow for the skirt response of the filter Note 2 Consider the amplitude errors which are introduced within the passband of the filter 70 Power Savings by Clock Gating fIIK mm Km Vcc An39 a D 0 D c127M274 D K m K m 12 noun 0 K m To All I Q o J m n 65 WT 14m 1474caz mm to All Complete shutdown takes 30 seconds Power Savings by A D and VREF Shutdown Vcc on 5 Vncl 5v 9quot zmsos quot CONTROL 5 quotW LIP CONTROL CMUS TD DATA BUS NO DATA OUTPUT BUFFER BUS VREFIZ TLH5671 11 Use AD00801 02 03 or 05 for lowest power consumption Note Logic inputs can be driven to VCC with AD supply at zero volts Buffer prevents data bus from overdriving output of AD when in shutdown mode 12 Functional Description 10 UNDERSTANDING AD ERROR SPECS A perfect A D transfer characteristic staircase waveform is shown in Figure 1a The horizontal scale is analog input voltage and the particular points labeled are in steps of 1 L88 1953 mV with 25V tied to the VREF2 pin The digital output codes that correspond to these inputs are shown as D 1 D and D 1 For the perfect AD not only will center value A 1 A A 1 analog inputs produce the cor rect output ditigal codes but also each riser the transitions between adjacent output codes will be located i12 LSB away from each centervalue As shown the risers are ideal and have no width Correct digital output codes will be pro vided for a range of analog input voltages that extend i 12 L88 from the ideal centervalues Each tread the range of analog input voltage that provides the same digital output code is therefore 1 L88 wide Figure 1b shows a worst case error plot for the ADCO801 All centervalued inputs are guaranteed to produce the cor rect output codes and the adjacent risers are guaranteed to be no closer to the centervalue points than i14 LSB In Transfer Function DIGITAL OUTPUT CODE A 1 A AI ANALOG INPUT Vm other words if we apply an analog input equal to the center value i 14 L88 we guarantee that the A D will produce the correct digital code The maximum range of the position of the code transition is indicated by the horizontal arrow and it is guaranteed to be no more than 12 L88 The error curve of Figure 1c shows a worst case error plot for the ADCO802 Here we guarantee that if we apply an analog input equal to the LSB analog voltage centervalue the AD will produce the correct digital code Next to each transfer function is shown the corresponding error plot Many people may be more familiar with error plots than transfer functions The analog input voltage to the A D is provided by either a linear ramp or by the discrete output steps of a high resolution DAC Notice that the error is con tinuously displayed and includes the quantization uncertain ty of the AD For example the error at point 1 of Figure 1a is 12 LSB because the digital code appeared 12 L88 in advance of the centervalue of the tread The error plots always have a constant negative slope and the abrupt up side steps are always 1 L88 in magnitude Error Plot 1 LSB 12 LSB ERROR I 12 LSB 1 L83 ANALOG INPUT Wm a Accuracy i 0 L33 A Perfect A D Transfer Function DIGITAL OUTPUT CODE Ai1 A A 1 ANALOG INPUT VIN Error Plot 1 LSB nu ma I M I ERROR I 39 I l I J vIztsn 39 I 34LSB l I 1LSB 1 A ERROR ANALOG INPUT ltva b Accuracy i 1A LSB Transfer Function DIGITAL OUTPUT CODE A 1 A A 1 ANALDG lNPUT Ivm c Accuracy i 12 L33 Error Plot 1 LSB ERROR a I I I I a a C x z 4 391LSB A1 A A1 ANALOG INPUT Vm TLH5671 12 FIGURE 1 Clarifying the Error Specs of an A D Converter Functional Description Continued 20 FUNCTIONAL DESCRIPTION The ADCO801 series contains a circuit equivalent of the 256R network Analog switches are sequenced by succes sive approximation logic to match the analog difference in put voltage VN VN to a corresponding tap on the R network The most significant bit is tested first and after 8 comparisons 64 clock cycles a digital 8bit binary code 1111 1111 fullscale is transferred to an output latch and then an interrupt is asserted INTR makes a high tolow transition A conversion in process can be interrupt ed by issuing a second start command The device may be operated in the freerunning mode by connecting W to the W input with E 0 To ensure startup under all pos sible conditions an external W pulse is required during the first powerup cycle On the hightolow transition of the W input the internal SAR latches and the shift register stages are reset As long as the input and W input remain low the AD will re main in a reset state Conversion will start from 1 to 8 clock periods after at least one of these inputs makes a lowto high transition A functional diagram of the A D converter is shown in Fig ure 2 All of the package pinouts are shown and the major logic control paths are drawn in heavier weight lines The converter is started by having and W simulta neously low This sets the start flipflop F F and the result ing 1 level resets the 8bit shift register resets the Inter rupt INTR FF and inputs a 1 to the D flop FF1 which is at the input end of the 8bit shift register Internal clock signals then transfer this 1 to the Q output of FF1 The AND gate G1 combines this 1 output with a clock signal to provide a reset signal to the start FF If the set signal is no longer present either W or is a 1 the start FF is reset and the 8bit shift register then can have the 1 clocked in which starts the conversion process If the set signal were to still be present this reset pulse would have no effect both outputs of the start F F would momentarily be at a 1 level and the 8bit shift register would continue to be held in the reset mode This logic therefore allows for wide and W signals and the converter will start after at least one of these signals returns high and the internal clocks again provide a reset signal for the start F F 1539 RESET SHIFT REGISTER quot0 BUSV AND OUIESCENT STATE INFUTPROTECTION FOR ALL LOGIC INPUTS INPUT CLK Tl INTERNAL cIRcUITs avsaov c 0 HM CLK B l i START CONVERSION 20 M88 Vcc VREEIG V 1 t IF RESET quotDquot 9 LADDER SAR BBIT VREEzc AND A LATCH SHIFT RH DEcoDER lt NOTE 2 REGISTER is A A MD L53 3 ViDut L n I AGND CL 7 LE LATcRI 5 i VINC iv J7 Jr W iv v XFER 7 TRlSTATE 32 SE vmi c OUTPUT LATCHES F41 x IfclK x msa LSB I 5 x 11 12 13 14 1515 11 18 m R J c o Nv MP DIGITAL OUTPUTS 1 co L I TRlSTATE CONTROL gt L mCLK 3 NOTE W quot1quot OUTPUT ENABLE FIB Note 1 shown twice for clarity Note 2 SAR Successive Approximation Register RESET TLH5671 13 FIGURE 2 Block Diagram Functional Description Continued After the 1 is clocked through the 8bit shift register which completes the SAR search it appears as the input to the Dtype latch LATCH 1 As soon as this 1 is output from the shift register the AND gate G2 causes the new digital word to transfer to the TRISTATE output latches When LATCH 1 is subsequently enabled the Q output makes a hightoIow transition which causes the INTR FF to set An inverting buffer then supplies the INTR input sig nal Note that this control of the INTR FF remains low for 8 of the external clock periods as the internal clocks run at 18 of the frequency of the external clock If the data output is continuously enabled E and W both held low the W output will still signal the end of conversion by a high toIow transition because the input can control the Q output of the INTR FF even though the RESET input is constantly at a 1 level in this operating mode This INTR output will therefore stay low for the duration of the E signal which is 8 periods of the external clock frequency assuming the AD is not started during this interval When operating in the freerunning or continuous conver sion mode INTR pin tied to W and E wired low see also section 28 the START FF is SET by the hightoIow transition of the INTR signal This resets the SHIFT REGIS TER which causes the input to the Dtype latch LATCH 1 to go low As the latch enable input is still present the 5 output will go high which then allows the INTR FF to be RESET This reduces the width of the resulting W output pulse to only a few propagation delays approximately 300 ns When data is to be read the combination of both and W being low will cause the INTR FF to be reset and the TRISTATE output latches will be enabled to provide the 8 bit digital outputs 21 Digital Control Inputs The digital control inputs E W and W meet standard T2L logic voltage levels These signals have been renamed when compared to the standard A D Start and Output En able labels In addition these inputs are active low to allow an easy interface to microprocessor control busses For nonmicroprocessor based applications the E input pin 1 can be grounded and the standard A D Start function is obtained by an active low pulse applied at the W input pin 3 and the Output Enable function is caused by an active low pulse at the W input pin 2 22 Analog Differential Voltage Inputs and CommonMode Reiection This AD has additional applications flexibility due to the analog differential voltage input The VN input pin 7 can be used to automatically subtract a fixed voltage value from the input reading tare correction This is also useful in 4 mA 2O mA current loop conversion In addition common mode noise can be reduced by use of the differential input The time interval between sampling VN and VN is 4 12 clock periods The maximum error voltage due to this slight time difference between the input voltage samples is given by 45 AVerAX VP Zchm where AVe is the error voltage due to sampling delay Vp is the peak value of the commonmode voltage fGm is the commonmode frequency As an example to keep this error to 14 LSB 5 mV when operating with a 60 Hz commonmode frequency fem and using a 640 kHz AD clock fCLK would allow a peak value of the commonmode voltage Vp which is given by V AVeMAX fCLk P 27mm 45 or VP 5 gtlt1O 3 640x103 628 60 45 which gives VpE 19V The allowed range of analog input voltages usually places more severe restrictions on input commonmode noise lev els An analog input voltage with a reduced span and a relatively large zero offset can be handled easily by making use of the differential input see section 24 Reference Voltage 23 Analog Inputs 231 Input Current Normal Mode Due to the internal switching action displacement currents will flow at the analog inputs This is due to onchip stray capacitance to ground as shown in Figure 3 l39 quotquotquotquotquotquotquotquot quot39l VA PEAK ro Rs TIME I l l I I 39 ll in I l I I l STEM 12 pFl TLH5671 14 39ONOI SW1aI39ldSW2 5k I39 I39ON CSTRAY 5 k X 12 pF 60 n8 FIGURE 3 Analog Input Impedance Functional Description Continued The voltage on this capacitance is switched and will result in currents entering the VN input pin and leaving the VN input which will depend on the analog differential input voltage levels These current transients occur at the leading edge of the internal clocks They rapidly decay and do not cause errors as the onchip comparator is strobed at the end of the clock period Fault Mode If the voltage source applied to the VN or VN pin exceeds the allowed operating range of VCC 50 mV large input currents can flow through a parasitic diode to the V00 pin If these currents can exceed the 1 mA max allowed spec an external diode 1 N914 should be added to bypass this current to the V00 pin with the current bypassed with this diode the voltage at the VN pin can exceed the V00 voltage by the forward voltage of this diode 232 Input Bypass Capacitors Bypass capacitors at the inputs will average these charges and cause a DC current to flow through the output resist ances of the analog signal sources This charge pumping action is worse for continuous conversions with the VN input voltage at fullscale For continuous conversions with a 640 kHz clock frequency with the VN input at 5V this DC current is at a maximum of approximately 5 MA There fore bypass capacitors should not be used at the analog inputs or the VHEFZ pin for high resistance sources gt 1 kn f input bypass capacitors are necessary for noise filter ing and high source resistance is desirable to minimize ca pacitor size the detrimental effects of the voltage drop across this input resistance which is due to the average value of the input current can be eliminated with a fullscale adjustment while the given source resistor and input bypass capacitor are both in place This is possible because the average value of the input current is a precise linear func tion of the differential input voltage 233 Input Source Resistance Large values of source resistance where an input bypass capacitor is not used will not cause errors as the input cur rents settle out prior to the comparison time If a low pass filter is required in the system use a low valued series resis tor 1 km for a passive RC section or add an op amp RC active low pass filter For low source resistance applica tions 1 km a 01 qu bypass capacitor at the inputs will prevent noise pickup due to series lead inductance of a long wire A 1000 series resistor can be used to isolate this ca pacitor both the R and C are placed outside the feedback loop from the output of an op amp if used 234 Noise The leads to the analog inputs pin 6 and 7 should be kept as short as possible to minimize input noise coupling Both noise and undesired digital clock coupling to these inputs can cause system errors The source resistance for these inputs should in general be kept below 5 kn Larger values of source resistance can cause undesired system noise pickup Input bypass capacitors placed from the analog in puts to ground will eliminate system noise pickup but can create analog scale errors as these capacitors will average the transient input switching currents of the A D see sec tion 231 This scale error depends on both a large source resistance and the use of an input bypass capacitor This error can be eliminated by doing a fullscale adjustment of the A D adjust VREFZ for a proper fullscale reading see section 252 on FullScale Adjustment with the source re sistance and input bypass capacitor in place 24 Reference Voltage 241 Span Adjust For maximum applications flexibility these ADs have been designed to accommodate a 5 VDC 25 VDC or an adjusted voltage reference This has been achieved in the design of the IC as shown in Figure 4 VccanEFl o 20 ab 1 9 VRWZG r DIGITAL 5 cincun39s L 4 ANALOG 1 l quotmm cmcuirs 1t gt i 1 J AGND noun 1 1 I77 TLH5671 15 FIGURE 4 The VREFERENCE Design on the IC Notice that the reference voltage for the IC is either 12 of the voltage applied to the V00 supply pin or is equal to the voltage that is externally forced at the VREF2 pin This al lows for a ratiometric voltage reference using the V00 sup ply a 5 VDC reference voltage can be used for the V00 supply or a voltage less than 25 VDC can be applied to the VREFZ input for increased application flexibility The inter nal gain to the VREF2 input is 2 making the fullscale differ ential input voltage twice the voltage at pin 9 An example of the use of an adjusted reference voltage is to accommodate a reduced span or dynamic voltage range of the analog input voltage If the analog input voltage were to range from 05 VDC to 35 VDC instead of 0V to 5 VDC the span would be 3V as shown in Figure 5 With 05 VDC applied to the VN pin to absorb the offset the reference voltage can be made equal to 12 of the 3V span or 15 VDC The AD now will encode the VN signal from 05V to 35 V with the 05V input corresponding to zero and the 35 VDC input corresponding to fullscale The full 8 bits of resolution are therefore applied over this reduced analog input voltage range Functional Description Continued Add if VREF2 i 1 VDC with LM358 to draw 3 mA to ground cl lt 39 VN MAX 35V A VIM V7 39 lel MIN SPAquot 3quot n5v cine15 I a Analog Input Signal Example 05 VDc ZEROSHIFT ADJ 5 O le 9 ND VREFz 7 anl VnEF SPAN2 15 vnci F 15 VI 1 I a SPAquot 2 LM35I 1 t R ADJ l TLH5671 16 b Accommodating an Analog Input from 05V Digital Out ooHEx to 35V Digital Out FFHEX FIGURE 5 Adapting the AD Analog Input Voltages to Match an Arbitrary Input Signal Range 242 Reference Accuracy Requirements The converter can be operated in a ratiometric mode or an absolute mode In ratiometric converter applications the magnitude of the reference voltage is a factor in both the output of the source transducer and the output of the A D converter and therefore cancels out in the final digital output code The AD00805 is specified particularly for use in ratio metric applications with no adjustments required In abso lute conversion applications both the initial value and the temperature stability of the reference voltage are important factors in the accuracy of the A D converter For VREF2 voltages of 24 VDC nominal value initial errors of i10 mVDC will cause conversion errors of i1 LSB due to the gain of 2 of the VREF2 input In reduced span applications the initial value and the stability of the VREF2 input voltage become even more important For example if the span is reduced to 25V the analog input LSB voltage value is cor respondingly reduced from 20 mV 5V span to 10 mV and 1 L88 at the VREF2 input becomes 5 mV As can be seen this reduces the allowed initial tolerance of the reference voltage and requires correspondingly less absolute change with temperature variations Note that spans smaller than 25V place even tighter requirements on the initial accuracy and stability of the reference source In general the magnitude of the reference voltage will re quire an initial adjustment Errors due to an improper value of reference voltage appear as fullscale errors in the A D transfer function IC voltage regulators may be used for ref erences if the ambient temperature changes are not exces sive The LM33GB 25V IC reference diode from National Semiconductor has a temperature stability of 18 mV typ 6 mV max over 0 C TA 70 C Other temperature range parts are also available 25 Errors and Reference Voltage Adjustments 251 Zero Error The zero of the AD does not require adjustment If the minimum analog input voltage value VNMN is not ground a zero offset can be done The converter can be made to output 0000 0000 digital code for this minimum input voltage by biasing the AD VN input at this VNMN value see Applications section This utilizes the differential mode op eration of the AD The zero error of the A D converter relates to the location of the first riser of the transfer function and can be mea sured by grounding the VlN input and applying a small magnitude positive voltage to the VlN input Zero error is the difference between the actual DC input voltage that is necessary to just cause an output digital code transition from 0000 0000 to 0000 0001 and the ideal 12 L88 value 12 LSB 98 mV for VREF2 2500 VDC 252 FullScale The fullscale adjustment can be made by applying a differ ential input voltage that is 112 LSB less than the desired analog fullscale voltage range and then adjusting the mag nitude of the VREF2 input pin 9 or the V00 supply if pin 9 is not used for a digital output code that is just changing from 11111110to11111111 Functional Description Continued 253 Adjusting for an Arbitrary Analog Input Voltage Range If the analog zero voltage of the A D is shifted away from ground for example to accommodate an analog input sig nal that does not go to ground this new zero reference should be properly adjusted first A VN voltage that equals this desired zero reference plus 12 L88 where the LSB is calculated for the desired analog span 1 L88 ana log span256 is applied to pin 6 and the zero reference voltage at pin 7 should then be adjusted to just obtain the 00HEX to 01HEX code transition The fullscale adjustment should then be made with the proper VN voltage applied by forcing a voltage to the VN input which is given by VMAX VMIN VN fS adj 256 VMAx 15 where VMAX The high end of the analog input range and VMjN the low end the offset zero of the analog range Both are ground referenced The VREFZ or VCC voltage is then adjusted to provide a code change from FEHEX to FFHEX This completes the ad justment procedure 26 Clocking Option The clock for the AD can be derived from the CPU clock or an external RC can be added to provide selfclocking The CLK IN pin 4 makes use of a Schmitt trigger as shown in Figure 6 U cum 19 f 1 quot CLKTM RC CLK I M CLK R E 10 k c I 110 TLH5671 17 FIGURE 6 SelfClocking the AD Heavy capacitive or DC loading of the clock R pin should be avoided as this will disturb normal converter operation Loads less than 50 pF such as driving up to 7 A D convert er clock inputs from a single clock R pin of 1 converter are allowed For larger clock line loading a CMOS or low power TTL buffer or PNP input logic should be used to minimize the loading on the clock R pin do not use a standard TTL buffer 27 Restart During a Conversion If the AD is restarted and W go low and return high during a conversion the converter is reset and a new con version is started The output data latch is not updated if the conversion in process is not allowed to be completed there fore the data of the previous conversion remains in this latch The INTR output simply remains at the 1 level 28 Continuous Conversions For operation in the freerunning mode an initializing pulse should be used following powerup to ensure circuit opera tion In this application the input is grounded and the W input is tied to the INTR output This W and INTR node should be momentarily forced to logic low following a powerup cycle to guarantee operation 29 Driving the Data Bus This MOS AD like MOS microprocessors and memories will require a bus driver when the total capacitance of the data bus gets large Other circuitry which is tied to the data bus will add to the total capacitive loading even in TRI STATE high impedance mode Backplane bussing also greatly adds to the stray capacitance of the data bus There are some alternatives available to the designer to handle this problem Basically the capacitive loading of the data bus slows down the response time even though DC specifications are still met For systems operating with a relatively slow CPU clock frequency more time is available in which to establish proper logic levels on the bus and therefore higher capacitive loads can be driven see typical characteristics curves At higher CPU clock frequencies time can be extended for IO reads andor writes by inserting wait states 8080 or using clock extending circuits 6800 Finally if time is short and capacitive loading is high exter nal bus drivers must be used These can be TRlSTATE buffers low power Schottky such as the DM74L8240 series is recommended or special higher drive current products which are designed as bus drivers High current bipolar bus drivers with PNP inputs are recommended 210 Power Supplies Noise spikes on the V00 supply line can cause conversion errors as the comparator will respond to this noise A low inductance tantalum filter capacitor should be used close to the converter VCC pin and values of 1 pF or greater are recommended If an unregulated voltage is available in the system a separate LM340LAZ50 TO92 5V voltage regu lator for the converter and other analog circuitry will greatly reduce digital noise on the V00 supply 211 Wiring and HookUp Precautions Standard digital wire wrap sockets are not satisfactory for breadboarding this A D converter Sockets on PC boards can be used and all logic signal wires and leads should be grouped and kept as far away as possible from the analog signal leads Exposed leads to the analog inputs can cause undesired digital noise and hum pickup therefore shielded leads may be necessary in many applications Functional Description Continued A single point analog ground that is separate from the logic ground points should be used The power supply bypass capacitor and the selfclocking capacitor if used should both be returned to digital ground Any VREF2 bypass ca pacitors analog input filter capacitors or input signal shield ing should be returned to the analog ground point A test for proper grounding is to measure the zero error of the AD converter Zero errors in excess of 14 L88 can usually be traced to improper board layout and wiring see section 251 for measuring the zero error 30 TESTING THE AD CONVERTER There are many degrees of complexity associated with test ing an AD converter One of the simplest tests is to apply a known analog input voltage to the converter and use LEDs to display the resulting digital output code as shown in Fig ure 7 For ease of testing the VREF2 pin 9 should be supplied with 2560 VDC and a VCC supply voltage of 512 VDC should be used This provides an LSB value of 20 mV If a fullscale adjustment is to be made an analog input voltage of 5090 VDC 5120 112 LSB should be applied to the VN pin with the VN pin grounded The value of the VREF2 input voltage should then be adjusted until the digital output code is just changing from 1111 1110 to 1111 1111 This value of VREF2 should then be used for all the tests The digital output LED display can be decoded by dividing the 8 bits into 2 hex characters the 4 most significant MS and the 4 least significant LS Table shows the fractional binary equivalent of these two 4bit groups By adding the voltages obtained from the VMS and VLS columns in Table the nominal value of the digital display when 10k 150 pF 10F 11 TANTALUM START Vnc A 6ND 2560 Vac VREFZ 01uf 13quot M33 393 N a NSLSIJZ s TLH5671 18 FIGURE 7 Basic AD Tester VREF2 2560V can be determined For example for an output LED display of 1011 0110 or B6 in hex the voltage values from the table are 3520 0120 or 3640 VDC These voltage values represent the centervalues of a per fect A D converter The effects of quantization error have to be accounted for in the interpretation of the test results For a higher speed test system or to obtain plotted data a digitaltoanalog converter is needed for the test setup An accurate 10bit DAC can serve as the precision voltage source for the A D Errors of the AD under test can be expressed as either analog voltages or differences in 2 digi tal words A basic A D tester that uses a DAC and provides the error as an analog output voltage is shown in Figure 8 The 2 op amps can be eliminated if a lab DVM with a numerical sub traction feature is available to read the difference voltage A C directly The analog input voltage can be supplied by a low frequency ramp generator and an XY plotter can be used to provide analog error Y axis versus analog input X axis For operation with a microprocessor or a computerbased test system it is more convenient to present the errors digi tally This can be done with the circuit of Figure 9 where the output code transitions can be detected as the 10bit DAC is incremented This provides 14 L88 steps for the 8bit AD under test If the results of this test are automatically plotted with the analog input on the X axis and the error in LSB s as the Y axis a useful transfer function of the AD under test results For acceptance testing the plot is not neces sary and the testing speed can be increased by establishing internal limits on the allowed error for each code 40 MICROPROCESSOR INTERFACING To dicuss the interface with 8080A and 6800 microproces sors a common sample subroutine structure is used The microprocessor starts the A D reads and stores the results of 16 successive conversions then returns to the user s program The 16 data bytes are stored in 16 successive memory locations All Data and Addresses will be given in hexadecimal form Software and hardware details are pro vided separately for each type of microprocessor 41 Interfacing 8080 Microprocessor Derivatives 8048 This converter has been designed to directly interface with derivatives of the 8080 microprocessor The A D can be mapped into memory space using standard memory ad dress decoding for E and the MEMR and MEMW strobes or it can be controlled as an IO device by using the IO R and IO W strobes and decoding the address bits A0 gt A7 or address bits A8 gt A15 as they will contain the same 8bit address information to obtain the E input Us ing the IO space provides 256 additional addresses and may allow a simpler 8bit address decoder but the data can only be input to the accumulator To make use of the addi tional memory reference instructions the AD should be mapped into memory space An example of an AD in IO space is shown in Figure 10 Functional Description Continued aBIT VANALOG OUTPUT OACIOOD IOBIT DAC AD UNDER TEST ANALOG INPUT VOLTAGE IIIOX ANALOG ERROR VOLTAGE FIGURE 8 AD Tester with Analog Error Output DIGITAL quotA3190quot VANALOG AD UNDER DIGITAL INPUT 10393quot TEST OUTPUT nAc TLH5671 19 FIGURE 9 Basic Digital AD Tester TABLE I DECODING THE DIGITAL OUTPUT LEDS OUTPUT VOLTAGE FRACTIONAL BINARY VALUE FOR CENTER VALUES HEX BINARY WITH VREF2 2560 VDc MS GROUP LS GROUP VMS GROUP VLS GROUP F 1 1 1 1 1516 15256 4800 0300 E 1 1 1 0 78 7128 4480 0280 D 1 1 0 1 1316 13256 4160 0260 C 1 1 0 0 34 364 3840 0240 B 1 0 1 1 1116 11256 3520 0220 A 1 0 1 0 58 5128 3200 0200 9 1 0 0 1 916 9256 2880 0180 8 1 0 0 0 12 132 2560 0160 7 0 1 1 1 716 7256 2240 0140 6 0 1 1 0 38 3128 1920 0120 5 0 1 0 1 516 2256 1600 0100 4 0 1 0 0 14 164 1280 0080 3 0 0 1 1 316 3256 0960 0060 2 0 0 1 0 18 1128 0640 0040 1 0 0 0 1 116 1256 0320 0020 0 0 0 0 0 0 0 Display Output VMS Group VLS Group 2O Functional Description Continued INT 14 W WR 27 W n n 25V TWHF mm Mquot as miquot 032 11 ans W on 5 08518 use 20 DB7 7V A015 36 AD14 39 AD13 38 A012 37 A011 40 AD10 1 DM8131 BUS COMPARATOR TLH5671 20 Note 1 Pin numbers for the DP8228 system controller others are IN88080A Note 2 Pin 23 of the IN88228 must be tied to 12V through a 1 kn resistor to generate the EST 7 instruction when an interrupt is acknowledged as required by the accompanying sample program FIGURE 10 ADCOBO1IN38080A CPU Interface SAMPLE PROGRAM FOR FIGURE 10 ADCOBO1IN38080A CPU INTERFACE 0058 C5 00 05 RST 7 JMP LD DATA 0 O O O O O 0100 21 00 02 START LXI H 0200H HL pair will point to data storage locations 0105 51 00 04 RETURN LXI SP 0400H Initialize stack pointer Note 1 0106 7D MOVA L Test of bytes entered 0107 FEOF CPI OFH If 16 JMPto 0109 CA 15 01 JZ CONT user program 0100 D5 E0 OUT E0 H Start AD 010E FB EI Enable interrupt 010E 00 LOOP NOP Loop until end of 0110 C5 OF 01 JMP LOOP conversion 0115 0 CONT 0 O O O O 0 0 User program to 0 0 0 process data 0 O O O O O O O O 0500 DB E0 LD DATA IN E0 H Load data into accumulator 0502 77 MOVM A Store data 0505 25 INXH Increment storage pointer 0504 C5 05 01 JMP RETURN Note 1 The stack pointer must be dimensioned because a EST 7 instruction pushes the PC onto the stack Note 2 All address used were arbitrarily chosen 21 Functional Description Continued The standard control bus signals of the 8080 W and W can be directly wired to the digital control inputs of the AD and the bus timing requirements are met to allow both starting the converter and outputting the data onto the data bus A bus driver should be used for larger microprocessor systems where the data bus leaves the PC board andor must drive capacitive loads larger than 100 pF 411 Sample 8080A CPU Interfacing Circuitry and Program The following sample program and associated hardware shown in Figure 10 may be used to input data from the converter to the NS8080A CPU chip set comprised of the NS8080A microprocessor the NS8228 system controller and the NS8224 clock generator For simplicity the AD is controlled as an IO device specifically an 8bit bidirection al port located at an arbitrarily chosen port address E0 The TRlSTATE output capability of the AD eliminates the need for a peripheral interface device however address decoding is still required to generate the appropriate for the con verter quot88048 ANALOG INPUT It is important to note that in systems where the AD con verter is 1of8 or less IO mapped devices no address decoding circuitry is necessary Each of the 8 address bits A0 to A7 can be directly used as inputs one for each lO device 412 INSBO48 Interface The NS8048 interface technique with the ADCO801 series see Figure 11 is simpler than the 8080A CPU interface There are 24 VD lines and three test input lines in the 8048 With these extra lO lines available one of the IO lines bit 0 of port 1 is used as the chip select signal to the AD thus eliminating the use of an external address decoder Bus control signals W W and W of the 8048 are tied directly to the A D The 16 converted data words are stored at on chip RAM locations from 20 to 2F Hex The W and W signals are generated by reading from and writing into a dummy address respectively A sample interface program is shown below A0608quot TLH5671 21 FIGURE 11 N38048 Interface SAMPLE PROGRAM FOR FIGURE 11 NSBO48 INTERFACE O4 10 JMP ORG O4 50 JMP ORG 99 FE ANL 81 MOVX 89 01 START ORL B8 20 MOV B9 FF MOV BA 10 MOV 25 FF AGAIN MOV 99 FE ANL 91 MOVX 05 EN 96 21 LOOP JNZ EA 1B DJNZ OO NOP OO NOP ORG 81 INDATA MOVX AO MOV 18 INC 89 01 ORL 27 CLR 95 RETR 10H Program starts at addr 10 SH 50H Interrupt jump vector 10H Main program P1 OFEH Chip select A Rl Read in the lst data to reset the intr P1 1 Set port pin high R0 ZOH Data address R1 OFFH Dummy address R2 1OH Counter for 16 bytes A OFFH Set A00 for intr loop P1 OFEH SendCSbitOofP1 Rl A Send WR out I Enable interrupt LOOP Wait for interrupt R2 AGAIN If 16 bytes are read go to user39 5 program 50H A Rl Input data CS still low RO A Store in memory R0 Increment storage counter P1 1 Reset CS signal A Clear ACC to get out of the interrupt loop 22 Functional Description Continued 42 Interfacing the 280 The Z80 control bus is slightly different from that of the 8080 General W and W strobes are provided and sepa rate memory request MREQ and IO request IORQ sig nals are used which have to be combined with the general ized strobes to provide the equivalent 8080 signals An ad vantage of operating the AD in IO space with the 280 is that the CPU will automatically insert one wait state the W and W strobes are extended one clock period to allow more time for the IO devices to respond Logic to map the AD in IO space is shown in Figure 13 W T 2 U Tim M R 3 W R MMMcaz TLH5671 23 FIGURE 13 Mapping the MD as an lO Device for Use with the 280 CPU Additional IO advantages exist as software DMA routines are available and use can be made of the output data trans fer which exists on the upper 8 address lines A8 to A15 during IO input instructions For example MUX channel selection for the AD can be accomplished with this operat ing mode 43 Interfacing 6800 Microprocessor Derivatives 6502 etc The control bus for the 6800 microprocessor derivatives does not use the W and W strobe signals Instead it em ploys a single RW line and additional timing if needed can be derived fom the 452 clock A IO devices are memory mapped in the 6800 system and a special signal VMA indicates that the current address is valid Figure 14 shows an interface schematic where the AD is memory mapped in the 6800 system For simplicity the E decoding is shown using 12 DM8092 Note that in many 6800 systems an al ANALOG INPUTS Note 1 Numbers in parentheses refer to M06800 CPU pin out Note 2 Number or letters in brackets refer to standard M6800 system common bus code ready decoded m line is brought out to the common bus at pin 21 This can be tied directly to the E pin of the AD provided that no other devices are addressed at HX ADDR 4XXX or 5XXX The following subroutine performs essentially the same function as in the case of the 8080A interface and it can be called from anywhere in the user s program In Figure 75 the ADCO801 series is interfaced to the M6800 microprocessor through the arbitrarily chosen Port B of the M06820 or M06821 Peripheral Interface Adapter PIA Here the E pin of the AD is grounded since the PIA is already memory mapped in the M6800 system and no E decoding is necessary Also notice that the AD output data lines are connected to the microprocessor bus under pro gram control through the PIA and therefore the AD W pin can be grounded A sample interface program equivalent to the previous one is shown below Figure 15 The PIA Data and Control Regis ters of Port B are located at HEX addresses 8006 and 8007 respectively 50 GENERAL APPLICATIONS The following applications show some interesting uses for the AD The fact that one particular microprocessor is used is not meant to be restrictive Each of these application cir cuits would have its counterpart using any microprocessor that is desired 51 Multiple AD60801 Series to MC6800 CPU Interface To transfer analog data from several channels to a single microprocessor system a multiple converter scheme pre sents several advantages over the conventional multiplexer singleconverter approach With the ADCO801 series the differential inputs allow individual span adjustment for each channel Furthermore all analog input channels are sensed simultaneously which essentially divides the microproces sor s total system servicing time by the number of channels since all conversions occur simultaneously This scheme is shown in Figure 16 To 4Dl RM 34 61 our avis 3 no 13 311 m 32 29 02 31 R 03 30 ii 04 29 32 D5 28 301 ns 21 E m 26 I A12 22 34 A13 23 ii A14 24 ll A15 25 33 VMA 5 IF END ml WW I 414243 TLH5671 24 FIGURE 14 ADC0801MC6800 CPU Interface Functional Description Continued 0056 0058 005B 005D 005F SAMPLE PROGRAM FOR FIGURE 14 ADC0801MC6800 CPU INTERFACE DF 56 DATAIN STX TEMPZ CE 00 20 LDX 0020 FF FF F8 STX FFF8 B7 50 00 STAA 5000 0E CLI 5E CONVRT WAI DE 54 LDX TEMPl 8C 02 0F CPX 020F 27 14 BEQ ENDP B7 50 00 STAA 5000 08 INX DF 54 STX TEMPl 20 F0 BRA CONVRT DE 54 INTRPT LDX TEMPl B6 50 00 LDAA 5000 A7 00 STAA X 5B RTI 02 00 TEMPl FDB 0200 00 00 TEMPZ FDB 0000 CE 02 00 ENDP LDX 0200 DF 54 STX TEMPl DE 56 LDX TEMPZ 59 RTS Save contents ofX Upon low CPU jumps to 0020 Start ADCO80l Wait fo r inte rrupt Is final data stored Re starts ADCO801 Read data Store it at X Starting address for data storage Reinitialize TEMPl Return from subrouti To user39 5 program ne Note 1 In order for the microprocessor to service subroutines and interrupts the stack pointer must be dimensioned in the user s program v CLKIN ANALOG Vm INPUTS A GND VREFZ D GNU 150 pF FIGURE 15 ADCOBO1M0682O PIA Interface TLH5671 25 24 Functional Description Conlinued SAMPLE PROGRAM FOR FIGURE 15 ADCOBO1 M06820 PIA INTERFACE 0010 CE 00 58 DATAIN LDX 0013 FF FF F STX 0016 B6 80 06 LDAA 0019 4F CLRA 00 1A B7 80 0 7 STAA 001D B7 80 06 STAA 0020 CLI 0021 CS 34 LDAB 0025 86 3D LDAA 0025 F7 80 07 CONVRT STAB 0028 B7 80 0 STAA 002B 3E WAI 0020 DE 40 LDX 002E BC 02 0F CPX 0031 27 0F BEQ 0035 08 INX 00 54 DF 40 STX 00 36 20 ED BRA 00 58 DE 40 INTRPT LDX 00 3A B6 80 06 LDAA 00 3D A7 00 STAA 00 3F B RTI 0040 02 00 TEMPl FDB 0042 CE 02 00 ENDP LDX 0045 DF 40 STX 0047 RTS PIAORB EQU PIACRB EQU The lollowing schemalic and sample subrouline DATA lN ma e used lo inlerlace up lo 8 AD00801 s direclly lo lhe M06800 CPU This scheme can easily be exlended lo allow lhe inlerlace ol more converlers ln lhis conliguralion lhe converlers are arbilrarily localed al HEX address 5000 in lhe M06800 memory space To save componenls lhe clock signal is derived lrom jusl one RC pair on lhe lirsl converler This oulpul drives lhe olher ADs All lhe converlers are slarled simullaneously wilh a STORE inslruclion al HEX address 5000 Nole lhal any olher HEX address ol lhe lorm 5XXX will be decoded by lhe circuil pulling all lhe a inpuls low This can easily be avoided by u i a more delinilive address decoding scheme All lhe inlerrupls are ORed logelher lo insure lhal all ADs have compleled lheir conversion belore lhe microprocessor is in lerrupled The subrouline DATA lN may be called lrom anywhere in lhe user s program Once called lhis rouline inilializes lhe aooss Uponfi lowCPu arrrs jumpsto0038 PIAORB Clearpossiblef flags PIACRB PIAORB SetPortBasinput a34 aSD PIACRB StartsADCOBOl PIACRB Waitforinterrupt TEMPl llozoF Is final data stored ENDP EMPl CONVRT MP1 PIAORB Readdatain x StoreitatX 0200 Starting address for data storage aozoo ReinitializeTEMPl TEMPl Return from subroutine 8006 To user39 s program 8007 CPU slarls all lhe converlers simullaneously and walls lor lhe inlerrupl signal Upon receiving lhe inlerrupl il reads lhe converlers lrom HEX addresses 5000 lhrough 5007 and slores lhe dala successively al arbilrarily chosen HEX ad dresses 0200 lo 0207 belore relurnlng lo lhe user s pro gram A CPU regislers lhen recover lhe original dala lhey had belore servicing DATA W 52 AuloZeroed Differenlial Transducer Amplifier verler The dillerenlial inpuls ol lhe AD00801 series eliminale lhe need lo perlorm a dillerenlial lo single ended conversion lor a dillerenlial lransducer Thus one op amp can be eliminal ed since lhe dillerenlial lo sin le ended conversion is pro vided by lhe dillerenlial inpul ol lhe AD00801 series in gen eral a lransducer preamp is required lo lake advanlage ol lhe lull AD converler inpul dynamic range Functional Description Continued nW mafia m 32 29 oz 31 K 03 an ii In 29 32 na 23 an as 27 If 07 26 I ANALOG INPUTS A2 11 0 A1 m V no a an ABC 5VBl J 12 o o o DM74LS138 W 7 GND 1 I ANAwG 414243 INPUTS VMA 5lFl A12 22W A13123il A14124Hm Note 1 Numbers in parentheses refer to M06800 CPU pin out Note 2 Numbers of letters in brackets refer to standard M6800 system common bus code TLH5671 26 FIGURE 16 Interfacing Multiple AIDS in an M66800 System SAMPLE PROGRAM FOR FIGURE 16 INTERFACING MULTIPLE ADs IN AN M66800 SYSTEM ADDRESS HEX CODE MNEMONICS COMMENTS 0010 DF 44 DATAIN STX TEMP Save Contents of X 0012 CE 00 2A LDX 002A Upon m LOW CPU 0015 FF FF F8 STX FFF8 Jumps to 002A 0018 B7 50 00 STAA 5000 Starts all AD 39 5 001B 0E CLI 0010 SE WAI Wait for interrupt 001D CE 50 00 LDX 5000 0020 DF 40 STX INDEX1 Re set both INDEX 0022 CE 02 00 LDX 0200 1 and 2 to starting 0025 DF 42 STX INDEX2 addresses 0027 DE 44 LDX TEMP 0029 59 RTS Return from subroutine 002A DE 40 INTRPT LDX INDEX1 INDEX1 gt X 0020 A6 00 LDAA X Read data in from AD at X 002E 08 INX Increment X by one 002F DF 40 STX INDEX1 X gt INDEX1 0051 DE 42 LDX INDEX2 INDEX2 gt X Functional Description Conlinued SAMPLE PROGRAM FOR FIGURE 15 INTERFACING MULTIPLE ADs IN AN M06800 SYSTEM ADDRESS HEX CODE MNEMONICS COMMENTS 0053 A700 STAA X Stox e data at 0055 BC 0207 CPX 0207 Have allAD39Sbeen read 0038 2705 BEQ RETURN Yes branch to RETURN 005A 8 INX No incrementbe one 003B DF 42 STX INDEX2 X gt INDEX2 003D 20 EB BRA INTRPT Branch to 002A 003F 5B RETURN RTI 0040 50 00 INDEXl FDB 5000 Starting address forAD 0042 02 00 INDEX2 FDB 0200 Starting address fordata Storage 0044 00 00 TEMP FDB 000 Note 1 In ordeviov u m M 1m 1 user39s pvog For ampliiicalion oi DC inpu1 signals a major sys1em error is 1he inpu1 oiise1 vollage oi 1he ampliiiers used ior 1he preamp Figure 17 is a gain oi 100 diiierenlial preamp whose oiise1 vollage errors will be cancelled by a zeroing subrouline which is periormed by 1he lNSBOBOA microproc essor syslem The lolal allowable inpu1 oiisel vollage error ior1his preamp is ony 50 pV ior V4 LSB error This would obviously require very precise ampliiiers The expression ior 1he diiierenlial ou1pu1 vollage oi 1he preamp 39 39 Is Vo VIN VIN 1 2112 SlGNAL GAlN 2R 17 R1 DC ERROR TERM GAlN where ix is 1he curren11hrough resislor Rx All oi 1he oiisel error 1erms can be cancelled by making rlXRX Vos V053 7 V052 This is 1he principle oi 1his aulozeroing scheme The lNSBOBOA uses 1he 3 lO porls oi an lN88255 Pro gramable Peripheral lnleriace PPl lo con1ro1he aulo zero ing and inpu1 da1airom1he ADCOBO1 as shown in Figure 18 The PM is programmed ior basic lO opera1ion mode 0 wi1h Porl A being an inpu1 por1 and Porls B and C being ou1pu1porls Two bi1s oi Porl C are used lo allernalely open or close 1he 2 swi1ches a1 1he inpu1 oi 1he preamp Swilch Vos2 Vos Vosa i XRX SW1 is closed lo iorce 1he preamp s diiierenlial inpu1 lo be zero during 1he zeroing subrouline and 1hen opened and 2 is 1hen closed ior conversion oi 1he ac1ual diiierenlial VX increas or e e 1he diiierenlial ou1pu1vo1age equal lo zero This is accomplished by ensuring 1ha1 1he vollage a1 1he ou1pu1 oi A1 is approximaiely 25V so 1ha1 a logic 1quot 5V on any ou1pu1 oi Porl B will source curren1inlo node Vx 1hus raising 1he vollage a1 Vx and making 1he ou1pu1 diiierenlial more negalive Conversely a logic 0quot 0V will pull curren1 oi node Vx and decrease 1he vollage causing 1he diiier pV which will null 1he oiise1 error 1erm lo i4 LSB oi iu scale ior1he ADCOBO1 1 is impor1an1 1ha1 1he vollage levels 1ha1 drive 1he aulozero resislors be conslan1Aso ior sym melly a logic swing oi 0V lo 39 venienl To achieve an lt 5 o o 3 ource Buiier ampliiier A1 is necessary so 1ha1 i1 can source or sink 1he DA ou1pu1 currenl Functional Description Continued VmH Avm VREFZ vmm 25V z FROM OUTPUT PORT B BUFFER FIGURE 16 F ROM O UTPUT PORT 2 FIGURE 16 Note 1 R2 495 R1 Note 2 Switches are LMC13334 CMOS analog switches Note 3 The 9 resistors used in the autozero section can be i5 tolerance FIGURE 17 Gain of 100 Differential Transducer Preamp lNVERTiNG ADDRESS DM3131 BUFFERS OUTPUT 4 TM PORT A au r r E as mssznz PREAMP OUTPUTS quot 83255 PPI 8080A DATA BUS 3 PORT B BUFFERS TD quotSARquot MMMCDD RESISTDRS TD SW1 BUFF E RS MMNCIJEI SW2 TLH5671 27 FIGURE 18 Microprocessor Interface Circuitry for Differential Preamp 28 A flow chart for the zeroing subroutine is shown in Figure 19 It must be noted that the ADCO801 series will output an all zero code when it converts a negative input VN 2 VN Also a logic inversion exists as all of the lO ports are buffered with inverting gates Basically if the data read is zero the differential output volt age is negative so a bit in Port B is cleared to pull VX more negative which will make the output more positive for the next conversion If the data read is not zero the output volt age is positive so a bit in Port B is set to make VX more positive and the output more negative This continues for 8 approximations and the differential output eventually con verges to within 5 mV of zero The actual program is given in Figure 20 All addresses used are compatible with the BLC 8010 microcomputer system In particular Port A and the ADCO801 are at port address E4 Port B is at port address E5 Port C is at port address E6 PPI control word port is at port address E7 Program Counter automatically goes to ADDRSC3D upon acknowledgement of an interrupt from the ADCO801 53 Multiple AD Converters in a 280 Interrupt Driven Mode ln data acquisition systems where more than one A D con verter or other peripheral device will be interrupting pro gram execution of a microprocessor there is obviously a need for the CPU to determine which device requires servic ing Figure 21 and the accompanying software is a method of determining which of 7 ADCO801 converters has com pleted a conversion W asserted and is requesting an interrupt This circuit allows starting the A D converters in any sequence but will input and store valid data from the converters with a priority sequence of A D 1 being read first AD 2 second etc through AD 7 which would have the lowest priority for data being read Only the converters whose INT is asserted will be read The key to decoding circuitry is the DM74LSS73 8bit D type flipflop When the 280 acknowledges the interrupt the program is vectored to a data input 280 subroutine This subroutine will read a peripheral status word from the DM74LS373 which contains the logic state of the INTR out puts of all the converters Each converter which initiates an interrupt will place a logic 0 in a unique bit position in the status word and the subroutine will determine the identity of the converter and execute a data read An identifier word which indicates which A D the data came from is stored in the next sequential memory location above the location of the data so the program can keep track of the identity of the data entered START ZEROING SUBROUTINE CLOSE SW1 OPEN SW2 INITIALIZE SAR BIT POINTER REG B X 3980 I INITIALIZE SAR CODE IN REG C REG C X 397F I OUTPUT FIRST SAR CODE PORT B X 3980 START MD AND READ DATA quotORquot REG B WITH REG C TO CLEAR BIT IN PORT B WHEN REAPPLIED SHIFT quot1quot IN REG B RIGHT TO POINT TO NEXT BIT IS REG B ZERO OPEN SW1 CLOSE SW2 PREAMP IS ZEROED AND PROPER INPUT CONVERSIONS CAN BE DONE EXCLUSIVEORquot REG BWITH REG 8 TO SET NEXT BIT IN PORT B OUTPUT NEW SAR CODE TO PORT B TLH5671 28 FIGURE 19 Flow Chart for AutoZero Routine 29 SD00 SE90 MVI 90 SD02 DSE39I Out Control Port Program PPI SD04 2601 MVI H 01 AutoZero Subroutine 3D06 7C MOVAH SD07 D3E6 OUT C Close SW1 open SW2 3D09 0680 MVI B 80 Initialize SAR bit pointer 3DOB 3E7F MVI A 7F Initialize SAR code 3DOD 4F MOV CA Return 3DOE D3E5 OUT B Port B SAR code 3D10 SlAASD LXI SP SDAA Start Dimension stack pointer 3D13 D3E4 OUTA Start AD 3D15 FB IE 3D16 oo NOP Loop Loop untilmasserted 3D17 C3163D JMP Loop 3D1A 7A MOVAD AutoZero 3D1B C600 ADI 00 3D1D CAZDSD JZSetC TestAD output data for zero SD20 78 MOVAB Shift B SD21 F600 URI 00 Clear carry 3D23 1F RAR Shift quot1quot in B right one place 5D24 FE00 CPI 00 IsBzero Ifyes last SD26 CAS39ISD JZ Done approximation has beenmade 5D29 47 OVBA SDZA C3333D JMP New C 3D2D 79 MOVAC Set C SDZE B0 ORA B Set bit in C that is in same 3D2F 4F position as quot1quot inB 3D30 C3203D JMP Shift B 3D33 XRA C New C Clear bit in C that is in 3D34 C30D3D JMPReturn same positionas quot1quot inB 3D37 47 MOVBA Done then output new SARcode 3D38 7C MOVAH Open SW1 close SW2then 3D39 EE03 XRI 05 proceedwith program Preamp SDSB D5E6 OUT C is now zeroed SDSD 0 Normal Program for processing proper data values SCSD DBE4 INA ReadAD Subroutine ReadAD data SCSF EEFF XRI FF Invert data 3C41 57 MOVDA 3C42 78 MOVAB IsBReg0 Ifnot stay 3C43 E6FF ANI FF in auto zero subroutine 3C45 C21A3D JNZAutoZero 5048 CSSDSD JMP Normal Note All numerical values are hexadecimal representation Fl 5 URE 20 Software for AutoZeroed Differential AD 53 Multiple AD Converters in a ZBO Interrupt Driven Mode Continued Th 1 39 1 e o owmg no es appy 5 The peripherals oi concern are mapped in1o lO space 1 11 Is assumed 1ha11he CPU au1oma1cay perlorms a RST wiih 1he 39ollowing p0 assignmems 7 ins1ruc1ion when a valid in1errup1 is acknowledged CPU is in in1errup1 mode 1 Hencee1he subrou1ine s1ar1ing ad HEX PORT ADDRESS PERIPHERAL dress 01 X0038 MM74CB74 8bi1ilipilop 2 The address buslrom1he 280 and 1he da1a bus 10 1he Z 01 AD1 are assumed 10 be inverled by bus drivers 02 AD 2 3 AD da1a and iden1ilying words will be slored in sequen 03 A D 3 1ia memory oca1ions s1ar1ing a11he arbi1rariy chosen ad 04 AD 4 dress X 3E00 05 AD 5 4 The s1ack poin1er mus1 be dimensioned in 1he main pro 05 AD 5 gram as 1he RST 7 ins1ruc1ion au1oma1icay pushes 1he 07 AD 7 PC on1o1he s1ack and 1he subrou1ine uses an addi1iona TL39 44 39 1he 39 39 39 1 6 s1ack addresses 1he program MMMCSU DZ m MMMczu DMNLSI 38 TLH5671 29 FIGURE 21 Multiple ADs with Z80 Type Microprocessor INTERRUPT SERVICING SUBROUTINE SOURCE LOC OBJ CODE STATEMENT COMMENT 0058 E5 PUSH HL Save contents of all registers affected by 0059 C5 PUSH BC this subroutine 005A F5 PUSH AF Assumed INT mode 1 earlier set 005B 21 00 5E LD HL XSEOO Initialize memory pointer where data will be stored 005E OE Ol LD C X01 C register will be port ADDR of AD converters 0040 D500 OUT X00 A Load peripheral status word into 8bit latch 0042 DB00 IN A X00 Load status word into accumulator 0044 47 LD BA Save the status word 0045 79 TEST LDAC Test to see if the status of all AD39shave 0046 FE 08 CP X08 been checked If so exit subroutine 0048 CA 60 00 JPZ DONE 004B 78 LD AB Test a single bit in status word by looking for 004C lF RRA a quotlquot to be rotated into the CARRY anI NT 004D 47 LDBA is loaded asaquotlquot If CARRY is set then load 004E DA 5500 JPC LOAD contents of AD at port ADDR in C register 0051 0C NEXT INC C If CARRY is not set increment C register to point 0052 C5 4500 JP TEST to next AD then test next bit in status word 0055 ED 78 LOAD IN A C Read data from interrupting AD and invert 0057 EE FF XOR FF the data 0059 77 LD HL A Store the data 005A 2C INC L 005B 71 LD HL C Store AD identifier AD port ADDR 005C 2C INC L 005D C5 51 00 JPNEXT Test next bit in status word 0060 F1 DONE POP AF Reestablish all registers as they were 0061 C1 POP BC before the interrupt 0062 El POP HL 0065 C9 RET Return to original program 31 Ordering Information TEMP RANGE 0 C T0 70 C 0 C T0 70 C 0 C T0 70 C 40 C TO 85 C i 1A Bit ADC0801LCN Adjusted r 12 Bit ADC0802LCWM ADC0802LCV ADC0802LCN ERROR Unadjusted i 12 Bit ADC0803LCWM ADC0803LCV ADC0803LCN Adjusted r 1 Bit ADC0804LCWM ADC0804LCV ADC0804LCN ADC0805LCN Unadjusted PACKAGE OUTLINE M2OB Small Outline V2OA Chip Carrier N2OA Molded DIP TEMP RANGE 40 C TO 85 C 55 C TO 125 C i 1A Bit Adjusted ADC0801LCJ ADCO801LJ ERROR i 12 Bit Unadjusted ADC0802LCJ ADC0802LJ i 12 Bit Adjusted ADC0803LCJ ADC0802LJ883 i 1 Bit Unadjusted ADC0804LCJ PACKAGE OUTLINE J2OA Cavity DIP J2OA Cavity DIP Connection Diagrams ADC080X DuallnLine and Small Outline SO Packages J cs 1 20 VCC0R vREF 2 19 CLKR W 3 18 DBOLSB CLKIN 4 17 DBI W 5 15 DBZ vN 6 15 DB VN39 7 14 DB4 AGND 8 13 035 vREFz 9 12 DBG DGND 1o 11 DB7MSB TLH5671 30 ADC080X Molded Chip Carrier PCC Package See Ordering Information NV m C m 0 DD DB1 B CLK IN INTR VVIN39 V D D 13 D35 12 D36 DB7 M33 10 D GND 9 VREF2 AGND TLH5671 32 32 Physical Dimensions inches millimeters 0180 4572 MAX 0290 0320 7366 8128 0 0310 0410 gt 7074 1041 0 0291 0299 7391 7595 0010 0029 0254 0737 X4 0025 0535 RAD 0220 0310 gt 0985 25019 memmmmmmmm 5588 1874 0005 0020 0127 0508 GLASS SEALANT 0008 0012 0203 0305 0 RAD TYP ILiHiJL4JililLliJLiTl 00370005 0940 i012 lt 0005 0055i0005 0127 13971t0127 1020 0050 1 M39 05081524 ll V 5080 MAX 7 V A 86 94 0150 3810 00250200 MIN 3175 5000 0050 0018i0003 1524 0457 i 0070 MAX BOTH ENDS 0100i0010 0004 0009 0013 0229 0330 TYP ALL LEADS 0102 ALL LEAD TIPS 2540 i 0254 J20AREVM DuallnLine Package J Order Number ADC0801LJ ADC0802LJ ADC0801LCJ ADC0802LCJ ADC0803LCJ or ADC0804LCJ ADC0802LJ883 or 59629096601MRA NS Package Number J20A 0490 0512 12590 13005 zu mmun 0394 0419 10000 10543 D 0 30 TYP LEADNO1 000000000 40 1 2 3 4 5 5 7 a 9 10 f MMAX 0254 0093 0104 2362 2542 0 0004 0012 006370 0102 0305 j 7 0 SEATING f T HE PLANE gt 001670050 A M 0014390020TVP 04064270 1270 035670503 TYP ALL LEADS TYP Mm 0203 M205 REV F SO Package M Order Number ADC0802LCWM ADC0803LCWM or ADC0804LCWM NS Package Number MZOB 34 Physical Dimensions inches millimeters Continued 0092 X 0030 1013 1040 2337 X 0702 MAX DP PIN 1001 IDENT 2573 2042 mmmmmmmmm 0125 0140 00320005 1 00130127 m m RAD G 0004 00127 PIN 1001 105101 03928 0PTIDN1 l 0 WM 1 Lumwmmmm quot 0090 0300 0320 gt m OPTION 2 mam 33912 0000 M 0040 lt 001101112 0 m 0005 o 0005 1524 1010 4 4X m31 l M51 TVP TYP l i 39 139 0145 0200 30 3 1 1 1 7 3 5000 95 15 0000 0015 90 10004 1 1 I l70220 0301 0020 TYP 010010010 1 L 00000005 m 00100003 I I 0040 15240127 quot325 0015 1010 0255 4381 0457 1 0070 0 1 1175 3550 Molded DuallnLine Package N Order Number AD00801LCN AD00802LCN AD00803LCN ADCOBO4LCN or ADCOBOSLCN NS Package Number N20A 35 0500 MIN N20A lREV G 8Bit uP Compatible AD Converters ADC0801ADC0802ADC0803ADC0804ADC0805 Physical Dimensions inches millimeters Continued 0006 D 0350 0000 015 889 ooo 0017i0004 4sz 301445 PIN 1 IDENT 043i010 0065 45 X 165 L 074i008 4 39 L 127 0200 508 quotP 0050 TYP 0029l0003 TYP 031010020 7871051 TYP J SEATING PLANE 0020 gt lt MIN TYP 039010005 05 9911013 TYP 01050015 267t038 TYP 01650180 TYP 419 457 O 0004 010 VZOA REV L Molded Chip Carrier Package V Order Number ADC0802LCV ADC0803LCV or ADC0804LCV NS Package Number V20A LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe National Semiconductor Corporation Arlington TX 76017 Tel 1800 2729959 Fax 1800 7377018 English Tel 49 Italiano Tel 49 1111 West Bardin Road Fax 49 0180530 85 86 Email cnngetevm2nsccom Deutsch Tel 49 0180530 85 85 0180532 78 32 Frangais Tel 49 0180532 93 58 0180534 16 80 National Semiconductor Japan Ltd Tel 810432992309 Fax 810432992408 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel 852 27371600 Fax 852 27369960 National does not assume any respons bility for use of any circuitry described no circuit patent censes are implied and National reserves the right at anyt me without notice to change said circuitry and specificat ons yNational Semiconductor DAC0808DAC0807DAC0806 8Bit DA Converters General Description The DA00808 series is an 8bit monolithic digitaltoanalog converter DAC featuring a full scale output current settling time of 150 ns while dissipating only 33 mW with i 5V sup plies No reference current IREF trimming is required for most applications since the full scale output current is typi cally i1 LSB of 255 IREF 256 Relative accuracies of bet ter than i019 assure 8 bit monotonicity and linearity while zero level output current of less than 4 uA provides 8bit zero accuracy for IREF22 mA The power supply cur rents of the DA00808 series are independent of bit codes and exhibits essentially constant device characteristics over the entire supply voltage range The DA00808 will interface directly with popular TTL DTL or CMOS logic levels and is a direct replacement for the January 1995 MC1508MC1408 For higher speed applications see DACOBOO data sheet Features Relative accuracy i019 error maximum DA00808 Full scale current match i1 LSB typ 7 and 6bit accuracy available DA00807 DACOBOG Fast settling time 150 ns typ Noninverting digital inputs are TTL and CMOS compati ble High speed multiplying input slew rate 8 mAus Power supply voltage range i45V to i 18V Low power consumption 33 mW i5V Block and Connection Diagrams MSB Al A2 A3 A4 A5 A5 A7 I I I o I RANGE CONTROL R2R LADDER Vnsrmo uPu cunnsm Vcc SOURCE PAIR VHEFl lo REFERENCE CURRENT AMP 0 COMPEN TL H 5687 1 SmallOutline Package Io Order Number DACOBOB DACOBO7 or DACOBOG See NS Package Number J 16A M16A or N16A DuallnLine Package 1 NC NOTE 2 iCOMI ElllSATIIJN 2 15 END VREFl l 3 14 VEE VREFll I s 13 v 393 auction 99 SERIES M55 Ill 5 1 L38 7 na lAri A4 a g AB TLH5687 2 Vcc Vnzr m VREF H COMPENSATION NC NOTE 2 GND VEE I0 cavemanoN 16 AB LSB 15 A7 14 A6 13 A5 9 A1 MSB TLH5687 13 Top View Ordering Information ACCURACY OPERATING TEMPERATURE ORDER NUMBERS RANGE J PACKAGE J16A N PACKAGE N16A SO PACKAGE M16A 7bit O CSTAS 75 C DAC0807LCJ 6bit O CSTAS 75 C DAC0806LCJ DAC0808 LCM DAC0807 LCM DAC0806 LCM DAC0808LCN MC1408P8 DACO807LCN MC1408P7 DAC0806LCN MC1408P6 MC1408L7 MC1408L6 Note Devices may be ordered by using either order number 1995 National Semiconductor Corporation TLH5687 RRD B30M115Printed in U S A SJalIGAUOO VCI 8398 90800VGLO800VG80800VCI Absolute Maximum Ratings Note 1 If MilitaryAerospace s ec led device are required Storage Temperature Range 765 Cto 150 C lease contact the National Semicondu tor sales Lead Temp Soldering 10 seconds OfficeDistributors for availability and specifications Dual nLine package plague 250 Power Supply Voltage DuallnLine Package Ceramic 300 C Vac 18VDG Surlace Mount Package 718 V93 Vapor Phase 60 seconds 215 C Digital lnput Voltage v5 v1 2 e 10 V93 to 15 VDG intrared 15 seconds 220 Applied Output Voltage V0 711 V93 to 18VDG Relerence Current 1 4 5 mA ggirjutrleggngatlngs T lt T lt T Relerence Amplilier inputs V14 V15 V33 V55 DACOBOBLC Series MthgrAlgjr 76 Power Dissipation Note 3 1000 mW ESD Susceptibility Note 4 TBD Electrical Characteristics vac 5v0vEE e1 VD VRE R14 2 mA DACOBOB TA essac to 125 c DACOBOBC DAC0807C DAC0806C TA 0 C to 75 C and all digital inputs at high logic level unless otherwise noted symbol Parameter Conditions Min Typ Max Units Er Relative Accuracy Error Relative Figure 4 to Full Scale lo DACOBOBLC LM1408 8 i019 DAC0807LC LM1408 7 Note 5 i 039 DAC0806LC LM14086 Note 5 i 075 Settling Time to Within 12 LSB TA 25 C Note 6 150 ns includes lpLH Figure 5 lpLH lpHL Propagation Delay Time TA 25 C Figure 5 30 100 ns TClo Output Full Scale Current Drilt 20 ppm C MSB Digital input Logic Levels Figure 3 VIH High Level Logic 1quot 2 VDG VIL Low Level Logic 0 08 VDG MSB Digital lnput Current Figure 3 High Level VIH 5v 0 0040 mA Low Level VIL 08V 0003 08 mA 1 5 Relerence lnput Bias Current Figure 3 1 3 HA Output Current Range Figure 3 V55 7 5v 0 20 21 mA VEE 715V0TA 25ac 0 20 42 mA lo Output Current VREF 2000V R14 10009 Figure 3 19 199 21 mA Output Current All Bits Low Figure 3 0 4 HA Output Voltage Compliance Note 2 Er 019 TA 25 C VEE 75v 1R3 1mA 7055 04 V93 V55 Below e10v 750 04 VDG Electrical Characteristics Continued VCC 5V VEE 15 VDC VREF R14 2 mA DACO808 TA 55 C to 125 C DACO808C DACO807C DACO806C TA 0 C to 75 C and all digital inputs at high logic level unless otherwise noted Symbol Parameter Conditions Min Typ Max Units SRIREF Reference Current Slew Rate Figure 6 4 8 mAus Output Current Power Supply 5V VEE 165V 005 27 uAV Sensitivity Power Supply Current All Bits Figure 3 Low lcc 23 22 mA IEE 43 13 mA Power Supply Voltage Range TA 25 C Figure 3 VCC 45 50 55 VDC VEE 45 15 165 VDC Power Dissipation All Bits Low VCC 5V VEE 5V 33 170 mW VCC 5V VEE 15V 106 305 mW All Bits High VCC 15V VEE 5V 90 mW VCC 15V VEE 15V 160 mW Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions Note 2 Range control is not required Note 3 The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX OJA and the ambient temperature TA The maximum allowable power dissipation at any temperature is PD TJMAX TA0JA or the number given in the Absolute Maixmum Ratings whichever is lower For this device TJMAX 125 C and the typical junctiontoambient thermal resistance of the dualinline J package when the board mounted is 100 CW For the dualin line N package this number increases to 175 CW and for the small outline M package this number is 100 CW Note 4 Human body model 100 pF discharged through a 15 km resistor Note 5 All current switches are tested to guarantee at least 50 of rated current Note 6 All bits switched Note 7 Pinout numbers for the DAL080X represent the dualinline package The small outline package pinout differs from the dualinline package Typical Application v 5v 5 M 50000 M53 A1o 1VV o mom1 EF DIGITAL A40 mam lNPUTS VEE l5V TLH5687 3 FIGURE 1 1OV Output Digital to Analog Converter Note 7 Typical Performance Characteristics VCC 5V VEE 15V TA Logic Input Current vs Input Voltage E s 2 E E B 4 S E 2 1 0 712407875 4 20 2 4 6 01012141810 VL 7 LOGIC INPUT VOLTAGE V Output Current vs Output Voltage Output Voltage Compliance 2 0 a E E E I a 395 f S I 9 u 14 111 5 2 2 6 10 14 18 Va A OUTPUT VOLTAGE v Typical Power Supply Current vs VEE DRl IEE WITH 5 1mA I14U2mA POWER SUPPLV CURRENT mil 1 u n 2 44 s n 1o1z14 15 1n zn vEE NEGATIVE POWER suner V OUTPUT VOLTAGEW In AUUTPUT CURRENT mA POWER SUPPLY CURRENT lull 0 0245 25 C unless othenvise noted Bit Transfer Characteristics 14Z u 12 m s a 4 2u z 4 6 31012141511 VL LOGIC INPUT VOLTAGE V Output Voltage Compliance vs Temperature SHADED AREAINDiCATES PERMISSIBLE OUTPUT VOLTAGE RANGE FOR VEE15VI142mA 50 0 50 100 150 TEMPERATURE 3981 Typical Power Supply Current vs Vcc 81012141018 20 V53 POSITIVE POWER SUPPLY V Logic Threshold Voltage vs Temperature 18 16 111 12 1 03 06 04 02 VTquot 4 LOGIC THRESHOLD VOLTAGE vac 0 55 37 19 71 17 35 53 71 89107125 TA TEMPERATURE 01 Typical Power Supply Current vs Temperature ALL 2 2 E Z 1 n D u gt E 2 In a u E E 3950 0 50 100 150 TEMPERATURE quot0 Reference Input Frequency Response 6 4 A 2 E n S 2 L g 4 3 A6 gt 3 gt0 a 3910 m 01 03 1 3 10 IV FREOUENDV1MH1 TLH5687 5 Unless othenvise specified R14 R15 1km C 15 pF pin 16 to VEE RL 50 pin 4 to ground Curve A Large Signal Bandwidth Method of Figure 7 VREF 2 Vpp offset 1 V above ground Curve B Small Signal Bandwidth Method of Figure 7 RL 2500 VREF 5O mVpp offset 200 mV above ground Curve C Large and Small Signal Bandwidth Method of Figure 9 no op amp RL 500 R5 500 VREF 2V V5 100 mVpp centered at 0V MSB A1 39our 4 LMDACUH TLH5687 4 FIGURE 2 Equivalent Circuit of the DACOBOB Series Note 7 Test Circuits DIGITAL INPUTS Vl and I1 apply to inputs A1 A8 The resistor tied to pin 15 is to temperature compensate the bias current and may not be necessary for all applications AN TLH5687 6 FIGURE 3 Notation Definitions Test Circuit Note 7 M88 12 BT IJ I 0A CONVERTER 0 02quot D 0T0 1W OUTPUT ERROR MAX DACIJIIIIII SERIES Vs FIGURE 4 Relative Accuracy Test Circuit Note 7 PHL was 10 us 39 39VW A1 A2 A3 A4 A5 A6 A7 A8 lo K 2 4 8 16 32 64 128 256 v v where K E E OSTPUT and AN 1 if AN is at high level 0 if AN is at low level ERROR l1v1 TL H 5687 7 14V USE RLTO END FOR TURN quotOFFquot MEASUREMENT SEE TEXT is 15l us TVP T0 12 LSB nL5o I PIN no sun 24v 0m DAV 2ch 1k o m CLAMP lEVEl l 01 MP SETTLING TIME o M J T on FIGURE 5 1 k 0 quot 1 39 a 1 FOR SETTLING TIME quot 00 MEASUREMENT ALI ans 4 swncum Low Tl mom f on g 25 pF 7 I TRANSIENT 395 quotF RESPONSE k v 1mm Low CAPACITANCE we FAST REWVEFIV DIODE l 1 tPLM FIGURE 5 Transient Response and Settling Time Note 7 PHL TLH5687 8 6 Test Circuits Continued Vcc VCC 3142 R15 13 5 14 I i I A1 0 VREF n 14 i I A20 1114 vner I I 1115 1k 0 A3 0 7 o a s AN 11 2 15 1k A4 0 o 0 o va mention 2 L A5 070 4 1339 390 LI DACIJBOB As 07 4 quot A7 12 16 v r 1 15 BL 50 SCOPE 2 mA 3 c 3 15 pF SLEWING SEE TEXT FOB VALUES DF 1 TIME dl 1 IV V 11 BL 11 5 TLH5687 10 VEE I I TLH5687 9 FIGURE 7 Positive VREF Note 7 FIGURE 6 Reference Current Slew Rate Measurement Note 7 Vcc Vs 31421115 13 Rs A1 5 4 H14 5 an MC 15 R15 VREF quot 1 l 1 A3 a VB 15 14 Iquot A404 A5 9 museum 2 A1 5 15 NC 10 c 6 o A6 l AZ When VS 0l14 20 mA 3 11 4 LI 7 A70 16 Azo 8 ABO MO DAcusna 13 VREF V5 9 V V 3 I L A501 SERIES 0 CB 0 R14 RS A R0 6 A60 11 A7 12 3 s55 TEXT FOR VALUES or c A O VEE Ro VEE 2 1 4 TLH5687 11 FIGURE 8 Negative vREF Note 7 2 CD 7 6 1351 ovo TLH5687 12 FIGURE 9 Programmable Gain Amplifier or Digital Attenuator Circuit Note 7 Application Hints REFERENCE AMPLIFIER DRIVE AND COMPENSATION The reference amplifier provides a voltage at pin 14 for con verting the reference voltage to a current and a turnaround circuit or current mirror for feeding the ladder The reference amplifier input currrent I14 must always flow into pin 14 regardless of the setup method or reference voltage polarity Connections for a positive voltage are shown in Figure 7 The reference voltage source supplies the full current I14 For bipolar reference signals as in the multiplying mode R15 can be tied to a negative voltage corresponding to the minimum input level It is possible to eliminate R15 with only a small sacrifice in accuracy and temperature drift The compensation capacitor value must be increased with increases in R14 to maintain proper phase margin for R14 values of 1 25 and 5 kn minimum capacitor values are 15 37 and 75 pF The capacitor may be tied to either VEE or ground but using VEE increases negative supply rejection Application Hints Con1inued A nega1ive relerence vol1age may be used il R14 is ground ed and1he relerence vol1age is applied 1o R15 as shown in pin 16 using 1he values ol1he previous paragra h The neg a1ive relerence vol1age mus1 be a1 leas1 4V above 1he VEE supply Bipolar inpu1 signals may be handled by connec1ing 41o a posi1ive relerence vol1age equal 1o 1he peak posi 1ive inpu1 level a1 pin 15 When a DC relerence vol1age is used capaci1ive bypass 1o ground is recommended The 5V logic supply is no1 recom relerence R14 should be decoupled by connec1ing i11o 5V 1hrough ano1her a 2 9 m 3 a w lt m m 2 3 m 5quot m E 3 9 5 3 2 5 m m a 2 9 m E 3 1 pF 1o ground For relerence vol1ages grea1er1han 5V a clamp diode is recommended be1ween pin 14 and ground ll pin 14 is driven by a high impedance such as a 1ransis1or curren1 source none ol1he above compensa1ion me1hods apply and 1he amplilier mus1 be heavily compensa1ed de creasing 1he overall bandwid1h OUTPUT VOLTAGE RANGE The vol1age on pin 4 is res1ric1ed 1o a range ol 7055 1o 04V when VEE 75V due 1o 1he curren1 swi1ching me1h ods employed in 1he DACOBOB The nega1ive ou1pu1vol1age compliance ol1he DACOBOB is ex1ended1o 7 5V where 1he nega1ive supply vol1age is more nega1ive1han 710V Using a lullscale curren1ol 1992 mA and load resis1or ol 25 kn be1ween pin 4 and ground will yield a vol1age o ol 256 levels be1ween 0 and 4980V Floa1ing pin 1 does no1 allec1 1he conver1er speed or power dissipa1ion However1he value ol1he load re i H 39 39 L39 1ime due 4 age swing Values ol RL up 1o 5009 do no1 signilican1ly allec1perlormance bu1 a 25 kn load increases wors1case se11ling1ime1o 12 ps when all bi1s are swi1ched ON Reler 1o 1 e subsequen1 1ex1 sec1ion on Se11ling Time lor more de1ails on ou1pu1 loading OUTPUT CURRENT RANGE The ou1pu1 curren1 maximum ra1ing ol 42 mA may be used only lor nega1ive supply vol1ages more nega1ive1han 78V e1o1he increased vol1age drop across 1he resis1ors in 1he relerence curren1 amplilier ACCURACY Absolu1e accuracy is 1he measure ol each ou1pu1 curren1 level wi1h respec1 1o i1s in1ended value and is dependen upon rela1ive accuracy and lullscale curren1 dril1 Rela1ive 39 e measure ol each ou1pu1 curren1 level as a lrac1ion ol1helullscale curren1 The rela1ive accuracy ol1he ACOBOB is essen1ially cons1an1 wi1h 1empera1ure due 1o Iau u 1he excellen11empera1ure1racking ol1he monoli1hic resis1or ladder The relerence curren1 may dril1 wi1h 1empera1ure causing a change in 1he absolu1e accuracy ol ou1pu1 cur ren1 However 1he DACOBOB has a very low lullscale cur ren1 dril1 wi1h 1empera1ure The DACO 8 series is guaran1eed accura1e1o wi1hin 12 LSB a1 a lullscale ou1pu1 curren1 ol 1992 mA This corre sponds 1o a relerence amplilier ou1pu1 curren1 drive 1o 1he ladder ne1work ol 2 mAywi1h1he loss ol 1 L88 8 pA which d The inpu1 curren1 1o pin 14 has a guaran1eed value ol be1ween 19 and 21 mA allowing some misma1 h in 1he N curren1 source pair The accuracy 1es1 circui1 is shown in Figure 4 The 12 bi1 conver1er is calibra1ed lor a lullscale ou1pu1 curren1 ol 1992 mA This is an op1iona s1ep since 1he DACOBOB accu racy is essen1ially1he same be1ween 15 and 2 Then 1he DACOBOB circui1s lullscale curren1 is 1rimmed 1o 1he same value wi1h R14 so 1ha1 a zero value appears a11he error amplilier ou1pu1 The coun1er is ac1iva1ed and 1he error band may 39 layed on an oscilloscope de1ec1ed by compara1ors or s1ored in a peak de1ec1or Two 8bi1 D1oA conveners may no1 be used 1o cons1ruc1 a 16bi1 accuracy D1oA conver1er 16bi1 accuracy implies a 1o1al error ol VZ ol one parl in 65536 or i000076 A which is much more accura1e1han1he 0019 specilica 1ion provided by 1he DACOBOB MU LTIPLYING ACCURACY The DACOBOB may be used in 1he mul1iplying mode wi1h 8bi1 accuracy when 1he relerence curren1 is varied over a range ol 2561 ll 1he relerence curren1 in 1he mul1iplying mode ranges lrom 16 pA 1o 4 mAy1he addi1iona error con L n L m 1han 16 pA TL racy when relerred1olullscale A mono1onic conver1er is one which supplies an increase in curren1lor each incremen1 in 1he binan word Typically1he DACOBOB is mono1onic lor all values ol relerence curren1 above 05 mA The recommended range lor opera1ion wi1h a DC relerence curren1 is 051o 4 mA SE39I39I39LING TIME The wors1case swi1ching condi1ion occurs when all bi1s are swi1ched ON which corresponds 1o a low1ohigh 1ransi1ion lor all bi1s This 1ime is 1ypically 150 ns lor se11ling1o wi1hin 12 L88 lor 8bi1 accuracy and 100 ns1o 12 L88 lor 7 and 6bi1 accuracy The 1urn OFF is typically under 100 ns These 1imes apply when RL 5009 and Co 25 pF Ex1ra care mus1 be 1aken in board layou1 since 1his is usually 1he dominan1 lac1or in sa1islac1on 1es1 resul1s when mea suring se11ling 1ime Shorl leads 100 pF supply bypassing lor low lrequencies and minimum scope lead leng1h are all manda1ory Physical Dimensions inches millimeters T 9733 W 16 9 E 0220 0310 559787 l 0025 V v39 V V 39v39 k L LJ R 0 64 1 a 0005 0020 R 013 051 WP 003720005 TN 0 005 O39QHO39V 0290 0320 39 00550005 737813 0 13 139400 3 WP GLASS SEALANT MIN TYP 013200360 P J TY 0200 051152 l l b l I 503 457 MAX TYP 0 l 0150 l I y 39 K 38 1001 TYP 01010002 025 i 005 quotP 01250200 TYP 90 i4 950150 318 5231 TYP WP 030 i i 203lMAx 39 051 0410 001320005 gt 39 lt BOTH ENDS MMOIUB TYP 787 W41 MMREV i 0100 t 0010 WP 254 1 025 DuallnLine Package Order Number DAC0807 or DAC0806 NS Package Number J16A 0386 0394 9004 1000 15 15 14 13 12 11 10 9 0220 0244 30 5191 6198 TYP 0 0 0 0 0 0 LEAD No1 1 2 3 4 5 6 7 8 l IDENI MAx 2 4 0150 0157 3010 3088 0010 0020 M 02544500 5 13461153 N 0 MAX TYP 0102 0254 ALL LEADS LEE l l mu j F31 w L w 1 SEATING QT T T PLANE 000070010 0 mo 050 m 0 050 0014 0020 m 02034254 0 355 1270 035154500 1w ALL LEADS MOB 13927quot TYP 0004 TYP ALL LEADS 0000 gt lt TYP 0203 M16A REV H ALL LEAD TIPS Small Outline Package Order Number DAC0806LCM DAC0807LCM or DAC0808LCM NS Package Number M16A DAC0808DAC0807DAC0806 8Bit DA Converters Physical Dimensions inches millimeters Continued 0043 0370 0000 2141 2210 M 2230gt I I 2337 mm DIA NOM IE E II El III II E El 2X PIN 111011051111 0350 0127 0200 N 7112 0030 Iii Ill Ill L I Iii Iii IE 3 mm 39 0762 0300 0320 MA 0040 7020 0120 0005 0060 m 0130 0005 1051 1524 39TYP I 130230127 i LJ J I I I I39 0145 0200 3003 5000 05 5 0009 0015 9 0020 0229 0381 0075 10015 gt 1905 t0381 30 39 0100 0010 8255 1016 39 0301 2540 0254 H 00100003 0425 0140 3950 T 1045710070 3175 1555 lt N16AREV E DuallnLine Package Order Number DACOBOB DACOBO or DAC0806 NS Package Number N16A LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor National Semiconductor Corporation Europe 1111 West Bardin Road Arlington TX 76017 Tel 1800 2729959 Fax 1800 7377018 2 X N 49 0180530 85 86 Email cnngetevm2nsccom Deutsch Tel 49 0180530 85 85 English Tel 49 0180532 78 32 Frangais Tel 49 0180532 93 58 Italiano Tel 49 0180534 16 80 National Semiconductor National Semiconductor Hong Kong Ltd Japan Ltd 13th Floor Straight Block Tel 810432992309 Ocean Centre 5 Canton Rd Fax 810432992408 Tsimshatsui Kowloon Hong Kon Tel 852 27371600 Fax 852 27369960 National does not assume any respons bility for use of any circuitry described no rirrnit nalenl quot 4 and 39 me right at anytme without notice to change said circuitry and specificatons


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